Analog Integrated Chip Design

Ke-Horng Chen
NCTU EE
2011 Autumn

LAB 912

Analog Integrated Chip Design

Teaching Material:
Text Book
Design of Analog CMOS Integrated Circuits, by Behzad
Razavi, McGRAW-HILL, 2001

References
CMOS Analog Circuit Design, by Phillip E. Allen, Oxford
University Press, 2002
Analysis and Design of Analog Integrated Circuits, Paul R.
Gray, John Wiley & Sons, Inc., 2001

Grade
50% Homework
50% Mid-exam, Final-exam

TA: , , , (912)
English TA time: Monday AM10:00~12:00

LAB 912

Outline

Introduction
Basic MOS Device Physics
Single-Stage Amplifiers
Differential Amplifiers
Passive and Active Current Mirrors
Frequency Response of Amplifiers
Noise
Feedback
Operational Amplifiers
Stability and Frequency
Voltage Reference Circuits
Switched-Capacitor Circuits

LAB 912

Introduction

In the past two decades,

CMOS technology has
rapidly embraced the
field of the analog
integrated circuits,
providing low-cost,
high-performance
solutions and rising to
dominate the market

While silicon bipolar and III-V device still find niche applications,
only CMOS processes have emerged as a viable choice for the
integration of todays complex mixed-signal systems
LAB 912

Why Analog ?

Processing of natural signals

Digital communication

Attenuation and distortion of

data through a lossy cable

Use of multi-level signaling

to reduce the required
bandwidth

LAB 912

Why Analog ? (contd)

Disk drive electronics

Wireless receivers

Sensors

Microprocessors and memories

High-speed (digital) circuit

design is in fact analog design

Optical receiver

LAB 912

Why is analog design difficult?

Digital circuits entail primarily one trade-off between speed and

power dissipation
Analog design must deal with a multi-dimensional tradeoff consisting
of speed, power dissipation, gain, precision, supply voltage, etc.

With the speed and precision required in processing analog signals, analog
circuits are much more sensitive to noise, crosstalk, and other interferers
than are digital circuits
Second-order effects in devices influence the performance of analog
circuits much more heavily than that of digital circuits

The design of high-performance analog circuits can rarely be

automated, usually requiring that every device be hand-crafted.
Despite tremendous progress, modeling and simulation of many
effects in analog circuits continue to pose difficulties, forcing the
designers to draw upon experience and intuition when analyzing the
results of a simulation
Developed and characterized for digital applications, such
technologies do not easily lend themselves to analog design,
requiring novel circuits and architectures to achieve a high
performance
LAB 912

Comparison of Analog and Digital Circuits

Analog Circuits

Signals are continuous in amplitude and can be

continuous or discrete in time
Designed at the circuit level
Components must have a continuum of values
Customized
CAD tools are difficult to apply
Requires precision modeling
Performance optimized
Irregular block
Difficult to route automatically
Dynamic range limited by power supplies and
noise (and linearity)

Digital Circuits

Signal are discontinuous in amplitude and

time-binary signals have two amplitude states
Designed at the systems level
Component have fixed values
Standard
CAD tools have been extremely successful
Timing models only
Programmable by software
Regular blocks
Easy to route automatically
Dynamic range unlimited

LAB 912

Skills Required for Analog IC Design

In general, analog circuits are more complex than digital

Requires an ability to grasp multiple concepts simultaneously

Must be able to make appropriate simplifications and
assumptions
Requires a good grasp of both modeling and technology
Have a wide range of skills - breadth (analog only is rare)

Be able to learn from failure

Be able to use simulation correctly

Simulation truths:

(Usage of a simulator) x (Common sense) Constant

Simulators are only as good as the models and the knowledge of

those models by the designer
Simulators are only good if you already know the answers

LAB 912

Analog Integrated Circuit Design

What is Analog IC Design?

Analog IC design is the successful

implementation of analog circuits
and systems using integrated
circuit technology

Unique Features of Analog IC Design

Geometry is an important part of the design

Electrical Design Physical Design Test Design

Usually implemented in a mixed analog-digital circuit

Analog is 20% and digital 80% of the chip area
Analog requires 80% of the design time
Analog is designed at the circuit level
Passes for success: 2-3 for analog, 1 for digital
LAB 912

10

The Analog IC Design Flow

LAB 912

11

Basic MOS Device Physics

LAB 912

Introduction

In studying the design of integrated circuits, one of two

extreme approaches can be taken:

Begin with quantum mechanics and understand solid-state,

semiconductor device physics, device modeling, and finally the
design of circuits
Treat each semiconductor device as a black box whose behavior is
described in terms of its terminal voltages and currents and design
circuits with little attention to the internal operation of the device

LAB 912

13

General considerations

MOSFET as a switch

If the gate voltage, VG, is high, the transistor

connects the source and the drain together
If the gate voltage, VG, is low, the transistor
isolates the source and the drain

MOSFET structure

LAB 912

14

MOS device

Simple NMOS device

Cross section of CMOS n-well technology

MOS symbols

Simple PMOS device

LAB 912

15

Operation of MOSFET

A MOSFET driven by a gate voltage

Onset of inversion

Formation of inversion layer

Formation of depletion region

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16

Threshold voltage

In semiconductor physics, the VTH of an NFET is defined as the

gate voltage for which the interface is as much n-type as the
substrate is p-type
The threshold voltage can be provided that

VTH MS 2F

Qdep
Cox

The work function is defined as the energy

required to remove an electron from Fermi
level Ef to a position just outside the material
(the vacuum level)

MS is the difference between the work functions of the polysilicon

gate and the silicon substrate MS F substrate F gate
F = (kT / q)ln(Nsub / ni), q is electron charge, Nsub is the doping
concentration of the substrate
Qdep is the charge in the depletion region
Cox is the gate oxide capacitance per unit area
LAB 912

17

I/V characteristics Triode region

Condition: VDS VGS VTH

(VD VG VTH)

Equal source and drain voltage

Qd WCox VGS VTH , Cox : F m

Derivation

Unequal source and drain voltage

Qd x WCox VGS V x VTH

I D Qd x v WCox VGS V x VTH v WCox VGS V x VTH n

x 0

I D dx

VDS

V 0

I D nCox

dV x
dx

WCox n VGS V x VTH dV

W
W
1 2
1
2
V
V
V
V
and
I
C
V
V
,

GS
TH
DS
DS
D ,max
n ox
GS
TH
L
L
2
2

LAB 912

18

I/V characteristics Triode region (contd)

Drain current versus drain-source

1
W
2
voltage
I D ,max nCox VGS VTH
2
L
I D nCox

W
1 2
V
V
V
VDS

GS
TH
DS

L
2

Linear operation in deep triode region

With the condition VDS << 2(VGS VTH)

deep triode region

Ron
LAB 912

1
W
nCox VGS VTH
L

19

I/V characteristics Saturation region

Condition: VDS VGS VTH (VD VG VTH)

Saturated MOSFETs operating as

current sources

Pinch-off behavior

ID

LAB 912I D

1
W
nCox VGS VTH 2
2
L

1
W
2
n Cox ' VGS VTH 20
2
L

Transconductance

1
W
n Cox ' VGS VTH 2
2
L

For amplification purposes, the transconductance of the device is

calculated
gm

I D
W
|VDS constant n Cox VGS VTH
VGS
L

2 nCox

ID

2I D
W
W
, where =nCox
I D 2I D
L
VGS VTH
L

MOS transconductance as a function

W
g m n Cox VGS VTH
L

g m 2 nCox LAB I912

D
L

gm

2I D
VGS VTH

21

Conceptual visualization of saturation and

triode regions
Saturation

Edge

of Triode Region

Saturation

Edge

of Triode Region

LAB 912

22

Second-order effects
1.

Body effect

VTH VTH 0
where

2F VSB 2F

2q Si N sub / Cox

denotes the body effect coefficient

No

body effect

LAB 912

Body

effect

23

Second-order effects (contd)

Example: Source follower with (a) no body effect and (b) body
effect

no body effect

body effect

(a) Ignore body effect:

As Vin varies, Vout closely follows the input because the drain current
remains equal to I1
1
W
2
It can be written by
I1 nCox Vin Vout VTH

LAB 912

24

Second-order effects (contd)

Channel-length modulation

2.

4:1

ID

1
W
n C o x ' V G S V T H
2
L

1
1
1
1

(1 L / L ) 1
(1 L / L )
(1 V D S )
L' L
L
L

L is a function of VDS
Writing L= L L, i.e., 1/L (1+ L/ L)/L, and assuming L/L=VDS

ID

1
W
2
nCox VGS VTH 1 VDS
2
L

: the channel-length modulation coefficient

LAB 912

25

Second-order effects
(contd)

I D nCox

W
1 2

V
V
V
VDS

GS
TH
DS

2
L

constant

3.

Subthreshold conduction, VGS < VTH

I D I o exp

VGS
VT

where > 1 is a nonideality factor

and VT kT / q
If W increases while ID remains constant,
then VGS VTH and the device enters the
subthreshold region

ID

g
As a result, the transconductance is calculated to m V
T

revealing that

MOSFETs are inferior to bipolar transistors

The exponential dependence of ID upon VGS in subthreshold operation may
suggestion the use of MOS devices in this regime so as to achieve a higher
gain
However, since such conditions are met by only a large device width or
low drain current, the speed of subthreshold circuits is severely
limited
LAB 912
26

MOS devices

Birds eye of a MOS device

Show the overlap between the

source or drain and the gate

Vertical views of a MOS device

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27

MOS device capacitances

Oxide capacitance between the gate and the channel, C1 = WLCox

Depletion capacitance between the channel and the substrate,
C2 WL q Si N sub / 4F
Capacitance due to the overlap of the gate poly with the source and
drain areas, C3 and C4

The overlap capacitance per unit width is denoted by Cov (per unit width)

Junction capacitance between the source/drain areas and the substrate

Bottom-plate capacitance associated with the bottom of the junction,

C j C j 0 / 1 VR / 2F
Note: C j : F / m 2
Sidewall capacitance due to the perimeter of the junction, CjSW (note: CjSW :
F/m)
m

LAB 912

28

MOS device capacitances (contd)

Example: Calculate the source and drain junction capacitances

Folded structure:
CDB

W
W

EC j 2 E C jsw
2
2

CSB 2 EC j 2 E C jsw
2

WEC j 2 W 2 E C jsw

C DB C SB WEC j 2W E C jsw

The geometry of the folded structure in Fig. (b) exhibits substantially

less drain junction capacitance than that in Fig. (a) while providing the
same W/L
LAB 912

29

Variation of CGS and CGD versus VGS

C7

Example

OFF: CGB=[C1C2/(C1+C2)]+2C7

ON: CGB=2C7

VTH=0.6V

VX is higher than 1V

C7

For VX 0, M1 is in the triode region,

CEN CEF = (1/2)WLCox + WCov, and CFB is
maximum

Why?

LAB 912

Triode

Saturation

30

Voltage dependence of CGS, CGD, and CGB as a

function of VGS with VDS constant and VBS=0
OFF
CGB C1 2C7 Cox Weff Leff CGBO Leff

CGS C3 Cox LD Weff CGSO Weff

CGD C4 Cox LD Weff CGDO Weff

Saturation

C1+2C7
C3+2/3C1
C3+1/2C1

CGB 2C7 CGBO Leff

CGS C3 3 C1 Cox LD 0.67 Leff Weff

CGSO Weff 0.67Cox Weff Leff

CGD C4 Cox LD Weff CGDO Weff

C3,C4
2C7

N o n satu r ated
C G B 2 C 7 C G B O L eff

1
C 1 C ox L D 0 .5 L eff
2
C G S O 0 .5 C o x L ef f W eff

1
C 1 C o x L D 0 .5 L eff
2
C G D O 0 .5 C o x L eff W eff

LAB 912

C GS C 3

C GD C 4

eff

eff

31

NMOS Terminal Capacitances, L=0.35um

mn dn gn 0 0 nch L=0.35u W=10u
vdn dn 0 dc 0.5V
vgn gn 0 dc 1.2V
m1 dn gn 0 0 nch L=0.35u W=10u geo=1
m2 dn gn 0 0 nch L=0.35u W=10u geo=2
m3 dn gn 0 0 nch L=0.35u W=10u geo=3
.op
.dc vgn 0V 3.5V 10mV
.probe
+ cgs = par('-cgsbo(mn)')

OPTION DCCAP: turn on capacitance

+ cgd = par('-cgdbo(mn)')
calculations for a DC sweep
+ cdtot = par('cddbo(mn)')
$ cgd + cdb
+ cgtot = par('cggbo(mn)')
$ cgs + cgd + cgb
+ colgs = par('covlgs(mn)')
$ col at source
+ colgd = par('covlgd(mn)')
$ col at drain
.options dccap post=2 brief
.option ingold=2 numdgt=2 accurate
.option absmos=1e-15 absv=1e-12 relmos=1e-7 absi=1e-14
.lib 'mm0355v.l' TT
LAB 912
32
.end

Behavior of MOS Device as a Capacitor

Accumulation region: VG<0:

Weak inversion: 0<VGS<VTH:

The negative potential on the gate attracts

the holes in the substrate to the oxide
interface
A capacitor has a unit-area capacitance of
Cox because the two plates of the capacitor
are separated by tox

A depletion region begins to form under the

oxide
The capacitance consists of the series
combination of Cox and Cdep

Strong inversion: VTH<VGS:

The capacitance returns to Cox

LAB 912

33

Behavior of MOS Device as a Capacitor

(contd)

Bulk tuning of the

polysilicon-oxide-channel
capacitor (0.35m CMOS)

C m ax / C m in 4
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34

MOS small-signal model

Basic MOS small-signal model

gm

I D
VGS

Channel-length modulation represented by

a depend current source
VDS

ro

Channel-length modulation represented by

a resistor

VDS
1
1
1

I D
I D VDS 1 C W V V 2 I D
GS TH
n ox
L
2
LAB 912

35

MOS small-signal model (contd)

Body effect represented by a dependent current source

In the saturation region, gmb can be expressed as

V
I
W
g mb D nCox VGS VTH TH
VBS
L
VBS
gm
VTH VTH
1 2

2 F VSB
VBS VSB 2
I

Thus
g mb D g m
gm
VBS
2 2F VSB

where g mb g m

LAB 912

36

MOS small-signal model (contd)

Example: Sketch gm and gmb of M1 as a function of the bias

current I1

g mb g m
2 2F VSB

VX

VSB

Since gm 2nCox W LI D , we have g m I1

The dependence of gmb upon I1 is less straightforward

As I1 increases, VX decreases and so does VSB

LAB 912

37

MOS small-signal model (contd)

Complete MOS small-signal model

Reduction of gate resistance by folding

Req=RG/4
LAB 912

38

MOS SPICE models

LAB 912

39

MOS SPICE models (contd)

The parameters of Spice models are defined as below:

LAB 912

40