980

IEEE TRANSACTIONSON CIRCUITS AND SYSTEMS, VOL.

36, NO. 7, JULY 1989

Digital Phase-Locked Loop with

Jitter Bounded
STEPHEN M. WALTERS, SENIOR MEMBER,
IEEE,

AND

TERRY TROUDET

Abstract-A design of an all-digital phase-locked loop (DPLL) with

direct frequency synthesis is proposed in order to generate signals that
satisfy preimposed requirements on jitter over any given range of frequencies. Control of the jitter is obtained by means of a frequency-phase
window comparator which compares the bit overflow/underflow of the
direct synthesis (accumulator-type) DCO output to a fixed frequency-phase
window, and thus ensures that the jitter of the generated signal is bounded
within the preassigned limits. Acquisition of frequency and phase lock are
achieved through successive approximations, which reduces the acquisition
time of the DPLL. The concept has been confirmed through laboratory
experiments to synthesize frequencies from 10 Hz to 1.544 MHz with a
6.25-percent upper bound on the jitter.

P i i l

At

I. INTRODUCTION

Manuscript received January 28, 1988; revised October 21, 1988. This
paper was recommended by Associate Editor C. A. T. Salama.
The authors are with the Navesink Research and Eneineerine" Center.
Bell Communications Research, Red Bank, NJ 07701-7620.
IEEE Log Number 8927735.

Lock:'EO=
P

CHARACTERISTIC common to all digital phaselocked loops (DPLL's) [1]-[15] is that they generate
a signal which presents some jitter with respect to an ideal
signal operating at the same frequency. The problem of
diminishing the jitter has been a very challenging question.
In the domain of digtal telecommunications, it is of prime
importance to generate clock signals over wide dynamic
ranges of frequency that are as jitter-free as possible in
order to ensure proper data transmission, clock recovery,
and synchronization. Although many DPLL designs have
been proposed in order to diminish the jitter, they often
require complicated implementations and limit the dynamic range of the DPLL.
As an attempt to circumvent these difficulties, the present work introduces a simple frequency-phase window
comparator in conjunction with an accumulator-type digital controlled oscillator (DCO) and proposes a DPLL
architecture where the jitter systematically satisfies preimposed requirements. The demonstration of this arrangement is organized as follows. A general review of the
DPLL architecture and the functionality of its building
blocks is given in Section 11. Section I11 presents a jitter
performance analysis of the specific accumulator-type
DCO. The frequency-phase window comparator concept
for an accumulator-type DCO is introduced in Section IV,
while Section V describes the physical implementation of
the DPLL and its relation to telecommunications applications.

I:

51
9

Fig. 1. General structure of a DPLL.

11. GENERAL
STRUCTURE
OF A DIGITAL
PHASE-LOCKED
LOOP
In its general form, a DPLL consists mainly of a frequency generator (the digital controlled oscillator), a
phase-frequency comparator, and a filter interconnected
as shown in Fig. 1. A reference clock fref is divided by an
integer q, producing a signal fref/qto which the DCO will
be locked. The function of the DCO is to generate a wide
range of frequencies from a system clock which operates at
a frequency f, much hgher than the DCO output frequency fDco. Before being fed back to the phase-frequency
comparator, the DCO output is divided by an integer value
p , so that the frequency fDco/p is actually compared with
fref/q. Since this signal at the input of the phase-frequency
comparator will be quite often referred to throughout the
text, it is most convenient to call it the f, clock with
frequency fref/q.The result of t h s comparison is low-pass
filtered and fed back to the DCO, whch adjusts the DCO
output frequency to reduce the error. The low-pass filter is
a critical element in determining important parameters
such as acquisition time, jitter, and stability. Assuming a
proper design, the feedback mechanism converges and the
DCO output frequency reaches steady state, where

It is the purpose of the following sections to introduce a

DPLL which will synthesize bounded-jitter signals with
rates that are fractional ratios of fief, as shown in (1). Since
the ability of the loop to produce the desired frequency

0098-4094/89/0704-0980$01.00

01989 IEEE

981

WALTERS AND TROUDET: DIGITAL PHASE-LOCKED LOOP

fwO= m.s.b.
Ideal

Fig. 2. Schematic illustration of jitter.

( p / q ) f r e r depends primarily upon the nature of the DCO

used, a decisive factor for the design of the loop is the
choice of the DCO. The choice of the DCO is crucial not
only to generate an output frequency which is, on the
average, equal to the desired frequency, but also to keep
the jitter of the output signal within acceptable limits. This
is illustrated in the next section, where the influence of the
input/output frequencies on the jitter is discussed for an
accumulator-type DCO. According to the usual definition,
the jitter of the DCO output is defined as the maximum
absolute deviation (expressed in time or as a fraction of a
pulse) of a pulse edge of the DCO output from an ideal
waveform operating at the desired frequency ( p / q ) f r e f ,
assuming an initial synchronization. A schematic illustration of jitter is given in Fig. 2.
From the above definition of the jitter, it is clear that,
for a frequency of the DCO output slightly different from
( p / q ) f r e f , the jitter will keep accumulating with time,
ultimately reachmg 100 percent or, equivalently, one pulse
discrepancy, unless the DCO output is properly synchronized with the f, clock by periodically clearing the accumulator (see Fig. 3). In addition to the fact that synchronizing the DCO by clearing the accumulator will bound
the jitter, the overall operation of the DPLL becomes
much simpler to analyze since a predictable number of
accumulations will occur during each cycle of the f, clock.
This will allow the frequency/phase of the DCO output
signal to be compared with the f, clock during each cycle
of f,, and the result of the comparison to be available at
the input of the DCO at the very beginning of the next
cycle, thus providing accurate readjustments of the DCO.

I 3 1I 6 1 9 1 1 2 1 1 5 1 2 1 5 1
1.
I

.
I

.
I

1.

1,

1,

1.

foco :2

1
1

4
1

7~ 1 110 1~1 3 41 1 ~
61
1

1.

Fig. 4. Output signal of 4-bit accumulator-type DCO.

denotes the time when the latch is cleared by a SYNC pulse

and if T, = l/f, denotes the period of the system clock, the
value at the output of the adder at time 1, = to nT,, i.e.,
after the nth rising edge of f,, is Zy='=,k= nk modulo 2 N .
The DCO output is given by the most significant bit of the
output of the latch, so that the DCO output frequency is
given by the formula

In effect, this latch acts as a phase register which indicates

the phase +(t,) of the DCO output signal. As such, the
above adder-latch arrangement constitutes a frequency
In order to demonstrate the ability of the accumulator- generator which operates at a fixed rate for given values of
type DCO to operate in conjunction with a phase-frequency k and f,. A key point is that (3.1) reads as fDco = kA,
comparator, it is best to first describe its dynamic charac- with A, = f , / 2 N , so that a large set of discrete frequencies
teristics for a general mode of operation where the gener- can be generated exactly by this accumulator-type DCO.
ated signals are only required to present on the average a The operations involved can be illustrated by the diagram
given frequency without any constraint at all on the jitter. of Fig. 4 for the example of a 4-bit adder with the value
This will subsequently clarify the analysis of the perfor- k = 3. At the n th rising edge of the system clock, the DCO
mance of the accumulator-type DCO when the jitter is output is given by the most significant bit of Cy=Ik =
externally bounded by the phase-frequency comparator.
3n modulo 24. During 16 pulses of f,, there are therefore
three rising edges of the DCO output so that
A . General Operational Conditions
111. ACCUMULATOR-TYPE
DCO: JITTER
PERFORMANCE
ANALYSIS

With the accumulator-type DCO, the DCO output is

generated by successively adding the value of an integer k
to itself at the high frequency rate f, of a system clock
[l], [2] as indicated in Fig. 3. At each rising edge of f,, the
output of an N-bit adder is latched and added to k . If to

which verifies the general formula (3.1) for N = 4 and

k = 3. From Fig. 4, it appears that the first DCO output
cycle (starting at Z o = 0000 modulo 16) lasts over six
system clock periods, whereas the second and third DCO

982

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL.

output pulses consist of only five system clock periods.

More generally, the duration of the low output signal may
indeed differ from the duration of the high input signal by
one system clock period T,. In contrast to the example of
Fig. 4, whose only purpose is to illustrate the DCO operations, fDco << f, in the practical range of applications of
the DCO, so that the DCO itself produces in the generated
signal an intrinsic jitter f D c o / f , much smaller than 1. This
is equivalent to quantization error (noise) due to sampling
the ideal waveform at f,.
In order to generate the desired frequency
(3.3)
this adder-latch arrangement is operated in conjunction
with a frequency comparator whch searches for a value of
k that leads to p pulses of the DCO output during two
successive rising edges of the f , clock. The notation (fDco)
has been adopted to account for the fact that, for a gven
k , the DCO output is being Synchronized (by clearing the
accumulator) at each rising edge of f, and would have a
different average frequency if it were not synchronized.
For given values of f , and f,, it is possible to find at
least one integer k which leads to less than ( p + 1 / 2 ) and
more than ( p - 1/2) DCO clock periods during a single
cycle of the f, clock, if the number of bits of the accumulator, N , satisfies the inequality

36, NO. 7, JULY 1989

simply ensure that the generated signal will have on the

average the desired frequency (i.e., within a k50 percent
margin of jitter).
In order to analyze the effect of the jitter upon these
operational conditions, let us first recall that the signal of
the DCO output is quantized in terms of system clock
periods
since any transition of the DCO output can
only occur at a transition of the system clock through the
latch defined in Fig. 3. From definition (3.1) of f D c o , one
pulse of the system clock represents the fraction fDco/fs
= k / 2 N of one pulse of the DCO output. As a result, over
any given dynamic range of frequencies, the upper bound,
j , on the jitter, which is the maximal deviation in time
between the DCO output and an ideal waveform operating
at the same frequency, cannot be brought below the intrinsic limit k / 2 N , which represents the quantization noise of
the accumulator-type DCO. Equivalently, for U priori given
upper bound j on the jitter, the DPLL arrangement can
only generate frequencies over the dynamic range defined
by the inequality

f DCO

j&.

(3.7)

Therefore, the stronger the requirement on the jitter, the

lower the maximum frequency that can be generated by
such an arrangement. Since it is necessary in practical
applications for the jitter of the generated signal to be
much less than unity (usually less than 10 percent), condition
(3.7) also implies that fDco << f,, as anticipated in
sfs
N > log, 7.
(3.4) Section III-A.
/ref
The main question that remains is whether it is possible
An N-bit accumulator can generate a frequency f D c o = to generate from t h s accumulator-type DCO a signal
( k / 2 ) f , only if the system clock period T, is longer than whch has the desired average frequency and presents a
the critical data path delay, T( N ) , encountered throughout jitter less than an a priori fixed upper bound j . With the
the adder. The wider the adder, the longer the propagation help of condition (3.4) whch ensures the existence of a
delay, so that the delay T ( N ) increases with the number of DCO output with the desired average frequency pfre,/q,
bits, N . As a result, the DCO can operate properly only if one can derive the expression for the lowest permissible
that can be imposed on the jitter, i.e.,
constraint jmin
(3.5)
J Jmm
(3.8a)

Instead of regarding, in (3.4), the rate fref as a parameter

and the number of bits, N , as a variable, it is possible to
consider N as a parameter and the rate fref of the input
frequency as a variable. Thus, given an N-bit-wide adder,
fractional rates of a reference frequency fref can be generated by the accumulator only if

with

As has been demonstrated previously, +50 percent is

the maximum tolerable jitter (corresponding to ( p f 1/2)
DCO output periods respectively during one period of the
fq clock) in order for the frequency of the accumulator-type
DCO output to be on the average equal to pfrer/q. This
provided fs be bounded by inequality (3.5). This means condition indicates that jmi,given by (3.8b) must be
that, for a given accumulator-type DCO, fractional rates of smaller than 1 / 2 , which leads as expected to the general
the transmission rate fief can be generated only if fref is operational condition (3.4) of the accumulator-type DCO.
fast enough. This point will be quantitatively discussed at Since the accumulator-type DCO can a generate integer
the end of this section.
multiples of frer/q, conditions (3.8) put a lower bound on
the frequencies fDco that can be generated with less than
B. Performance with Periodic Synchronization
100 X j percent jitter:
The lower bounds on the width of the accumulator and
the rate of the reference signal presented above do not
(3.9)
discriminate between the jitter of the DCO output, but

983

WALTERS A N D TROUDET: DIGITAL PHASE-LOCKED LOOP

In summary, the combination of (3.7) and (3.9) shows that

this DCO can generate signals over the dynamic range of
frequencies
fs

j2N+1

<fDcO<Jfs

Phase
Window

(3.10)

with a jitter less than a preimposed limit j .

IV. THEFREQUENCY-PHASE
WINDOW

1I

In order for the DCO to generate a signal that has the

desired average frequency p f r e f / q ,there must be p rising
edges of the DCO output during one period q/fref of the
f , clock. The frequency comparator consists therefore of a
down-counter and control logic which indicate that fDco
is too fast when the counter counts more than p pulses
and too slow when the counter counts less than p pulses
between two rising edges of f,. It is clear the p is the
number of overflows of the phase register (accumulator
latch) during one period of the reference clock f,, and that
the phase of the DCO output signal is given by the value
of the phase register after each overflow preceding a rising
edge of f,.
Only when the counter output is exactly equal to 0 does
the DCO output have the correct average frequency (3.3).
In the latter case, knowledge of the jitter can be obtained
from the values of the bits of the phase register at each
rising edge of the f, clock. When the DCO output frequency is, on the average, equal to pfrer/q, an upper
estimation of the jitter is given by the absolute maximum
deviation of the DCO output signal from an ideal waveform which would operate at the desired frequency p f r e r / q
with a high-to-low transition at each rising edge of the fq
clock when the phase register is cleared. It is therefore
possible to generate signals which satisfy preimposed requirements on the jitter by constraining the value of the
phase register, which defines the phase of the DCO output,
to be within a preassigned phase window. A synthesized
signal with bounded jitter can be obtained via an easily
implementable architecture by requiring that the n most
significant bits of the phase register all be equal, leading to
the upper bound j = 1/2" on the jitter. When the n most
significant bits of the phase register are all equal to zero,
the value of the accumulator output is smaller than 2N-"
and corresponds to a maximal phase advance of 1/2" of a
pulse. When the n most significant bits of the phase
register are all equal to 1, the value of the accumulator
output is larger than ( 2 N - 2 N - n ) and corresponds to a
maximal phase delay of 1/2" of a pulse. As a result, when
there are exactly p pulses of the DCO output signal during
one period of the f, clock, the jitter is sure to be less than
1/2" if the edge of the final state of the DCO phase
register falls within the phase window at each rising edge
of f,. Fig. 5 represents the eight phase states of the three
most significant bits of the DCO output, and the corresponding phase window which lies between T45" leading
to a maximum jitter of l / 2 3 . More generally, there are
2 N - " / k sectors, or transitions of the system clock, above

Fig. 5. Phase-frequency window for 100/2" percent maximum jitter

with n = 3.

Lead

Lag
rync

Phase
Window

Fig. 6 . Digital phase-locked loop with bounded jitter.

and below the 0" axis of an n-bit phase window. On the

other hand, there must be at least one sector above and
one sector below this axis in order to bound the jitter of a
synthesized frequency within 1/2". Since there are in general either n, or n,+l pulses of f , during one period of f,,
the existence of a sector on each side of the 0" axis is
indeed the necessary condition to always have the final
state of the DCO phase register within the phase window.
This limits the maximum possible value for k to 2N-" and
constraints the frequencies that can be generated by the
DCO, with less than j jitter, to be less than jf,. This is the
limit obtained in (3.7) on the basis of quantization noise
considerations. It is the purpose of the next section to
show how this phase window can be implemented in
conjunction with a frequency window comparator to control the jitter of the generated signal.
V. THEDPLL WITH ACCUMULATOR-TYPE
DCO
AND FREQUENCY-PHASE
WINDOWCOMPARATOR
A physical implementation of DPLL with an accumulator-type DCO and a frequency-phase window comparator
is schematically represented in Fig. 6 . Between two succes-

984

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS,VOL.

36, NO. 7, JULY 1989

Fig. 7. Photo of an SSI realization of the DPLL as part of an adaptive-rate multiplexer circuit board.

sive edges of the fq clock, fDC0 is divided by a downcounter whose output is analysed by the zero comparator.
At each rising edge of the fq clock, the counter is initialized to p. If the output of the counter at the next rising
edge of the fq clock is larger or smaller than zero, the zero
comparator indicates to the k-register controller that the
generated frequency, fDco, is too low or too hgh respectively. Similarly, the phase window comparator analyzes
the output of the phase regster, and indicates to the
k-register controller whether the phase of the generated
frequency is leading or lagging.
The actual search for the value of k that directs the
system to an in frequency-phase window state is performed by a low-pass filter which consists of a successive
approximation register (SAR) controlled by the k-register
controller as indicated in the architecture of Fig. 6 . The
SAR provides a value of k at the input of the accumulator-type DCO after each frequency-phase comparison. If
the condition frer/q > f s / 2 N + 1 - n is satisfied, there is at
least one value of k that corresponds to a frequency within
the dynamic range defined by (3.10) and for which the
DPLL ultimately converges to a locked state. For an N-bit
accumulator-type DCO, it is sufficient to choose an N-bit
SAR since the DCO output frequencies that can be generated by such an arrangement require that the corresponding k values which define fDC0 be less than 2 N .

At the first iteration, the SAR proposes the integer Z N -

to the accumulator, and waits for the k-register controller in order to propose to the accumulator either a
larger value of k (if fDco is too slow) or a smaller value (if
fDco is too fast). This iterative search for a k-solution
proceeds until the locked conditions are met by the system.
After the k-register controller has become inactive, the
SAR also remains inactive, and the DPLL reaching a
stationary state generates a signal with the desired average
frequency pfrer/qwith less than 100/2n percent jitter. The
function of the SAR (low-pass filter) is thus to increase or
decrease the value of the k-register via discrete stages until
an in frequency-phase state of the DPLL is reached.
When such a state is reached, the value of the k-register
remains unchanged, and the phase jitter whch is equal to
zero anytime the DCO output is synchronized with the fq
clock increases up to its maximum value (lying within the
frequency-phase window) just before the following synchronization of the DCO output with the fq clock. Since
the iterative search for k stops as soon as a locked state is
reached, the value of k at convergence does not necessarily
yield a minimum jitter signal; however, it will be within
the specified bound. Besides its easy implementation, this
discrete search for k provides a low acquisition time for
the DPLL while being free of the stability problems often
found with the continuous methods where k is incre-

WALTERS AND TROUDET: DIGITAL PHASE-LOCKED LOOP

Phase-window given by
the n msb of the DCO
phase-rqirtcr.
Upperbound j on jitter
nPlogl

N-bit
aczumulator,
system clock frequency
f , . Minimal synthesized
frequency 1..
N>Iogz+

Maximal
synthesized
frequency fm,x

jZN+lt.,.>f,>

mented or decremented by amounts proportional to the

frequency-phase difference between fDco/p and frer/q.
Although at most N iterations of the SAR are sufficient to
provide a k-solution, it is necessary to allow one reference
clock period between two iterations for the actual frequency-phase comparison. This means an acquisition time
of the DPLL less than 2Nq/fre,.
It is however important to underline that other applications may use other means to reach a locked state. In
particular, applications which require the generated frequency to change monotonically towards a locked state
necessitate tracking of the sign of the relative frequency of
the generated signal with respect to the desired frequency,
e.g., FSK. This type of locking could clearly not be obtained via an SAR search where the generated frequency
alternates above and below the desired frequency between
two successive iterations.

VI. SUMMARY
AND EXPERIMENTAL
RESULTS
The concept of a frequency-phase window operating in
conjunction with an accumulator-type DCO has been introduced and applied to the design of a DPLL with
bounded jitter. It generates signals over any given range of
frequencies where preimposed jitter requirements have to
be satisfied, and can be easily implemented in conjunction
with successive approximation registers to provide a low
acquisition time for the frequency-phase lock process.
These characteristics have practical appeal for the design
of DPLL in telecommunications applications where lowjitter signals are of prime importance. Table I characterizes
the DPLL design process.
f ~ * and
, j , one can find (n,N , f,). For
Given f,,,
example, in order to bound the jitter within 7 percent, it is
sufficient to choose a phase window with n = 4, which
leads to the upper bound j = 6.25 percent on the jitter. In
order to generate frequencies up to the 1.544 MHz of the
T1 camer, the system clock frequency is f, = 25 MHz,
which leads to f,, = 1.5625 MHz. The value N = 24 for
the number of bits of the accumulator DCO yields
the acceptable value fmin = 12 Hz. These characteristics
have been confirmed through laboratory measurements
of an SSI implementation of a DPLL with a 24-bit accumulator-type DCO operating in conjunction with a 25
MHz system clock.
Fig. 7 shows the DPLL described above as part of the
integrated circuit board of the subchannel interface of an
adaptive-rate multiplexer (161, [17]. This DPLL realization,

(c)
Fig. 8. (a) Frequency spectrum of the fundamental mode of the DCO
output si nal at 64 kb s (b) Frequency s ectrum of the fundamental
mode ani the first 14 h/a;monics of the D 8 0 output signal at 64 kb/s.
(c) Frequenc spectrum of the DCO output signal at 64 kb/s over a
range going $om 0 Hz to 26 MHz.

which consists of approximately 30 chips, makes it possible to adaptively synthesize the frequency required by the
subchannel interface in order to transmit and receive data
from and to the multiplexer within predetermined jitter
limits. A frequency spectrum analysis of the DCO output
signal is shown in the set making up Fig. 8 for a synthe-

986

IEEE TRANSACTTONS ON CIRCUITS AND SYSTEMS, VOL. 36, NO. 7, JULY 1989

before the rising edge of fq.For the 64 kb/s DCO output

signal shown in Fig. 9(b), the high-to-low transition of the
DCO waveform is ahead of the fq clock by approximately
300 ns. This corresponds to a maximum leading phase
jitter of approximately + 2 percent, which lies within the
6.25 percent upper bound limit of the 4-bit phase window.
Such an SSI realization could be extended to a VLSI
implementation of this DPLL architecture towards an
increase of operational bandwidth and easier circuit implementations in the domain of telecommunications applications.

ACKNOWLEDGMENT
The authors would like to thank F. Irizarry, S. Jain, J.
Meyer, E. Thomas, and K. Ramachandran for their help,
support, and stimulating discussions during the realization
of this work.

REFERENCES

(b)
Fig. 9. (a) Waveforms of the DCO output signal at 64 kb/s and of the
/, clock. (b) Maximum phase jitter of + 2 percent with respect to the /,
clock for the DCO output signal at 64 kb/s.

sized frequency of 64 kb/s. Fig. 8(a) shows the frequency

spectrum of the fundamental mode at 64 kHz of the DCO
output signal. The full-width half-maximum of the fundamental is only 20 Hz, which demonstrates the stability in
the frequency domain of the signal generated by the DPLL.
For the same digital signal, Fig. 8(b) represents the fundamental mode and the first 14 harmonics. The even harmonics are depressed, and the odd harmonics exhibit an
intensity attenuation characteristics of square-wave signals.
The frequency spectrum of the 64 kb/s DCO output signal
is represented in Fig. 8(c) over a range of frequencies from
0 Hz to 26 MHz. The marker which points at the system
clock frequency f, = 25 MHz indicates that no jitter is
introduced by the system clock.
The photo of Fig. 9(a) represents the waveform of the
DCO output signal for a synthesized frequency of 64 kb/s
(period of 15.6 ps), and one pulse of the fq clock. As
described previously, the DCO output signal is synchronized with the f, clock at each rising edge of fq when the
accumulator is cleared. The phase jitter of the DCO output
signal with respect to the fq clock is thus maximum just

R. E. Best, Phase-Locked Lmps: Theory, Design And Applications.

New York: McGraw-Hill, 1984.
U. L. Rhode, Digital PLL Frequency Synthesizers, Theory and
Design. Englewood Cliffs, NJ: Prentice Hall, 1983 (see also references therein).
M. L. Meade, Lock-in Amplifiers: Principles And Applications.
London: Peter Peregrinus, 1983.
W. F. Egan, Frequency Synthesis By Phase-Lock. New York:
Wiley, 1981.
F. M. Gardner, Phaselock Techniques, 2nd ed. New York: Wiley,
1979.
W. C. Lindsey, Phase-Locked Loops And Their Applications. New
York: IEEE Press, 1977.
A. Blanchard, Phase-Locked Loops: Application To Coherent Receiver Design. New York: Wiley, 1976.
V. Manassewitsch, Frequency Synthesizers: Theory And Design.
New York: Wiley, 1976.
J. Gorski-Popiel, Frequency Synthesis: Techniques And Applications.
New York: IEEE Press, 1975.
W. Zhang, An analytical solution of the Fokker-Plank equation
in the phase-locked loop transient analysis, rEEE Trans. Commun.,
vol. COM-35, pp. 773-775, July 1987.
C. M. Chie, New results on mean time-to-first-slip for a first-order
loop, IEEE Trans. Commun., vol. COM-33, pp. 897-903, Sept.
1985.
H. J. Kim, C. K. Un and J. C. Lee, The N-phase digital tanlock
loop for tracking sup ressed-carrier N-ary PSK signals, IEEE
Trans. Commun., vol. {OM-33, pp. 904-910, Sept. 1985.
A. T. Crowley, Digital frequency and phase lock loop, U.S.
Patent 4 374 438, Feb. 1983.
M. J. Underhill and N. J. Walters, Frequency synthesizer of the
phase lock loop type, U.S. Patent 4 380 743, Apr. 1983.
E. J. Nossen, Digitized frequency synthesizer, U.S. Patent
4 206 425, June 1980.
S. M. Walters, Adaptive rate multi lexing, TM-ARH-000842,
Bell Communications Research, Jan. 1885.
T. P. Troudet, Description of the hardware implementation of the
adaptive-rate multiplexer, TM-ARH-009642. Bell Communications Research, July 1987.

rIc

Stephen M. Walters (S73-M78-SM87) received the B.E.E. degree from

Auburn University and the M.S. and Ph.D. degrees in electrical engineering from Virginia Polytechnic Institute and State University. At Virginia
Tech, he performed studies of self-diagnosing cellular automata and was
a faculty member in the Electrical Engineering Department.

987

WALTERS AND TROUDET: DIGITAL PHASE-LOCKED LOOP

In 1977, he joined a Bell Laboratories team

which pioneered the first integrated digital signal
processor device, and later managed exploratory
projects in real-time software systems. In January 1984, he joined Bell Communications Research and led a research team in high-performance protocol processing implementations. He
is now Division Manager, Advanced Network
Technology, and is responsible for investigations
of broad-band ISDN and next-generation
switching.
Dr. Walters belongs to Sigma Xi, Phi Kappa Phi. and Eta Kappa Nu.
He holds seven patents in the areas of digital signal processing, transmission, and multiplexing. His research interests include computer/software
architecture, communication protocols, and neural networks. He has
published widely in these and related areas, has served as a subject matter
I

expert in CCITT, and is a member of the IEEE Communications Society

Switching Committee.

rIc
Terry Troudet graduated from the Ecole Centrale Des Arts & Manufactures in 1977, and
obtained his Doctorat 3em Cycle from the
University of Grenoble, Grenoble, France, in
1979. After obtaining the Ph.D. degree in theoretical physics at M.I.T. in 1982, he served as
Attache de Recherche in C.N.R.S., Orsay,
France, and was a Tolman Post-Doctoral Fellow
in physics at the California Institute of Technology, Pasadena, from 1982 to 1985.
i Communications Research, Red Bank, NJ.