2.

MOS Transistor Inverter: Static Characteristics II

2.1 MOS Inverter Voltage Transfer Characteristic

The schematic diagram of the simple MOS transistor inverter with a
resistive load is repeated in Fig. 2.1. As with the simple bipolar
transistor inverter, the transfer characteristic can be plotted as the
output voltage against input voltage, Vo vs. Vin as shown in Fig.2.2.

VDD

iD

RD
D

G
S

VO = VDS

Vi =VGS

Fig. 2.1 Schematic Diagram of the Simple MOS Inverter

Initially, with Vi = 0 the input voltage to the transistor is below

the threshold voltage and the transistor is OFF or non-conducting so
that the output voltage is pulled up to the supply voltage VDD. Once the
input voltage is increased to be equal to the threshold voltage, VT, the
transistor begins to conduct and so the output voltage falls. Since VDS
> VGS VT, the transistor operates firstly in the saturation region. As
the input voltage is further increased, the output voltage continues to
fall until eventually VDS < VGS VT and the transistor comes out of the
saturation region to operate in the non-saturation region. Eventually
the input voltage reaches a maximum of VDD and the output reaches its
minimum value of VOL as previously evaluated.

VO

VDD

cut-off
Vi < VT

non-saturation
VDS < VGS - VT

saturation
VDS > VGS - VT

slope = -1

VOH MIN
VDS = VGS - VT
VO = Vi - VT

slope = -1
VOL MAX
VOL
0

VT ViL MAX

ViH MIN

VDD

Vi

-VT

Fig. 2.2 Voltage Transfer Characteristic of the Simple MOS Transistor

Inverter

2.2 Critical Logic Voltages

The same critical input and output logic voltages can be
defined as for other logic families namely:
ViL MAX = maximum voltage acceptable as a logic LO input
ViH MIN = minimum voltage acceptable as a logic HI input.
VOL MAX = maximum voltage acceptable as a logic LO output.

VOH MIN = minimum voltage acceptable as a logic HI output.

(a) Critical Point ViL MAX , VOH MIN
This is the point on the upper left-hand part of the transfer
characteristic where the slope is -1. At this point the transistor can be
taken to be operating in the saturation region where, neglecting the
effects of channel length modulation for simplicity, the drain current is
described as:

ID = Kn(VGS VT )

But since VO = VDS and Vi = VGS and VO = VDD iDRD then:

VO = VDD KnRD(Vi VT )

Eq. 1

Expanding gives:

VO = VDD KnRDVi2 + 2KnRDViVT KnRDVT2

Differentiating:

VO
= 2KnRDVi + 2KnRDVT
Vi
At the critical point

VO
= 1 with Vi = ViL MAX and VO = VOH MIN so that:
Vi

2KnRDVi + 2KnRDVT = 1

2KnRDViL MAX = 1 + 2KnRDVT

So that:

ViL MAX = VT +

1
2KnRD

This value is a little higher than VT and for the example given with VT =
1V, RD = 100k and Kn = 100AV-2 , ViL MAX = 1.05V.
Substituting back into Eq.1 to find the output voltage for this
coordinate gives:

VOH MIN = VDD KnRD(ViLMAX VT )

1
VOH MIN = VDD KnRD VT +
VT
2KnRD

So that finally:

VOH MIN = VDD

1
4KnRD

This value is a little lower than VDD and for the example given with VDD
= 10V, VT = 1V, RD = 100k and Kn = 100AV-2, VOH MIN = 9.98V. The
coordinate of critical point (a) is then:

ViLMAX , VOH MIN = 1.05 , 9.98

(b) Critical Point ViH MIN , VOL MAX

This is the point on the lower right-hand part of the characteristic
where the slope is -1. At this point the transistor can be taken to be
operating in the non-saturation region where the drain current is
described as:
2
ID = K n[2 (VGS VT )VDS VDS
]

But again, since VO = VDS and Vi = VGS and VO = VDD iDRD then:

VO = VDD 2KnRD(Vi VT )VO + KnRDVO2

Expanding:

VO = VDD 2KnRDViVO + 2KnRDVTVO + KnRDVO2

Rearranging:

VO[1 2KnRDVT ] = VDD 2KnRDViVO + KnRDVO2

There is a choice here to use implicit differentiation to find

VO
or to
Vi

rearrange the expression as Vi in terms of VO and then find

Vi
. The
VO

latter is simpler as there is only one term in Vi. Then:

2KnRDViVO = VDD [1 2KnRDVT ]VO + KnRDVO2

so that:

Vi =

VDD
[1 2K nR D VT ] + VO

2K nR D VO
2K nR D
2

Then:

Vi
VDD
1
=
+
VO
2K nR D VO2 2

.Eq.2

For

Vi
VO
= 1 so that:
= 1 we can use
VO
Vi

VDD
1
+
= 1
2K nR D VO2 2
VDD
3
=
2
2K nR D VO 2

VO2 =

VDD
3K nR D

Taking the positive root as the practical value gives:

VOL MAX =

VDD
3K nR D

which for the example given with VDD = 10V, VT = 1V, RD = 100k and
Kn = 100AV-2 , VOL MAX = 0.58V.
This is considerably higher than the extreme value of VOL evaluated
previously. Then substituting this back into the expression for Vi in Eq.
2 above gives:

VDD

Vi =

2KnRD

VDD
3KnRD

[1 2KnRDVT ] + 1
2KnRD

VDD
2 3KnRD

Rearranging:
2
3KnRDVDD
1
1 VDD
Vi =

+ VT +
2 2
2 3KnRD
4KnRDVDD 2KnRD

Vi =

3VDD 1 VDD
1
+
+ VT
4KnRD 2 3KnRD
2KnRD

Vi =

3 VDD
1 VDD
1
+
+ VT
2 3KnRD 2 3KnRD
2KnRD

So that finally the critical input value is given as:

ViHMIN = VT + 2

VDD
1

3KnRD 2KnRD

which for the example given with VDD = 10V, VT = 1V, RD = 100k and
Kn = 100AV-2 gives ViH MIN = 2.1V. This gives the coordinates of critical
point (b) as:

ViH MIN , VOL MAX = 2.1, 0.58

2.3 Noise Margins

Finally, the noise margins for the simple MOS inverter can be
evaluated approximately from the critical points estimated from the
transfer characteristic as:

NMH = VOH MIN ViH MIN = 9.98 2.1 = 7.88V

NML = ViL MAX VOL MAX = 1.05 0.58 = 0.47V