ARM LPC2148 SCI Block

Prof. Anish Goel

UUART Features
16 byte Receive and Transmit FIFOs
Register locations conform to 550 industry
standard.
Receiver FIFO trigger points at 1, 4, 8, and 14
bytes.
Built-in fractional baud rate generator with
autobauding capabilities.
Mechanism that enables software and hardware
flow control implementation.

LPC2148 UART

Prof. Anish Goel

Pin description

LPC2148 UART

Prof. Anish Goel

Register description

LPC2148 UART

Prof. Anish Goel

UART0 Receiver Buffer Register

The U0RBR is the top byte of the UART0 Rx FIFO. The
top byte of the Rx FIFO contains the oldest character
received and can be read via the bus interface.
The LSB (bit 0) represents the oldest received data bit.
If the character received is less than 8 bits, the unused
MSBs are padded with zeroes.

LPC2148 UART

Prof. Anish Goel

UART0 Transmit Holding Register

The U0THR is the top byte of the UART0 TX FIFO. The
top byte is the newest character in the TX FIFO and can
be written via the bus interface.
The LSB represents the first bit to transmit.

LPC2148 UART

Prof. Anish Goel

UART0 Divisor Latch Registers

The UART0 Divisor Latch is part of the UART0 Fractional
Baud Rate Generator and holds the value used to divide the
clock supplied by the fractional prescaler in order to produce
the baud rate clock, which must be 16x the desired baud rate .
The U0DLL and U0DLM registers together form a 16 bit
divisor where U0DLL contains the lower 8 bits of the divisor
and U0DLM contains the higher 8 bits of the divisor.
A 0x0000 value is treated like a 0x0001 value as division by
zero is not allowed.
The Divisor Latch Access Bit (DLAB) in U0LCR must be one
in order to access the UART0 Divisor Latches.

LPC2148 UART

Prof. Anish Goel

UART0 Divisor Latch Registers

LPC2148 UART

Prof. Anish Goel

UART0 Fractional Divider Register

The UART0 Fractional Divider Register (U0FDR)
controls the clock pre-scaler for the baud rate generation
and can be read and written at users discretion.
This pre-scaler takes the APB clock and generates an
output clock per specified fractional requirements.

LPC2148 UART

Prof. Anish Goel

Baud Rate Calculation

Where PCLK is the peripheral clock, U0DLM and U0DLL

are the standard UART0 baud rate divider registers, and
DIVADDVAL and MULVAL are UART0 fractional
baudrate generator specific parameters.

[Refer Section 10.3.5 of UM2148 for standard baudrate

calculation]
10

LPC2148 UART

Prof. Anish Goel

UART0 Interrupt Enable Register

The U0IER is used to enable UART0 interrupt sources.

11

LPC2148 UART

Prof. Anish Goel

UART0 Interrupt Enable Register

12

LPC2148 UART

Prof. Anish Goel

UART0 Interrupt Identification Register

The U0IIR provides a status code that denotes the

priority and source of a pending interrupt.
The interrupts are frozen during an U0IIR access. If an
interrupt occurs during an U0IIR access, the interrupt is
recorded for the next U0IIR access.

13

LPC2148 UART

Prof. Anish Goel

UART0 Interrupt Identification Register

14

LPC2148 UART

Prof. Anish Goel

UART0 FIFO Control Register

The U0FCR controls the operation of the UART0 Rx and

TX FIFOs.

15

LPC2148 UART

Prof. Anish Goel

UART0 Line Control Register

The U0LCR determines the format of the data character

that is to be transmitted or received.

16

LPC2148 UART

Prof. Anish Goel

UART0 Line Status Register

17

LPC2148 UART

Prof. Anish Goel

UART0 Line Status Register

18

LPC2148 UART

Prof. Anish Goel

UART0 Line Status Register

19

LPC2148 UART

Prof. Anish Goel

UART0 Scratch pad register

The U0SCR has no effect on the UART0 operation. This

register can be written and/or read at users discretion.
There is no provision in the interrupt interface that
would indicate to the host that a read or write of the
U0SCR has occurred.

20

LPC2148 UART

Prof. Anish Goel

UART0 Auto-baud Control Register

21

LPC2148 UART

Prof. Anish Goel

UART0 Transmit Enable Register

The U0TER enables implementation of software flow

control. When TXEn=1, UART0 transmitter will keep
sending data as long as they are available.
As soon as TXEn becomes 0, UART0 transmission will
stop.

22

LPC2148 UART

Prof. Anish Goel

Architecture

The architecture of the UART0 is shown below in the

block diagram.
The APB interface provides a communications link
between the CPU or host and the UART0.
The UART0 receiver block, U0RX, monitors the serial
input line, RXD0, for valid input.
The UART0 RX Shift Register (U0RSR) accepts valid
characters via RXD0. After a valid character is assembled
in the U0RSR, it is passed to the UART0 RX Buffer
Register FIFO to await access by the CPU or host via the
generic host interface.
23

LPC2148 UART

Prof. Anish Goel

Architecture

The UART0 transmitter block, U0TX, accepts data written by

the CPU or host and buffers the data in the UART0 TX
Holding Register FIFO (U0THR).
The UART0 TX Shift Register (U0TSR) reads the data stored
in the U0THR and assembles the data to transmit via the serial
output pin, TXD0.
The UART0 Baud Rate Generator block, U0BRG, generates
the timing enables used by the UART0 TX block. The U0BRG
clock input source is the APB clock (PCLK).
The main clock is divided down per the divisor specified in the
U0DLL and U0DLM registers.
This divided down clock is a 16x oversample clock,
NBAUDOUT.
24

LPC2148 UART

Prof. Anish Goel

The interrupt interface contains registers U0IER and

U0IIR. The interrupt interface receives several one clock
wide e
Status information from the U0TX and U0RX is stored in
the U0LSR. Control information for the U0TX and U0RX
is stored in the U0LCR. Enables from the U0TX and
U0RX blocks.

25

LPC2148 UART

Prof. Anish Goel

UART0 block diagram

26

LPC2148 UART

Prof. Anish Goel