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Synthesis and Timing

Module 11

Overview

Metastability

Constraints

Clock Skew

Core Generator

Metastability

Flip-flops may go metastable if input signals do not meet setup and hold specifications relative to clock signal

CLK

setup and hold specifications relative to clock signal CLK D Q • Rules: – Input only
D Q
D
Q

Rules:

– Input only drives one FF

– Add 2-FF synchronizer

IF clk’EVENT AND clk = ‘1’ THEN input_d <= input; input_dd <= input_d;

Creating one clk pulse synchronizer

Sometimes an input signal is asynchronous and is much longer than clock period

Add 3FF synchronizer and generate single pulse

IF clk’EVENT AND clk = ‘1’ THEN

input_d

input_dd

input_ddd

input_pulse <= input_dd & NOT input_ddd;

<= input; <= input_d; <= input_dd;

always @ (reset, clk) begin

input_d

input_dd

input_ddd

input_pulse <= input_dd & ~input_ddd;

<= input; <= input_d; <= input_dd;

Timing Constraints

Used to guide the synthesis tools

Example 32-bit counter - no constraints (speed grades -4 and -5)

======================================================

Advanced HDL Synthesis Report Macro Statistics # Counters 32-bit up counter

:

:

1

1

====================================================== Timing Summary:

---------------

Speed Grade: -4 Minimum period: 6.680ns (Maximum Frequency: 149.703MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 8.094ns Maximum combinational path delay: No path found =============================================== Speed Grade: -5 Minimum period: 5.767ns (Maximum Frequency: 173.400MHz)

Adding timing constraint

Add to UCF file:

– NET "clk" PERIOD = 6ns HIGH 50%;

WARNING:Par:62 - Your design did not meet timing.

-------------------------------------------------------------------------------------------

Constraint

| Check | Worst Case | Best Case | Timing |Timing | Slack | Achievable |

Errors | Score

-------------------------------------------------------------------------------------------

* NET "clk_BUFGP/IBUFG" PERIOD = 6 ns HIGH

| SETUP| -0.456ns | 6.456ns |

9| 1430

50%

| HOLD | 2.432ns

|

|

0|

0

-------------------------------------------------------------------------------------------

1 constraint not met.

Try relaxing constraint

NET "clk" PERIOD = 6.5ns HIGH 50%;

----------------------------------------------------------------------------------

Constraint | Check| Worst Case | Best Case | Timing | Timing | Slack| Achievable |

Errors |

Score

----------------------------------------------------------------------------------

NET "clk_BUFGP/IBUFG" PERIOD = 6.5 ns HIG | SETUP| 0.203ns| 6.297ns| 0| 0

0

H 50%

| HOLD | 2.280ns|

|

0|

----------------------------------------------------------------------------------

All constraints were met.

Also see Timing Constraint User Guide

Examples:

NET ‘abc’ OFFSET = OUT xx ns AFTER ‘clk’; NET ‘def’ OFFSET = IN xx ns BEFORE ‘clk’;

Clock Skew

The difference between the time a clock signal arrives at the source flip-flop in a path and the time it arrives at the destination flip-flop.

– Misalignment of clock edges

– Degrades (reduces) time for flip-flop to flip-flop timing

Can be caused by different things but wire interconnect delays are the main cause inside FPGAs

– There are fast dedicated clock circuits and slower data paths

Old method of deriving slower clocks

Old method of deriving slower clocks Jim Duckworth, WPI 9 Synthesis and Timing - Module 11

WARNING:Route:455 - CLK Net:clk_1Hz may have excessive

skew because 0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.

Synthesis uses two clock signals

Synthesis uses two clock signals Jim Duckworth, WPI 11 Synthesis and Timing - Module 11

Two clock signals – not so good!

Two clock signals – not so good! Jim Duckworth, WPI 12 Synthesis and Timing - Module

Modify to only use one clock signal

Modify to only use one clock signal Jim Duckworth, WPI 13 Synthesis and Timing - Module

Clock signals use dedicated lines

Clock signals use dedicated lines Jim Duckworth, WPI 14 Synthesis and Timing - Module 11

Clock drives all flip-flops

Clock drives all flip-flops Jim Duckworth, WPI 15 Synthesis and Timing - Module 11

Crossing Clock Domains - FIFO

FPGA

FIFO
FIFO

200 MHz

ADC

SRAM

Crossing Clock Domains - FIFO FPGA FIFO 200 MHz ADC SRAM 400 MHz JimJim Duckworth,Duckworth, WPIWPI
Crossing Clock Domains - FIFO FPGA FIFO 200 MHz ADC SRAM 400 MHz JimJim Duckworth,Duckworth, WPIWPI

400 MHz

Coregen – create new module

Coregen – create new module Jim Duckworth, WPI Jim Duckworth, WPI 17 17 Synthesis and Timing

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Jim Duckworth, WPI

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Synthesis and Timing - Module 11

FIFO Generator

FIFO Generator Jim Duckworth, WPI Jim Duckworth, WPI 18 18 Synthesis and Timing - Module 11

Jim Duckworth, WPI

Jim Duckworth, WPI

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Synthesis and Timing - Module 11

VHDL for Modeling - Module 10

Select Options (1 of 6)

Select Options (1 of 6) Jim Duckworth, WPI Jim Duckworth, WPI 19 19 Synthesis and Timing

Jim Duckworth, WPI

Jim Duckworth, WPI

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Synthesis and Timing - Module 11

Specifying Write and Read widths

Specifying Write and Read widths Jim Duckworth, WPI Jim Duckworth, WPI 20 20 Synthesis and Timing

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Jim Duckworth, WPI

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Synthesis and Timing - Module 11

Summary – uses one Block RAM

Summary – uses one Block RAM Jim Duckworth, WPI Jim Duckworth, WPI 21 21 Synthesis and

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Jim Duckworth, WPI

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Synthesis and Timing - Module 11

Core is added to Project

Core is added to Project Jim Duckworth, WPI Jim Duckworth, WPI 22 22 Synthesis and Timing

Jim Duckworth, WPI

Jim Duckworth, WPI

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Synthesis and Timing - Module 11

Instantiation Template is Provided

Instantiation Template is Provided Jim Duckworth, WPI Jim Duckworth, WPI 23 23 Synthesis and Timing -

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Synthesis and Timing - Module 11

Simple Top Level to Demonstrate Use

Simple Top Level to Demonstrate Use Jim Duckworth, WPI Jim Duckworth, WPI 24 24 Synthesis and

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Jim Duckworth, WPI

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Synthesis and Timing - Module 11

VHDL for Modeling - Module 10

FIFO added – RTL Schematic

FIFO added – RTL Schematic Jim Duckworth, WPI Jim Duckworth, WPI 25 25 Synthesis and Timing

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Jim Duckworth, WPI

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Synthesis and Timing - Module 11

FIFO added – Technology Schematic

FIFO added – Technology Schematic Jim Duckworth, WPI Jim Duckworth, WPI 26 26 Synthesis and Timing

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Jim Duckworth, WPI

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Synthesis and Timing - Module 11

Simple Test Bench to Show Operation

Simple Test Bench to Show Operation Jim Duckworth, WPI Jim Duckworth, WPI 27 27 Synthesis and

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Jim Duckworth, WPI

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Synthesis and Timing - Module 11

FIFO Simulation

FIFO Simulation Jim Duckworth, WPI Jim Duckworth, WPI 28 28 Synthesis and Timing - Module 11

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Jim Duckworth, WPI

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Synthesis and Timing - Module 11