Beruflich Dokumente
Kultur Dokumente
1. Introduction
2. LNA Demoboard
1.043 IN.
Figure 1. Artwork for the ATF-5X143 series of low noise PHEMT devices
3. Circuit Details
One of the advantages of the enhancement mode
PHEMT is the ability to DC ground the source leads and
6244-01 AN 1299
yet require only a single positive polarity power supply.
Whereas a depletion mode PHEMT pulls maximum
drain current when Vgs = 0 V, an enhancement mode
PHEMT pulls nearly zero drain current when Vgs = 0 V.
The gate must be made positive with respect to the
source for the enhancement mode PHEMT to begin
pulling drain current. It is also important to note that
if the gate terminal is left open circuited, the device
will pull some amount of drain current due to leakage
current creating a voltage differential between the gate
and source terminals.
C4
0.20
Q1
0.15
R5
L1
L2
Ig (mA)
C1
L4
L3
0.10
0.05
C2
C5
R4
10
PIN (dBm)
C3
R1
Vdd
6244-02 AN 1299
1.043 IN.
Part
Value
Qty.
6244-04 AN 1299
C1, C4
C2, C5
C3, C6
L1
L2, L3
L4
R1
R2
R3
R4
R5
Q1
5.6 pF (0805)
18 pF (0805)
10 nF (0805)
6.8 nF (LL2012)
Shorting strip
8.2 nH (LL2012)
4.7 k (0805)
33 k (0805)
27 (0805)
56 (0805)
330 (0805)
ATF-54143
2
2
2
1
2
1
1
1
1
1
1
1
6244-3 AN 1299
The schematic diagram describing the 900 MHz low
noise amplifier is shown in Figure 2. Circuit topology is
very similar to the typical depletion mode circuit except
for the method of biasing the device. A parts placement
drawing is shown in Figure 3. The parts list for the
amplifier is shown in Table 1.
Biasing the ATF-54143 is accomplished by the use of
a voltage divider consisting of R1 and R2. The voltage
for the divider is derived from the drain voltage which
provides a form of voltage feedback to help keep drain
current constant. While low value resistors in R1 and
R2 should improve bias stability, they can result in
excessive rectified gate current under large signal input
conditions. If the rectified current is not kept below 2
mA, gate metal migration may occur over time. Using
the resistor values suggested in Table 1, the rectified
gate current, as shown in Figure 4, stays way below 2
mA even at the input power of 10 dBm.
gmVc
Rg
+
Vc
Cgs
Cds
Rds
G
Rg
Ig
+
Vc
Cgs
gmVc
Vg
Ls
Is = Ig + gmVc
Figure 5. Simplified FET models without source inductance (above) and with external source inductance (below)
Equations-AN1299
6244-05 AN 1299
1
jCgs
1
Zin = Rg jCgs
With the addition of source inductance, the input
impedance is modified accordingly [2]:
Ls
+ j Ls - 1
Zin' = Rg + gm
CLgs
Cgs
s
+ j Ls - 1
Zin' = Rg + gm
Cgs
The difference between
Zin and Cgs
Zin = Rg -
The
between
Zin and
Zin', difference
indicates that
feedback
adds
Ls
that feedback adds
Zgin', indicates
+ jLs to the input
m
CLgs
s + jL to the input
gimpedance
[2]. s
m
Cgs
impedance[2].
loss = 20 log
loss = 20 log
GOPT
200
10
500
500
Qu - Ql
200
QuQ- uQl
100
Qu
IM
2
IM
IP3 = Pfund +
2
IP3 = Pfund +
81.3
40.0 dBm
2
81.3
40.0 dBm
3IP3 = - 0.7 +
2
IP3 = - 0.7 +
100
GIN*
50
25
10
6244-06 AN 1299
5.0
4.5
4.0
STABILITY FACTOR, k
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
600
800
1000
1200
1400
FREQUENCY (MHz)
1600
1800
2000
6244-08 AN 1299
0
SHORTING
STRIP
ATF-54143
GAIN (dB)
L
-10
Equations-AN1299
L
-20
1.0
3.0
GHz
1
Zin = Rg jCgs
Figure 9. Wide-band gain sweep (1 ~ 6 GHz)
6244-09 AN 1299
6244-07 AN 1299
6.0
loss = 20 log
Qu - Ql
Qu
IP3 = Pfund +
IM
2
2.0
4. Performance
The prototype amplifier was tested at a Vds of 4.0 V and
Id of 60 mA. The measured gain and the noise figure
are shown in Figures 10 and 11. The gain measured
a nominal 19.5 dB at 900 MHz, while the noise figure
was 0.77 dB. The losses in the PCB substrate, matching
networks and connectors added to the total noise
figure of the amplifier. The low cost FR4 PCB material
has made the noise figure somewhat poorer than what
could have been achieved using a better substrate.
20
19
1.5
NOISE FIGURE (dB)
1.0
0.5
700
800
900
FREQUENCY (MHz)
1000
1100
6244-11 AN 1299
The measured input and output return losses are shown
in Figure 12. The input and output ports exhibited
return losses that were better than 12 dB at 900 MHz.
Further improvement in noise figure is possible with
some degradation of input return loss by altering the
input impedance matching network.
The 1 dB gain compression point, P1dB, indicates the
upper limit of the input or output power level at which
saturation has started to occur and non-linear effects
are becoming increasingly significant. The P 1dB is
measured by increasing the input power while noting
the point when the gain became compressed by 1 dB.
This measurement is most commonly referred to the
output.
18
-5
INPUT
17
16
700
800
900
FREQUENCY (MHz)
1000
6244-10 AN 1299
1100
GAIN (dB)
-10
OUTPUT
-15
-20
-25
-30
700
800
900
FREQUENCY (MHz)
6244-12 AN 1299
1000
1100
gs
impedance[2].
The relationship
between the gain and the input power
Equations-AN1299
is shown in Figure 13. The 1-dB compressed gain (G1dB)
and the associated input power (Pin) can be read from
the graph. The P1dB was calculated as below:
P1dB = G1dB + Pin = 18.7 2.3 = 16.4 dBm
1
Zin
= Rg 20.0
jCgs
Q - Ql
The
(Vds and I ds) have a
loss DC
= 20operating
log u conditions
Qu the IP3 result. Fixing Ids at 60 mA,
large influence over
Avago Technologies empirically found that the best
IP3 occurred at Vds = 2.9 V for the prototype. The third
order products were approximately 81.3 dB below
IM
= Pfund +
IP3 fundamental
the
output tones (Figure 14). Hence, the
2
third-order intercept point, referred to the output, was
calculated as below:
19.5
19.0
18.5
18.0
' = Rg + gm
Zin
GAIN (dB)
IP3 = - 0.7 +
-18.9 dBm
19.6919 dB
L
17.5
s
+ j Ls - 1
Cgs
Cgs
17.0
0
ATF-64143
ATF-54143
2V9/60mA
-2.34 dBm
18.6867 dB
81.3
40.0 dBm
2
-0.7 dBm AT 901.0 MHz
Ls
gm
+ jLs to the input
15.0
Cgs
-23.5
P (dBm)
Zin
', indicates that feedback adds
16.0
15.5
impedance[2].
-40
-0.5
6244-13 AN 1299
Qu - Ql
lossintercept
= 20 logpoint
The
was measured using two test signals
Qu
with a spacing of 500
kHz. The IP3, referenced to the
output, can be calculated as follows [5]:
IP3 = Pfund +
IM
2
-80
5. Appendix:
Determining the Optimum Amount of Source Inductance
0
-10
-20
-30
-40
0
-40
0
12
14
20
-20
6
8
10
FREQUENCY (GHz)
-10
10
0
20
-10
-20
-30
-30
-40
2
6
8
10
FREQUENCY (GHz)
12
14
10
GAIN (dB)
GAIN (dB)
20
GAIN (dB)
6
8
10
FREQUENCY (GHz)
12
14
6244-17 AN 1299
6. References
1. Smith, J., Modern Communication Circuits, McGraw-
Hill, 1986, chapter 5 sub-topic: Lossless feedback
amplifiers.
2. Henkes, D., LNA Design Uses Series Feedback to
Achieve Simultaneous Low Input VSWR and Low
Noise, Applied Microwave & Wireless, October, 1998.
3. Hewlett-Packard Application Note 1076, Using the
ATF-10236 in Low Noise Amplifier Applications in the
UHF through 1.7 GHz Frequency Range, sub-topic:
Design Techniques, page 2.
4. Hewlett-Packard Application Note 1085, 900 and
2400 MHz Amplifiers Using the AT-3 Series Low Noise
Silicon Bipolar Transistors, page 9.
5. Vizmuller, P., RF Design Guide, Artech House, 1995,
chapter 3.6: Intercept Point.
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright 2005-2010 Avago Technologies. All rights reserved.
5988-6670EN - July 13, 2010