LAB REPORT: BASICS OF VLSI

SIMULATION OF NMOS AND PMOS

Experiment 1:
date:26-08-2015
Submitted by:

RINOOP R.
JUSTIN K. THOMAS
M150190EC
SINO V. ANTONY
M150411EC

M150205EC

OBJECTIVE:
Simulating the input and output characteristics of nMOSFET and pMOSFET and
parameter extraction.
THEORY:
MOSFET is the fundamental building block of digital integrated circuits. It is a four
terminal device which operates in three regions, viz, cut-off, linear and saturation.
Drain current equation for n-channel MOSFET is,
ID=0

; (VGS<VTH)

ID= nCox

ID=

W
L

1
2 nCox

[(VGS-VTH) VDS -

1
2
2 VDS ]

W
2
L (VGS-VTH)

for cut-off

; (VDS<VGS-VTH) for linear region

; (VDS>VGS-VTH) for saturation region

SOFTWARE TOOL: Cadence Virtuoso

DESIGN CONSIDERATIONS:
nMOS

pMOS

W=1 m ; L=1m

W=1 m ; L=1m

W
L =1

W
L =1

VDD=1.8 V

V DD=1.8 V

SCHEMATICS AND PLOTS:

Figure 1 schematic -

Figure 2 schematic -

Figure 4 input characteristics - pmos(ID

Vs VGS)

Figure 3 input characteristics - nmos(ID Vs

VGS)

Figure 5 output characteristics nmos(ID Vs VDS)

Figure 6 output characteristics pmos(ID Vs VDS)

Figure 7 Effect of body bias on

nmos(ID Vs VGS)

Figure 8 Effect of body bias on

pmos(ID Vs VGS)

Figure 9 sub-threshold characteristics

nmos(log10ID Vs VGS)

Figure 10 sub-threshold characteristics

pmos(log10ID Vs VGS)

OBSERVATIONS AND CALCULATIONS:

Sl.no.
1
2

Parameter
Threshold
Voltage
Sub-threshold
current Ioff
Sub-threshold
Slope

Transconductance
gm(Linear)
Transconductance
gm(Saturation)

Value

Formula

nMOS

pMOS

From the plot

graphically

VTH=0.479mV

VTH=0.502mV

From the plot

Ioff=3.427pA

Ioff=4.347pA

SS=89.8mV/decade

SS=93.12mV/decade

gm= 79.42u
VDS=0.5 V

gm= 320.3u
VDS= -0.5 V

gm=310.964u
VDS=1.8 V

gm= 473.9u
VDS= -1.8 V

I
log ( DS) ;
s
V GS

VDS constant
ID
gm= V GS ;
VDS constant
ID
gm= V GS ;
VDS constant

DIBL

Drain
conductance
gd(Linear)
Drain
conductance
gd(Saturation)

Output resistance
r0

10

On resistance
ron

VDS1= 0.09 V
VTH1= 0.434 V
DIBL=
VDS2= 1.8 v
V
v
V TH 1V DS 1V TH 2V DS 2 TH2= 0.509
DIBL= 44.444
V DS 1V DS 2
mV
V
ID
gd= V DS

DIBL= 60.23

mV
V

gd =95.97 ;
VGS=.09 V

gd =67.29
VGS=.09 V

gd =3.123

gd =9.452

(Saturation)

320.178K
at VDS=1.8 V

105.8 K
at VDS=1.8 V

(Linear)

10.419K
at VDS=0.1 V

14.86K
at VDS=-0.1 V

; VGS

constant
ID
gd= V DS ; VGS
constant
rd =1/ g

rd =1/ g

INFERENCE:
i.
ii.
iii.

VDS1= -0.09 V
VTH1= -0.449 V
VDS2= -1.8 v
VTH2= -0.552 V

As source to body voltage (VSB) increases, threshold voltage increases.

The OFF current of pMOS is greater than that of nMOS.
The output resistance of nMOS is higher than pMOS
3

iv.
v.

The On resistance of pMOS is more compared to nMOS.

As VDS increases leakage current increases.

RESULT:
The input and output characteristics of nMOS and pMOS were simulated using cadence virtuoso
tool and plotted. Their typical parameter values have been calculated from the plots.