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Phys. Status Solidi C 11, No. 34, 906 910 (2014) / DOI 10.1002/pssc.201300490

current topics in solid state physics

Comparison of AlGaN/GaN
MISHEMT powerbar designs

Steve Stoffels*, Nicol Ronchi, Rafael Venegas, Brice De Jaeger, Denis Marcon,
and Stefaan Decoutere
Imec Leuven, Kapeldreef 75, 3001 Leuven, Belgium
Received 23 August 2013, revised 7 October 2013, accepted 12 December 2013
Published online 11 February 2014
Keywords AlGaN/GaN powerbar, MISHEMT, design, modelling
* Corresponding author: e-mail, Phone: +32 16 288506, Fax: +32 16281844

This works presents a comparison of several different

AlGaN/GaN powerbar designs, with a total gate width of
9mm, with the goal to minimize the total gate resistance.
Analytical models were developed for the interconnect
parasitics to aid in the design phase. The different power
transistor topologies were fabricated in a GaN-on-Si

MISHEMT technology. Measurements on the fabricated

transistors showed a good agreement between the analytical models and the measurements. Furthermore, the
modelling framework allowed us to design power transistors that reached the goal of reducing the gate resistance
while having minimal impact on other characteristics.

2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

1 Introduction AlGaN/GaN high electron mobility

transistors (HEMTs) have properties which make them
very desirable for use as power switches [1]. Cost reductions through e.g. heteroepitaxial growth on silicon [2]
have made it possible for AlGaN/GaN HEMTs to start
competing with established silicon power technologies.
The technology is now mature enough that system level integration of demonstrators are starting to be realized. It is
essential that, during the design phase there are tools available, which can predict how the component will function.
Furthermore, the trade-offs between different designs need
to be understood, such that a selection can be made between device topologies. For this work we have designed,
fabricated and evaluated three different AlGaN/GaN powerbar architectures. During the design phase we have developed analytical models to calculate the interconnect parameters such as gate resistance, access resistance and parasitic capacitances. The models were used to analyze three
different designs, with very different gate and interconnect
topologies and with the goal to reduce the overall gate resistance. The designs were fabricated in an 8 inch GaNOn-Si MISHEMT technology.
2 Topologies For this work we have investigated
three different topologies for power transistors. The most
common design presented in the literature for AlGaN/GaN
powerHEMTs is a fishbone type of design with long interdigitated fingers [3-6]. This design is referred to in this

paper as the long gate finger (LGF) design. The design is

easy to implement and relatively compact. The drawbacks
are that the long gate fingers lead to an excessive gate resistance and thus limit the choice of the stack for gate metallization. And secondly, due to the switching delay, the
active region at the end of such a finger will need a longer
time to switch, causing it to draw a large amount of current
during switching and potentially leading to reliability issues. A split gate version (W-gate) was also designed, for
which each gate finger is split in two along the width of the
finger, and each section was connected from two sides.
Therefore it is expected that Rg,lgw = Rg,lgf/4.



Figure 1 Schematic drawing of the a) LGF, b) SGF, c) 3DI designs.
2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

Phys. Status Solidi C 11, No. 34 (2014)

To avoid the issues related to the long gate fingers, we

have investigated two alternative designs, with more, but
shorter gate fingers in parallel. To accommodate the many
fingers, the active region was split up in several islands
which were horizontally and vertically repeated. This introduced the need for a more complex source and drain bus
architecture. For one design the interconnects were designed to run in between the active islands, we will refer to
this design as the short gate finger (SGF) design. An overview of the SGF design is shown in Fig. 1b. A disadvantage of this approach is the increase in area which is
needed for the interconnect bus. For the third design the interconnects for source and drain were designed in a cross
bar architecture, and stacked in a 3D interconnected manner on top of the active island (Fig. 1c), referred to as 3D
interconnected design (3DI). The direction of each subsequent interconnect level is perpendicular to the interconnects on the previous level. The gate bus runs on the lowest interconnect level in between the active islands. This
design is more compact, as the interconnects are on top of
active, however, due to the cross bar architecture, high potential and low potential lines cross, which necessitates the
need to optimize the inter-metal dielectric (IMD) thickness
for sustaining the high voltage applied between source and
drain in the off-state. The power bars were designed with a
gate drain spacing of 10 m, gate source spacing of 0.75
m and gate length of 1.5 m. The LGF design had an active width of wa=1 mm, while the SGF and 3DI design had
a wa=150 m. All designs had a total gate width of 9 mm.
3 Design methodology To study the impact of the
topology on the functioning of the transistor, it is essential
that models are developed which can predict the electrical
performance of the component. The main difference between the different topologies is related to how the interconnects are routed between the active islands. Therefore,
we have focused on modelling the parasitic resistance and
capacitance due to the interconnects. The goal is to have a
lumped representation for the parasitics at each of the ports
of the transistor, as is shown in the network in Fig. 2.

Figure 2 Lumped equivalent circuit representation of the interconnect parasitics of an AlGaN/GaN PowerHEMT.

3.1 Resistance model The goal was to find a single

lumped resistor representation for the interconnects at each
of the ports (Source/Gate/Drain) and an approximate value
for the resistances. This was done by creating a distributed
lumped component representation of the interconnect


work. It was assumed that the distributed network consisted of purely resistive components, and secondly it was
assumed that for each port all the connections of the interconnect elements to the active region were equipotential,
which were then referenced to ground. An example of a cut
out of a lumped circuit for a portion of the SGF design is
shown in Fig. 3.

Figure 3 Distributed resistance network for a portion of the gatebus for the SGF design.

The geometry of each of the designs was analysed and partitioned in sections through which the current could only
flow in one direction. The resistance (R) of each partition
could be calculated, using the value for the sheet resistance
R = Rsh W/L ,


where W is the width of the partition and L is the length of

the partition. Combining all the elements allowed us to
construct the distributed equivalent network. Using the
Kirchhoff rules allows to reduce the network to a single
lumped component.
3.2 Capacitance model For the capacitances we
have considered the parasitic capacitances due to the interconnects, occurring at different geometrical locations. An
overview of the different contributions is given in the diagram, shown in Fig. 4. There are three type of capacitors
considered, the first is an idealized parallel plate capacitor
with a single dielectric in between the metal plates, indicated by Cpp. The second capacitor that was modelled was
a parallel plate capacitor with multiple dielectrics (Cpp,m),
which can be approximated as a series connection of capacitors, with the plate separation and dielectric constant
defined by each subsequent dielectric layer in the stack.
The final capacitor that was considered was due to the
fringing fields (Cff) between the side and top of metal interconnects and the top of a nearby electrode. A conformal
mapping technique was used for calculating Cff [7]. The
analytical formulas for the different capacitance values are
thus given by:
Cpp = 0 r A/d ,


Cpp,m = 0 A/(d1/1 + ... + dn/n) ,


Cff = 0r/2 ln[(t + (d 2 + t 2 ) )/d] ,


where 0 is vacuum permittivity, r is the relative permittivity of the dielectric, dn is the thickness of the dielectric,
2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim






St. Stoffels et al.: Comparison of AlGaN/GaN MISHEMT powerbar designs

A is the area of the electrode and t is the thickness of the

metal interconnect. Apart from these parasitic capacitances
close to the access regions, we also considered overlap capacitances between different metal lines. Our designs also
included a source field plate (SFP) [8], which is not shown
in Fig. 4. The effects of the source field plate were taken
into account by assuming a parasitic parallel plate capacitance between the SFP and the 2DEG in the drain access
region and also between the SFP and the metallization at
the gate. For the on-state, the capacitance between the gate
and 2DEG was also considered.

have performed gate resistance and capacitance measurements, with an impedance analyzer and LCR meter. The Rg
was measured by biasing the device in the on-state. It is assumed that the gate-source branch acts as a series resistance (Rs), dominated by (Rg), and series capacitance (Cs),
the values can be determined from the measured impedance data. The extraction is done internally in the LCR meter. It can be seen from Fig. 5 that there is a good agreement between the analytical calculations and the measured
gate resistance. Furthermore, it can be seen that the 3DI
and LGF design have Rg values which are about 10x lower
than the original LGF design, reaching our design goal.
This demonstrates the capabilities of the modelling methodology presented in this work.

Figure 4 Physical location of the capacitors in the active region

of the component.
Table 1 Capacitance values for a LGF design. The fringing capacitance includes the lateral Cpp and the lateral Cff. Bulk is the
contribution of the bulk parallel plate capacitances between two
ports. Overlap is the capacitances due to interconnect crossing.

Figure 5 Rg for different device designs.

Calculating the different values for the capacitances revealed that the parasitic impedances are mainly caused by
the vertical interconnect overlap capacitances and the interconnect to substrate capacitances (Table 1). Also the
source field plate plays an important role in the contribution to the parasitic capacitance. For the power transistor
designs the lateral separation is large enough that fringing
field capacitances and horizontal overlap capacitance only
has a negligible influence.

The models for the parasitic capacitances were verified

on a single design, namely the LGF design. For the design
we have varied the pitch between the different gate fingers
(lgg) from 30 m to 80 m. The parasitic capacitances due
to the interconnects were calculated and compared with
measured values, shown in Fig. 6. It can be seen that the
values for the parasitic capacitances between the different
ports are in close agreement. The parasitic capacitances
were measured by biasing the transistor in off-state with a
high Vds. This condition assures that the intrinsic capacitances are minimized and the parasitic capacitances become dominant. It was assumed that under this condition
the source-gate branch could be represented by a parallel
resistor and capacitor, and the model for the LCR meter
was set to a parallel conductance (Gp) and capacitance (Cp).

4 Design of GaN powerbars The design goal was

to reduce the gate resistance of the LGF design with a factor of 5, while having limited impact on the key figures of
merit of the power transistor. The power transistors were
fabricated and subsequently characterized, which allowed
us to evaluate both the performance of the transistors and
also act as a validation for the modelling framework. The
power-transistors were fabricated in an AlGaN/GaN metal
insulator semiconductor HEMT (MISHEMT) device technology [9], with a bilayer dielectric stack to isolate the gate
electrode from the channel [10]. To verify the models we

Figure 6 Variation of the off-state capacitance with the gate to

gate pitch (lgg).








2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

Phys. Status Solidi C 11, No. 34 (2014)

Figure 7 On-state capacitance (Cgs,on) for different designs.

The on-state capacitances were measured with an LCR meter, with the transistor biased in the on-state. The extraction
of the capacitance value was achieved by using a series
Rs-Cs model. As can be seen in Fig. 7, an accuracy between
measurement and simulation of better than 20% was
achieved. Furthermore, the SGF design has a value for the
on-state capacitance, which is very similar to the LGF design. For the designs where there is much overlap between
the interconnects (as is the case for the 3DI and LGF-W
design), the capacitance is slightly higher.
5 Figures of merit As was demonstrated in previous
section, the modelling framework allowed us to design
power transistors with a lowered gate resistance, with a
minimal impact on the capacitance. In this section several
key figure of merits will be compared.

Figure 8 Normalized on resistance for different designs.

The first FOM is the on-resistance, normalized by the total

gate width. It can be seen from Fig. 8 that it is equal for all
topologies, indicating that there are no adverse effects on
the resistance. This also followed from our models, as the
calculated parasitic source and drain resistances were negligible compared to the resistance of the active channel.


The second FOM is the breakdown squared divided by the

specific on-resistance (normalized by the area of the active
region) and shows for a certain technology the trade-off
between these two parameters (see Fig. 9). There are several topologies which have a lower figure of merit, which
is caused by a vertical breakdown when high and low potential lines cross on different levels of the interconnects.
This behaviour was not unexpected as the inter-metal dielectrics were not optimized for reaching high breakdown
voltages. This optimization will be performed in future
work. The last figure of merit was the on-resistance times
the on-state gate-source capacitance, which is related to the
often used figure of merit of on-resistance times gate
charge. It can be seen in Fig. 10 that all designs perform at
a similar level. The 3DI has slightly higher value for this
FOM due to the increased overlap capacitances. Our models predicted this behaviour, as can be seen from Fig. 7 and
the FOM can be improved by increasing the IMD thickness.

Figure 10 Ron,spCgs,on for different designs.

6 Conclusions For this work we have shown a modelling framework which can, from simple analytical models, give a good description of the interconnect parasitics.
For each of the analysed topologies a good agreement was
achieved between simulated values and measurements. The
SGF/3DI power bar designs reached the design goal of reducing the gate resistance with a factor of 4 to 8 with respect to the long gate finger designs, while having limited
impact on the FOMs Ron,sp, RonCg,son and V 2BD/Ron,sp. The
3DI did exhibited a reduced value for the FOM V 2BD/Ron,sp
due to vertical breakdown at the interconnect crossings.
However, this was expected as no optimization was performed on the inter-metal dielectrics (IMD) and will be
addressed in future process iterations.
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Figure 9 Vbd2/Ron,sp for different designs.

2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim






St. Stoffels et al.: Comparison of AlGaN/GaN MISHEMT powerbar designs

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2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

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