Beruflich Dokumente
Kultur Dokumente
PWP
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RHB
NT
16 CHANNEL LED DRIVER WITH DOT CORRECTION AND GRAYSCALE PWM CONTROL
FEATURES
APPLICATIONS
16 Channels
12 bit (4096 Steps) Grayscale PWM Control
Dot Correction
6 bit (64 Steps)
Storable in Integrated EEPROM
Drive Capability (Constant-Current Sink)
0 mA to 60 mA (VCC < 3.6 V)
0 mA to 120 mA (VCC > 3.6 V)
LED Power Supply Voltage up to 17 V
VCC = 3 V to 5.5 V
Serial Data Interface
Controlled In-Rush Current
30MHz Data Transfer Rate
CMOS Level I/O
Error Information
LOD: LED Open Detection
TEF: Thermal Error Flag
VCC
GND
SCLK
DESCRIPTION
The TLC5940 is a 16-channel, constant-current sink
LED driver. Each channel has an individually
adjustable 4096-step grayscale PWM brightness
control and a 64-step, constant-current sink (dot
correction). The dot correction adjusts the brightness
variations between LED channels and other LED
drivers. The dot correction data is stored in an
integrated EEPROM. Both grayscale control and dot
correction are accessible via a serial interface. A
single external resistor sets the maximum current
value of all 16 channels.
The TLC5940 features two error information circuits.
The LED open detection (LOD) indicates a broken or
disconnected LED at an output terminal. The thermal
error flag (TEF) indicates an overtemperature
condition.
SIN
XLAT
VPRG
IREF
Max. OUTn
Current
VREF =1.24 V
VPRG
1
DCPRG
CNT
1 0
GS Register
DCPRG
1
DC Register
0
GS Counter
CNT
CNT
192
12Bit Grayscale
PWM Control
GS Register
12
23
DCPRG
1
96
95
1 0
VPRG
96
6 DC EEPROM11
Temperature
Error Flag
(TEF)
Constant Current
Driver
OUT1
Delay
x1
VPRG
CNT
Blank
1
6Bit Dot
Correction
DC Register
11 0
96
LED Open
Detection
(LOD)
OUT0
Delay
x0
VPRG
96
192
Constant Current
Driver
6Bit Dot
Correction
0 DC EEPROM 5
Input
Shift
Register
Status 0
Information:
LOD,
TED,
DC DATA
191
12Bit Grayscale
PWM Control
11
0
0
GSCLK
BLANK
Input
Shift
Register
12Bit Grayscale
PWM Control
GS Register
180
191
DCPRG
1
XERR
90
191
90
SOUT
DC Register
95 0
DC EEPROM
95
Constant Current
Driver
OUT15
Delay
x15
6Bit Dot
Correction
VPRG
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
TLC5940
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PACKAGE (1)
PART NUMBER
TLC5940PWP
TLC5940RHB
28-pin PDIP
TLC5940NT
TA
40C to 85C
(1)
For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI website at www.ti.com.
IO
VI
VO
VCC
0.3V to 6V
130mA
V(SOUT), V(XERR)
V(OUT0) to V(OUT15)
0.3V to 18V
V(VPRG)
0.3V to 24V
50
ESD rating
2kV
500V
Tstg
TA
(1)
(2)
(3)
(4)
55C to 150C
(3)
40C to 85C
31.58C/W
QFN (RHB)
35.9C/W
PDIP (NP)
48C/W
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
The package thermal impedance is calculated in accordance with JESD 51-7.
With PowerPAD soldered on PCB with 2 oz. (56,7 grams) trace of copper. See SLMA002 for further information.
TLC5940
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NOM
MAX
UNIT
DC CHARACTERISTICS
VCC
Supply Voltage
VO
VIH
VIL
IOH
VCC = 5V at SOUT
IOL
5.5
17
0.8 VCC
VCC
GND
0.2 VCC
mA
mA
60
mA
120
mA
23
85
IOLC
V(VPRG)
TA
20
22
-40
AC CHARACTERISTICS
VCC = 3 V to 5.5 V, TA = 40C to 85C (unless otherwise noted)
f(SCLK)
SCLK
30
MHz
f(GSCLK)
GSCLK
30
MHz
twh0/twl0
16
ns
twh1/twl1
16
ns
twh2
20
ns
twh3
20
ns
ns
tsu0
tsu1
10
ns
tsu2
10
ns
10
ns
tsu4
10
ns
tsu5
30
ns
tsu6
ms
th0
ns
th1
10
ns
th2
10
ns
10
ns
th4
10
ns
th5
ms
tprog
20
ms
tsu3
Hold Time
th3
(1)
Setup time
DISSIPATION RATINGS
(1)
PACKAGE
POWER RATING
TA < 25C
DERATING FACTOR
ABOVE TA = 25C
POWER RATING
TA = 70C
POWER RATING
TA = 85C
3958mW
31.67mW/C
2533mW
2058mW
2026mW
16.21mW/C
1296mW
1053mW
3482mW
27.86mW/C
2228mW
1811mW
28-pin PDIP
2456mW
19.65mW/C
1572mW
1277mW
The PowerPAD is soldered to the PCB with a 2 oz. (56,7 grams) copper trace. See SLMA002 for further information.
TLC5940
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ELECTRICAL CHARACTERISTICS
VCC = 3 V to 5.5 V, TA = 40C to 85C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
VOL
II
Input current
MIN
TYP
Supply current
VI = GND; VPRG
50
4
10
0.9
5.2
12
16
25
30
60
61
69
mA
0.1
Ilkg
IO(LC0)
IO(LC)
UNIT
V
0.5
VI = VCC; VPRG
ICC
MAX
VCC 0.5
mA
mA
54
IO(LC1)
2
+0.4
IO(LC2)
2.7
+2
%/V
%/V
%/V
%/V
IO(LC3)
IO(LC4)
T(TEF)
V(LED)
V(IREF)
Reference voltage
output
(1)
(2)
(3)
(4)
(5)
R(IREF) = 640
150
1.20
170
0.3
0.4
1.24
1.28
The deviation of each output from the average of OUT0-15 constant current. It is calculated by Equation 1 in Table 1.
The deviation of average of OUT1-15 constant current from the ideal constant-current value. It is calculated by Equation 2 in Table 1.
The ideal current is calculated by Equation 3 in Table 1.
The line regulation is calculated by Equation 4 in Table 1.
The load regulation is calculated by Equation 5 in Table 1.
Not tested. Specified by design
TLC5940
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D(%) =
100
(1)
100
(2)
1.24 V
D(% / V ) =
D(% / V ) =
(3)
(4)
(5)
SWITCHING CHARACTERISTICS
VCC = 3V to 5.5V, TA = -40C to 85C (unless otherwise noted)
PARAMETER
tr0
tr1
tf0
tf1
Rise time
Fall time
TEST CONDITIONS
MIN
TYP
SOUT
MAX
16
10
SOUT
30
16
10
30
UNIT
ns
ns
tpd0
30
ns
tpd1
BLANK to OUT0
60
ns
tpd2
1000
ns
tpd3
60
ns
tpd4
60
ns
tpd5
30
ns
20
30
ns
50
90
ns
td
ton-err
10
TLC5940
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DEVICE INFORMATION
PWP PACKAGE
(TOP VIEW)
GND
BLANK
XLAT
SCLK
SIN
VPRG
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Thermal
PAD
NT PACKAGE
(TOP VIEW)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
IREF
DCPRG
GSCLK
SOUT
XERR
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8
OUT1
28
OUT0
OUT2
27
VPRG
OUT3
26
SIN
OUT4
25
SCLK
OUT5
24
XLAT
OUT6
23
BLANK
OUT7
22
GND
OUT8
21
VCC
OUT9
20
IREF
OUT10
10
19
DCPRG
OUT11
11
18
GSCLK
OUT12
12
17
SOUT
OUT13
13
16
XERR
OUT14
14
15
OUT15
OUT14
OUT13
OUT12
OUT11
20
18
17
OUT15
21
19
SOUT
XERR
23
22
GSCLK
24
RHB PACKAGE
(TOP VIEW)
DCPRG
25
16
OUT10
IREF
26
15
OUT9
VCC
27
14
OUT8
13
NC
NC
28
THERMAL
PAD
OUT6
OUT5
OUT4 8
10
32
OUT3 7
31
XLAT
OUT2 6
BLANK
OUT1 5
OUT7
OUT0 4
NC
11
SIN 2
12
30
VPRG 3
29
SCLK 1
NC
GND
NC No internal connection
TLC5940
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TERMINAL FUNCTION
TERMINAL
NAME
NO.
I/O
DESCRIPTION
DIP
PWP
RHB
BLANK
23
31
Blank all outputs. When BLANK = H, all OUTn outputs are forced OFF. GS counter is also
reset. When BLANK = L, OUTn are controlled by grayscale PWM control.
DCPRG
19
26
25
GND
22
30
Ground
GSCLK
18
25
24
IREF
20
27
26
NC
12, 13,
28, 29
OUT0
28
OUT1
OUT2
OUT3
10
OUT4
11
OUT5
12
OUT6
13
10
OUT7
14
11
OUT8
15
14
OUT9
16
15
OUT10
10
17
16
OUT11
11
18
17
OUT12
12
19
18
OUT13
13
20
19
OUT14
14
21
20
OUT15
15
22
21
SCLK
25
SIN
26
SOUT
17
24
23
VCC
21
28
27
VPRG
27
Multifunction input pin. When VPRG = GND, the device is in GS mode. When VPRG = VCC, the
device is in DC mode. When VPRG = V(VPRG), DC register data can programmed into DC
EEPROM with DCPRG=HIGH. EEPROM data = 3Fh (default)
XERR
16
23
22
Error output. XERR is an open-drain terminal. XERR goes L when LOD or TEF is detected.
XLAT
24
32
Level triggered latch signal. When XLAT = high, the TLC5940 writes data from the input shift
register to either GS register (VPRG = low) or DC register (VPRG = high). When XLAT = low,
the data in GS or DC register is held constant.
No connection
TLC5940
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VCC
23 W
400 W
INPUT
SOUT
23 W
GND
GND
INPUT EQUIVALENT CIRCUIT (IREF)
V(IREF)
VCC
_
400 W
INPUT
23 W
Amp
XERR
100 W
GND
GND
INPUT EQUIVALENT CIRCUIT (VCC)
INPUT
OUT
GND
INPUT EQUIVALENT CIRCUIT (VPRG)
INPUT
GND
GND
TLC5940
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SOUT
RL = 51W
CL = 15pF
Testpoint
OUTn
CL = 15pF
DIO(LC4)
OUTn
VO = 1V
VO = 1V to 3V
V(IREF)
tpd3
VCC
Testpoint
IREF
R (IREG) = 640W
470k
XERR
TLC5940
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TYPICAL CHARACTERISTICS
REFERENCE RESISTOR
vs
OUTPUT CURRENT
10 k
TLC5940PWP
PowerPAD Soldered
7.68 k
1.92 k
1k
0.96 k
0.64 k
0.48 k
0.38 k
0.32 k
100
0
20
40
60
80
100
TLC5940RHB
3k
TLC5940NT
2k
TLC5940PWP
PowerPAD Unsoldered
1k
0
-40
120
-20
IO Output Current mA
80
60
100
TA Free-Air Temperature C
Figure 4.
OUTPUT CURRENT
vs
OUTPUT VOLTAGE
OUTPUT CURRENT
vs
OUTPUT VOLTAGE
65
TA = 25C,
VCC = 5 V
IO = 120 mA
IO = 60 mA,
VCC = 5 V
64
TA = 85C
63
IO = 100 mA
IO - Output Current - mA
IO - Output Current - mA
40
Figure 3.
100
IO = 80 mA
80
IO = 60 mA
60
IO = 40 mA
40
62
61
60
TA = 25C
TA = -40C
59
58
IO = 20 mA
57
IO = 5 mA
56
20
55
0
0
0.5
1
1.5
2
VO - Output Voltage - V
2.5
0.5
1.5
2.5
VO - Output Voltage - V
Figure 5.
10
20
140
120
Figure 6.
TLC5940
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TA = 25C,
VCC = 5 V
IO = 60 mA
4
VCC = 3.3 V
2
0
-2
VCC = 5 V
-4
-6
-8
-40
0
20
40
60
80
TA - Ambient Temperature - C
0
-2
-4
-6
100
20
40
60
IO - Output Current - mA
80
Figure 7.
Figure 8.
OUTPUT CURRENT
vs
DOT CORRECTION LINEARITY (ABS VALUE)
OUTPUT CURRENT
vs
DOT CORRECTION LINEARITY (ABS VALUE)
70
TA = 25C,
VCC = 5 V
IO = 60 mA,
VCC = 5 V
IO = 120 mA
60
100
IO = 80 mA
80
IO = 60 mA
60
40
IO = 30 mA
20
IO - Output Current - mA
IO - Output Current - mA
-8
-20
140
120
TA = 25C
TA = 85C
50
TA = -40C
40
30
20
10
IO = 5 mA
0
0
10
20
30
40
50
Dot Correction Data - dec
60
70
Figure 9.
10
20
30
40
50
Dot Correction Data - dec
Figure 10.
60
70
11
TLC5940
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PRINCIPLES OF OPERATION
SERIAL INTERFACE
The TLC5940 has a flexible serial interface, which can be connected to microcontrollers or digital signal
processors in various ways. Only 3 pins are needed to input data into the device. The rising edge of SCLK signal
shifts the data from the SIN pin to the internal register. After all data is clocked in, a high-level pulse of XLAT
signal latches the serial data to the internal registers. The internal registers are level-triggered latches of XLAT
signal. All data are clocked in with the MSB first. The length of serial data is 96 bit or 192 bit, depending on the
programming mode. Grayscale data and dot correction data can be entered during a grayscale cycle. Although
new grayscale data can be clocked in during a grayscale cycle, the XLAT signal should only latch the grayscale
data at the end of the grayscale cycle. Latching in new grayscale data immediately overwrites the existing
grayscale data. Figure 11 shows the timing chart. More than two TLC5940s can be connected in series by
connecting an SOUT pin from one device to the SIN pin of the next device. An example of cascading two
TLC5940s is shown in Figure 12 and the timing chart is shown in Figure 13. The SOUT pin can also be
connected to the controller to receive status information from TLC5940 as shown in Figure 22.
VPRG
th3
tsu3
twh2
XLAT
1st GS Data Input Cycle
DC
MSB
SIN
th2
SCLK
GS1
LSB
tsu2
GS2
MSB
GS2
LSB
th1
tsu1
96
GS1
MSB
DC
LSB
GS3
MSB
tsu0
twh0
192
193
th0
193
192
tpd0
twl0
-
SOUT
DC
MSB
GS1
MSB
SID1 SID1
MSB MSB-1
SID2 SID2
MSB MSB-1
SID1 GS2
LSB MSB
twh3
BLANK
GSCLK
1
tpd4
4096
tpd3
tpd1
Tgsclk
tpd3
OUT0
(current)
td
tpd1 + td
twh1
tsu4
th4
tpd3 + td
twl1
touton
OUT1
(current)
15 x td
tpd1 + 15 x td
OUT15
(current)
tpd2
XERR
SIN(a)
SIN
SOUT
TLC5940 (a)
SIN
SOUT
SOUT(b )
TLC5940 (b)
SCLK, XLAT,
BLANK,
GSCLK,
DCPRG,
VPRG
TLC5940
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VPRG
XLAT
SIN(a )
SCLK
DCb
MSB
DCa
LSB
GSb1
MSB
192
384
96X2
SOUT(b )
GSb2
MSB
GSa1
LSB
385
GSa2
LSB
GSb3
MSB
385
384
192X2
DCb
MSB
SIDb1 SIDb1
MSB MSB-1
GSb1
MSB
SIDa1
LSB
SIDb2 SIDb2
MSB MSB-1
GSb2
MSB
BLANK
GSCLK
4096
OUT0
(current)
OUT1
(current)
OUT15
(current)
XERR
ERROR INFORMATION
TEMPERATURE
OUTn VOLTAGE
TEF
LOD
TJ < T(TEF)
Don't Care
TJ > T(TEF)
Don't Care
TJ < T(TEF)
TJ > T(TEF)
SIGNALS
BLANK
XERR
H
L
H
L
L
L
13
TLC5940
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OUTPUT ENABLE
All OUTn channels of the TLC5940 can be switched off with one signal. When BLANK is set high, all OUTn
channels are disabled, regardless of logic operations of the device. The grayscale counter is also reset. When
BLANK is set low, all OUTn channels work under normal conditions. If BLANK goes low and then back high
again in less than 300ns, all outputs programmed to turn on still turn on for either the programmed number of
grayscale clocks, or the length of time that the BLANK signal was low, which ever is lower. For example, if all
outputs are programmed to turn on for 1ms, but the BLANK signal is only low for 200ns, all outputs still turn on
for 200ns, even though some outputs are turning on after the BLANK signal has already gone high.
Table 3. BLANK Signal Truth Table
BLANK
OUT0 - OUT15
LOW
Normal condition
HIGH
Disabled
14
TLC5940
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where:
VCC: device supply voltage
ICC: device supply current
VOUT: TLC5940 OUTn voltage when driving LED current
IMAX: LED current adjusted by R(IREF) Resistor
DCn: maximum dot correction value for OUTn
N: number of OUTn driving LED at the same time
dPWM: duty cycle defined by BLANK pin or GS PWM value
OPERATING MODES
The TLC5940 has operating modes depending on the signals DCPRG and VPRG. Table 4 shows the available
operating modes. The TPS5940 GS operating mode (see Figure 11) and shift register values are not defined
after power up. One solution to solve this is to set dot correction data after TLS5940 power-up and switch back
to GS PWM mode. The other solution is to overflow the input shift register with 193 bits of dummy data and latch
it while TLS540 is in GS PWM mode. The values in the input shift register, DC register and GS register are
unknown just after power on. The DC and GS register values should be properly stored through the serial
interface before starting the operation.
Table 4. TLC5940 Operating Modes Truth Table
SIGNAL
DCPRG
L
H
L
H
MODE
GND
192 bit
VCC
96 bit
V(VPRG)
VPRG
DC VALUE
EEPROM
DC Register
EEPROM
DC Register
L
H
EEPROM
Write dc register value to EEPROM. (Default
data: 3Fh)
15
TLC5940
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Figure 14 shows the dot correction data packet format which consists of 6 bits x 16 channel, total 96 bits. The
format is Big-Endian format. This means that the MSB is transmitted first, followed by the MSB-1, etc. The DC
15.5 in Figure 14 stands for the 5th most significant bit for output 15.
MSB
LSB
95
90
DC 15.5
89
DC 15.0 DC 14.5
DC 1.0
DC OUT15
DC 0.5
DC 0.0
DC OUT0
DC OUT14 DC OUT2
DC Mode Data
Input Cycle n+1
VCC
VPRG
SIN
DC n1
LSB
DC n
MSB
DC n
MSB1
DC n
MSB2
DC n
LSB+1
DC n
LSB
DC n+1
MSB
DC n+1
MSB1
twh0
SCLK
95
96
twl0
SOUT
DC n1
MSB
DC n1
MSB1
DC n1
MSB2
DC n1
LSB+1
DC n1
LSB
tsu1
DC n
MSB
DC n
MSB1
DC n
MSB2
twh2
th1
XLAT
16
TLC5940
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V(PRG)
VPRG
VCC
tsu6
tprog
th5
DCPRG
XLAT
SIN
DC
MSB
SCLK
DC
LSB
96
SOUT
DC
MSB
tpd5
OUT0
(Current)
OUT15
(Current)
SETTING GRAYSCALE
The TLC5940 can adjust the brightness of each channel OUTn using a PWM control scheme. The use of 12 bits
per channel results in 4096 different brightness steps, respective 0% to 100% brightness. Equation 9 determines
the brightness level for each output n:
Brightness in % + GSn
100
4095
(9)
where:
GSn = the programmed grayscale value for output n (GSn = 0 to 4095)
n = 0 to 15
Grayscale data for all OUTn
Figure 18 shows the grayscale data packet format which consists of 12 bits x 16 channels, totaling 192 bits. The
format is Big-Endian format. This means that the MSB is transmitted first, followed by the MSB-1, etc.
MSB
191
180
179
12
GS 15.0 GS 14.11
GS 15.11
GS OUT15
GS 1.0
GS OUT14 GS OUT2
11
LSB
0
GS 0.11
GS 0.0
GS OUT0
17
TLC5940
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the grayscale register (see Figure 11). New grayscale data immediately becomes valid at the rising edge of the
XLAT signal; therefore, new grayscale data should be latched at the end of a grayscale cycle when BLANK is
high.The first GS data input cycle after dot correction requires an additional SCLK pulse after the XLAT signal to
complete the grayscale update cycle. All GS data in the input shift register is replaced with status information
data (SID) after updated the grayscale register.
MSB
0
15
16
LOD 15
LOD 0
TEF
LOD Data
23
24
119
120
191
DC 15.5
DC 0.0
TEF
DC Values
Reserved
18
TLC5940
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VPRG
XLAT
1st GS Data Input Cycle
GS1
MSB
SIN
GS2
MSB
> tpd4 + 15 x td + tpd3
tsuLOD
1
SCLK
SOUT
192
GS2
LSB
193
GS1
MSB
SID1
MSB
192
SID1
MSB-1
SID1
LSB
GS2
MSB
BLANK
GSCLK
4096
tpd3
OUT0
(current)
td
OUT1
(current)
15 x td
OUT15
(current)
tpd2
XERR
tpd3 + 15 x td + tpd2
19
TLC5940
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GS PWM
Cycle n
BLANK
t wl1
t wh1
t h4
GSCLK
1
t wl1
t wh3
4096
t su4
1
t pd3
nxt d
t pd1 + td
OUT1
(Current)
2
t pd3
t pd1
OUT0
(Current)
GS PWM
Cycle n+1
t pd3+ n x t d
t pd1 + 15 x td
OUT15
(Current)
t pd2
XERR
(SCLK)
+ 193
(update)
n
(10)
where:
f(GSCLK): minimum frequency needed for GSCLK
f(SCLK): minimum frequency needed for SCLK and SIN
f(update): update rate of whole cascading system
n: number cascaded of TLC5940 device
20
TLC5940
www.ti.com
APPLICATION EXAMPLE
VCC
V(LED)
V(LED)
V(LED)
V(LED)
100 k
OUT0
SIN
XERR
SCLK
SCLK
VCC
100 nF
TLC5940
GSCLK
DCPRG
DCPRG
BLANK
BLANK
SOUT
VPRG
OUT15
SIN
SOUT
XERR
VCC
SCLK
XLAT
GSCLK
OUT0
SOUT
XERR
XLAT
Controller
OUT15
SIN
IREF
100 nF
XLAT
GSCLK
TLC5940
DCPRG
IREF
BLANK
IC 0
VPRG
IC n
W_EEPROM
7
VPRG_D
VPRG_OE
V(22V)
50 k
V(22V)
50 k
50 k
50 k
50 k
50 k
VPRG
21
www.ti.com
29-May-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
TLC5940NT
LIFEBUY
PDIP
NT
28
13
Green (RoHS
& no Sb/Br)
CU NIPDAU
-40 to 85
TLC5940NT
TLC5940NTG4
LIFEBUY
PDIP
NT
28
13
Green (RoHS
& no Sb/Br)
CU NIPDAU
-40 to 85
TLC5940NT
TLC5940PWP
ACTIVE
HTSSOP
PWP
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TLC5940
TLC5940PWPG4
ACTIVE
HTSSOP
PWP
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TLC5940
TLC5940PWPR
ACTIVE
HTSSOP
PWP
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TLC5940
TLC5940PWPRG4
ACTIVE
HTSSOP
PWP
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TLC5940
TLC5940RHBR
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TLC
5940
TLC5940RHBRG4
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TLC
5940
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
www.ti.com
(4)
29-May-2015
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLC5940 :
Addendum-Page 2
27-Jul-2013
Device
TLC5940RHBR
RHB
32
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
330.0
12.4
Pack Materials-Page 1
5.3
B0
(mm)
K0
(mm)
P1
(mm)
5.3
1.5
8.0
W
Pin1
(mm) Quadrant
12.0
Q2
27-Jul-2013
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLC5940RHBR
VQFN
RHB
32
3000
367.0
367.0
35.0
Pack Materials-Page 2
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