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# DIGITIAL ELECTRONICS

Assigment#1
Review Question Problems of
chapter 4

Submit By:

M.Usman

Rafique

Reg.No.:
Fa10-038

Section:
B

BEE-

## Q#1: sketch bjt as a switch and compare

transistor with ideal switch.
Ans:

## When transistors switch is off, there is small collector leakage current in

V CE
v cc
nano amperes exist and so,
is not exact equal to
due leakage
collector current, while in ideal switch we ignore leakage current so
xact equal to

v cc

V CE is e

## When transistors switch is on i.e. in saturation mode then small collector

V =0.
emitter voltage exist, typically about 0.2v while in ideal switch CE

## Q#2: Define saturated switch, nonsaturated

switch, saturation voltage, collector base
leakage current and hfe (min) relation.
Ans: Saturated switch: In saturated switch base-emitter
junction is forward biased and base-collector junction is also forward biased.
V CE
Approaches to 0.2 volts approximately.

## Nonsaturated switch: In nonsaturated switch base-emitter

junction is forward biased, while base-collector junction is reversed biased.

## Saturation voltage: When we increase

V CE is less then0.7

Ic

until

## v then transistor goes to saturation mode then

V CE

is said

to be saturated voltage.

IB

is zero,

Ic

hfe (min):

H FE

h FE

## Relationshipe:When transistor is on saturation voltage occur and when

off leakage current occur and saturation depend on hfe.

Q#4:

ANS:a)
Given:

v cc

=20v; RL=2.2k

h FE (min) =?
I C =20v/2.2k
=9.09mA

h FE (min) =9.09/0.3=30.3

b)

h FE (min)

=50

I B =9.09mA/50=182A

Q#5:

ANS:at R=22k

Ic=25/22=1.136mA

h FE (min) =70
I B =1.136mA/70=16.22mA

At R=2.2k

IB

Ic=25/2.2k =11.36mA

I B =11.36mA/100=114 A

Q#6:

ANS: At R=22k

At saturation
p=ic*

V CE

p=1.136mA*0.2v=0.228mW

=?

IB

=?

At cutoff
P=25*50nA=1.25mW

At R=22k

At saturation
p=11.36mA*0.2v=2.28mW

At cutoff
P=25*50nA=1.25mW

Q#8:

Ans:

v cc

=15v ; R=2.7k

; pulse width=2s

V CE =?

## a)before pulse apply

V CE =15-(50nA)(2.7k )
=14.999

## b)at the end of delay time

V CE =15-0.1(ic)Rc

=15-(0.1

V CE

/Rc)*Rc

=15-0.1*15=13.5v

## c)at the end of storage time

V CE =15-0.9(ic)Rc
=15-(0.9

V CE

/Rc)*Rc

=15-0.9*15=13.5v
=1.5v

ton=20ns

## until transistor switch off

pw+ton=2s+22ns=2.022 s

Q#9:

Ans: To reduce the turn on and turn off time we placed capacitor parallel to the base
resistance. At switch on, capacitor began to charge and

iB

began to increase so

junction capacitance charge fastly and turn on time reduce. At switch off capacitor start
i
to discharge and produce reverse B so, junction capacitance discharge rapidly. this
reduces turn off time.

Q#10:

Ans:R=27k

A)C=?
T=1/100 kHz = 0.01ms
tre=T/2=5 s

tre=2.3cRB
c=5 s/(2.3*27k )=80.5pF

B)f=?
tre=2.3(100pF)( 27k v )
=6.21 s
T=2tre
T=12.42 s
f=1/T=80.5kHz

Q#11:

Ans:In n-channel JFET,at on condition input voltage is zero and to get off condition
we provide negative input voltage, exceeding the

v GS

(off)

Comparision:JFET saturation voltage is less than BJT saturation voltage. It has small
drain-gate leakage current than BJT leakage current. IT has higher input resistance than
BJT.

Q#12:

Ans:a)cut off
v DS=?
v DS=vddi

RD

=20-(0.25nA)( 4.7k )
19.99999=20v

b)switch on
i

=vdd/RL

=20/4.7k =4.26mA
i

V=

)(rds)=

4.26mA(25 = 106mA

Q#14:

## Ans:CMOSE:The complementary combination of n-channel and p-channel

MOSFET term as CMOS.
Advantages: Power dissipation is extremely small compared to other devices. There is
no drain-gate leakage current but there is very small drain-source leakage current .Very
high input impedance.
Disadvantages: CMOS has low frequency response.
CMOS has high capacitance in it.so,its propagation delay is high among the logic
families.