VLSI Design, V sem B.

E (E&C)
Assignment 2 [L. No. L9-L16]
I Design/analysis problems/ descriptive questions
1. Implement the given function S which gives the sum of two inputs with a carry bit, using
NMOS pass transistor logic.
BC

(BC) +
(AB) C + A
S = ABC + A
2. Give the optimal implementation of two input XOR function using
[i] Only n-type/ p-type pass transistors
[ii] TGs
[iii] CMOS gate based approach
3. With the circuit diagram of CMOS inverter explain how the transfer characteristic is
obtained graphically. Explain the working operation of CMOS inverter for different regions.
4. Derive the expression for the Vinv voltage for a CMOS inverter
5. Refer the pass-transistor based logic network given in Fig. 5
[i] Determine the truth table for the circuit. What logic function does it implement?
[ii] Does the PMOS transistor serve any useful purpose?
6. Give the realization of half adder using CMOS gate based logic.
7. Find the midpoint voltage Vx and output voltage Vo, for the chain of two NMOS pass
transistors shown in Fig. 7. Assume VDD = 2.5V and Vthn = 0.5V.
8. Follow the procedure below to construct the CMOS logic gate for the function =
+

[i] Write the equation for the nMOS network.

[ii] Write the equation for the pMOS network.
[iii] Use the equations in (a) and (b) to construct a schematic for f.
[iv] Verify the nMOS and pMOS networks are proper complements (series groups in nMOS
are parallel in pMOS etc.)
9. Give the implementation of 4:1 MUX using a) NMOS pass transistors and b) Transmission
gates
10. Why depletion load NMOS inverter preferred over Enhancement load inverter? Explain
with proper circuit diagram.
11. Find the output voltage for the pass transistor networks shown in Fig. 11. Neglect the body
effect.
12. Derive Zpu/Zpd ratio for NMOS Inverter with depletion mode pull up.

13. Give the circuit implementation for following:

[i] Depletion load NMOS inverter [ii] CMOS Inverter [iii] Two-input NMOS NOR gate [iv]
Three variable NMOS majority function [v] Two-input NMOS EXOR gate [vi] Two-input
CMOS EX-NOR gate [vii] Two-input CMOS NOR gate
14. Derive Zpu/ Zpd for driven NMOS inverter when the input is applied through NMOS pass
transistor.
II Give objective/specific answers
1.
2.
3.
4.
5.
6.
7.

Why length of MOSFET is always kept minimum?

Why does drain current reduce due to body effect?
Is CMOS a ratioed logic? What do you understand by the term ratioed logic?
Why some CMOS gate based circuits use aspect ratios? Explain
What are the advantages of TGs over pass transistors?
Discuss the effect of n/p on the transfer characteristic of CMOS inverter.
Compare the transfer curve for NMOS (with depletion mode pull up) and CMOS
Inverter.
8. Why NMOS pass transistors were preferred over PMOS ones for switch based design?

Fig. 5

Fig. 7

Fig. 11
Date for completion: 3rd Sept 2015
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