Intro To Electronics BJT 2015

Introduction to Electronics
Part - II
Mrinal K Mandal
mkmandal@ece.iitkgp.ernet.in
Department of E & ECE
I.I.T. Kharagpur. 721302.
www.ecdept.iitkgp.ernet.in
Bipolar Junction Transistor (BJT)

One of the most important inventions (John Bardeen, Walter Brattain and
William Shockley at AT & T Bells lab, got Nobel in 1956).
It has three layers (npn or pnp): two pn junctions.
A three terminal device: emitter, base and collector.
Main applications: amplifiers, oscillators, switches, logic gates.
Bardeen
Base
E
Brattain
C
B
Shockley
The first transistors.

Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur
Emitter
p
Collector
BJT
Bipolar Junction Transistor (BJT)

B
B (base)
Base
p
(collector)
(emitter)
C
Conventional
current flow
direction
emitter
collector
B
E
npn- transistor
pnp- transistor
Analogy with a water tap point.
E
E
BJT with a heat sink
Different types of transistors.

3
BJT
Two pn junctions: barrier voltages are negative on the p-side and positive on
the n-side.
Bipolar device: two types of charge carrier are involved in the current flow.
The base region (mid-layer) is thin and lightly doped.
The emitter emits electron in npn, holes in pnp and collector collects them.
In normal operation, the emitter-base junction is forward-biased: carrier
injection.
The collector-base junction is reverse-biased, its depletion region penetrates
deep into the base.
C
emitter base collector

E
p
VEB
+
+
n
+
+
pnp- transistor biasing
VBC
pnp- transistor
Holes are the majority charge

carriers in an pnp device.
BJT Operation
C
emitter base collector

E
n
VBE
p
-
+
+
+
+
npn- transistor biasing
VCB
npn- transistor
Electrons are the majority

charge carriers in an npn device.
Forward bias base-emitter junction works as a diode: majority carriers electron

in n-type emitter drift into p-type base.
Holes also drift from base into emitter small because the base is thin and
lightly doped.
The electrons diffused into the collector-base depletion region they are
drawn across the collector-base junction collected at the collector terminals
(~96-99.5%).
In the bas region, a small percentage of the injected electrons recombines
with holes base current.
BJT Voltages and Currents

IC
IC
RC
IB
VBB
+
C -
RB
VEB
VEC
+
IE
RC
VCC
+
pnp-transistor biasing: common

emitter (CE) configuration.
IB
+
VBB
-
RB VBE
Common base current gain: dc = I C I E .
IB
IC = ( IC + I B ) IC =
.
1
.
IC = I B =
=
1
+1
VCE
IE
npn-transistor biasing: common

emitter (CE) configuration.
IC + I B
Applying KCL, I=
E
Common emitter current gain: dc = I C I B .
+
VCC
-
C +
IC
IE
+
VEE
-
RB
RC
IB
+
VCC
-
npn-transistor biasing: common base

(CB) configuration.
Different Configurations
IC
RC
IB
+
VBB
-
C +
RB VBE
VCE
IE
IC
IE
+
VCC
-
+
VEE
-
RC
RB
IB
+
VCC
-
Common base (CB) configuration.
Common emitter (CE) configuration.
IE
RC
IB
+
VBB
-
E +
RB VBE
VCE
IC
Common collector (CC) configuration.

+
VCC
-
7
BJT Characteristics: Input Characteristics

A
IC
RC
IB
+
VBB
-
20
RB
+
V VCE
-
VBE
-
30
+
VCC
-
IB (A)
10
0
IE
0.3
0.6
0.9
VBE(V)
Input characteristics of a npntransistor in CE configuration.
npn-transistor in common emitter (CE)

configuration.
30
Input parameters: I B , VBE

Output parameters: I C , VCE
20
IB (A)
VBE
Base current: I B = I B 0 exp
V
T
10
0
-0.3
-0.6
-0.9
VBE(V)
Input characteristics of a pnptransistor in CE configuration.
8
BJT Characteristics: Output Characteristics

Input loop:
DC load line
VCC /RC
Applying KVL,
=
VBB I B RB + VBE
15
= 30 A
Saturation
region
Output loop:
IC (mA)
Applying KVL,
V
V
IC =
CE + CC .
RC
RC
= 20 A
10
5
load line
= 0 A
0
0
=
At I C 0,=
VCE VCC and
at=
VCE 0,=
IC
VCC
.
RC
Active
region
= 10 A
Q-point
=
VCC I C RC + VCE
IB = 40 A
12
Cut-off
region
VCC
VCE (V)
Output characteristics for a npn
transistor in CE configuration.
Active region: base-emitter junction is in FB but base-collector junction is in

RB., Saturation region: both junctions are in FB, Cut-off region: both are in RB.
I C I E + I CBO ]
A saturation current component IC = ICBO flows even for IB = 0. [=
Consider VCE|sat = 0.2 V, if the transistor in saturation.
9
Some Important Characteristics

In active region, collector current IC is almost independent of VCE: constant
current source.
IC can be tuned by IB (linear model, function of VBE): voltage controlled current
source.
IC is mostly due to the flow of charges injected from a high-concentration
emitter into the base where there are minority carriers that diffuse toward the
collector: a minority-carrier device.
When using as an amplifier, the DC source supplies the energy required to
amplify a signal: fix the dc operating point (Q-point) first.
Linear approximation (output is an exact replica of the input signal) is valid only
for small signal amplitudes.
Non-linear device:
Does not have a linear relationship between current and voltage.
Examples: diode, transistors.
I = I 0 exp (V VT ) .
10
Voltage Amplification
A BJT works as an amplifier
only in active region and under
proper biasing condition.
In a class A amplifier, Q-point is
so selected that a BJT always
remains in the active region.
Slope of the load line and
hence voltage amplification
depends on RC.
In CE configuration, when the
input voltage (vbe) increases,
the
output
voltage
(vce)
decreases.
Saturation
region
VCC /RC
IC (mA)
ic
IB = 40 A
15
= 30 A
ib
10
= 20 A
Active
region
= 10 A
t (mS)
= 0 A
0
12
Cut-off
region
VCC
VCE (V)
vce
t (mS)
Output characteristics for a npn transistor in

CE configuration.
Maximum possible variation in VCE =

VCC - 0.2 V
11
Why Need Biasing?

In the following circuit, IB changes by 10 A because of a VBE change by 20 mV.
Calculate the change in VCE. Given that = 100.
IC
RC = 6 k
Solutions:
I C =I B =100 20 A =2 mA.
26
VCE =
I C RC =
VCE
VBB = 0.7 V
=12 V .
vb = 20sin t mV
Linear
approximation
40
IB (A)
VBE
VCC =
20 V
IE
Biasing: to set the dc

operating point.
IC = IB, only in active region.
0.7
VBE(V)
Input characteristics of the BJT.
In lab. experiment, dont forget to

switch on the dc power supply.
12
BJT in Saturation
In the previous example, recalculate the change in VCE if RC is changed to 12 k.
IC
Solutions:
RC = 12 k
I C =I B =100 20 A =2 mA.
VCE =
I C RC =
2 12
VCE
VBB = 0.7 V
= 24 V (> VCC ) wrong .
vb = 20sin t mV
VBE
VCC =
20 V
IE
High IB drives the BJT in saturation.

Considering maximum possible variation,
VCE max =
VCC 0.2
=19.8 V
Neglecting the contribution of ICBO.
13
BJT In Saturation
IC
Calculate IB and IC. Given that = 100, RB =

10 k, RC = 1 k, VBB = 5 V and VCC = 12 V.
Solutions:
Applying KVL in the input loop,
=
VBB I B RB + VBE
IB
=
RC
IB
+
VBB
-
RB VBE
+VCC
wrong.
=
31 V ?
12 43 =
VCC I C RC =
So, the transistor is in saturation.
IC
IB
+VBB
RB
Applying KVL in the output loop,
IC
VCE
IE
VBB VBE
5 0.7
=
= 0.43mA.
10k
RB
I C = I B = 43mA
VCE
+
VCC
-
C +
VCC VCE 12 0.2

= = 11.8 mA.
RC
1k
VBE
RC
+
VCE
IE
npn-transistor in CE configuration.
14
BJT Biasing
Biasing: setting up the dc operating point (quiescent point).
Minimize number of dc sources, increase stability of the circuit (eg. VBE and ICBO
depend on temperature, varies widely from transistor to transistor).
Three popular biasing schemes:
1. Base bias
2. Collector-to-base bias
3. Voltage divider bias.
Analysis objectives:
Draw the dc load line (apply KVL for the input and output loops, assume
suitable VBE value)
Identify Q-point (IBQ, ICQ, VCEQ)
Estimate the maximum variation of the output voltage.
15
1. Base Bias
Input loop:
R B=
I B VCC VBE
VCC VBE
IB =
.
RB
+VCC
RB
vin
In forward active region:

IC = I B ,
VBE = 0.7 V( Si),
V
V
CE + CC .
IC =
RC RC
RC
+
VCE
IE
+
VBE
-
0.3 V( Ge) .
vout
Base bias configuration (npn-BJT).
Output loop:
R C=
I C VCC VCE
VCC VCE
I CQ =
RC
VCEQ =VCC R C I C .
Load line:
IC
IB
DC load line I = 40 A
B
VCC /RC
IC (mA)
15
= 30 A
10
= 20 A
=
At I C 0,=
VCE VCC
VCC
=
VCE 0,=
IC
.
RC
= 10 A
Q-point
5
0
= 0 A
0
8
VCE (V)
12 VCC
16
Base Bias
+18 V
Calculate the Q-point values ( = 100).

Solutions:
VCC VBE
18 0.7
I BQ =
470 103
RB
= 36.8 A.
470 k
Assuming
active condition.
=
I CQ =
I BQ
3.68 mA.
VCEQ =
VCC R C I C
=
18 3.68 2.2
= 9 .9 V.
IC
IB
+
VBE
-
2.2 k
+
VCE
IE
Assumption is correct.
Recalculate the Q-point values for = 50.

=
I CQ =
I BQ
1.84mA.
VCEQ =
VCC R C I C
=
13.95 V.
A BJT with the same number

may have wide variation of
(high manufacturing tolerance)
VCEQ changes by 41% when changes by 50%.

17
Base Bias
-18 V
+18 V
+
VEB
-
IC
IB
470 k
VEB
+
2.2 k
VEC
+
IE
IB
470 k
IC
IE
+
VEC
-
2.2 k
pnp transistor in base bias configuration.
In the above circuit, Vcc is changed to 12 V. Calculate the new Q-point ( = 100).
V=
VBE + RB I B
CC
VCC VBE
12 0.7
I BQ
=
=
470 103
RB
= 24 A.
=
I CQ =
I BQ
2.4mA.
VCEQ =VCC R C I C
=12 2.4 2.2
= 6.72 V.
The transistor is working in the

forward active region.
18
Base Bias Circuit Design

Determine the resistor values for the specified Qvalue.
Input loop:
R B I=
VCC VBE
BQ
RB
+VCC
IC
IB
RB
vin
I CQ
VCC VBE
put
=
I
BQ
.
I BQ
+
VBE
-
RC
+
VCE
IE
vout
In forward active region:
VBE = 0.7 V( Si),
0.3 V( Ge) .
Output loop:
R C I CQ = VCC VCEQ
RC =
Base bias configuration (npn-BJT).
VCC VCEQ
.
I CQ
Design a base bias circuit using a Si transistor with = 100 to set the Q-point at
ICQ = 5 mA and VCEQ = 6 V. Use VCC = 12 V.
Solution: I B =
I CQ
= 50
VBE =
A.
0.7 V.
RB =
226 k
and
RC =
1.2 k .
19
2. Collector-To-Base Bias
+VCC
RC
(IC+IB)
B
VCC /RC
15
= 30 A
10
= 20 A
IB
RB
vin
+
VBE
-
+
VCE
-
vout
IC (mA)
IE
npn transistor in collector-tobase bias configuration.
Input loop:
Applying KVL,
VCC= RC (I C + I B ) + RB I B +VBE
V VBE
. where I C = I B .
I B = CC
RB + RC ( + 1)
= 10 A
Q-point
= 0 A
0
12 VCC
VCE (V)
Output loop:
VCC
= R C (I C + I B ) +VCE
VCC VCE
I CQ =
RC (1 + 1 )
load line
VCEQ =VCC RC (1 + 1 ) I C .
At I C 0,=
VCE VCC
=
VCE 0,=
IC
=
VCC
RC (1 + 1 )
VCC
.
RC
20
Collector-To-Base Bias
+VCC
RC
(IC+IB)
B
VCC /RC
15
= 30 A
10
= 20 A
IB
RB
vin
+
VBE
-
+
VCE
-
vout
IC (mA)
IE
= 10 A
Q-point
5
0
= 0 A
0
12 VCC
VCE (V)
The change in resistor position improves bias stability.

Negative feedback effect:
IF IC increases above the design level, VCE decreases.
The reduced VCE level causes IB to be lower than the design value.
Because IC = IB, IC tends to decrease.
21
+18 V
Calculate the Q-point values for = 100. Calculate

the new values if is changed to 50.
2.2 k
(IC+IB)
IB
Solutions:
For = 100:
VCC VBE
IB =
RB + RC ( + 1)
= 35.1
A.
I CQ = I B = 3.51 mA.
VCEQ =
VCC RC (I C + I B )
= 10.2 V.
270 k
For = 50:
IB =
VCC VBE
RB + RC ( + 1)
= 45.3
A.
I CQ = I B = 2.31 mA.
vin
+
VBE
-
+
VCE
-
vout
IE
VCEQ =
VCC RC (I C + I B )
= 12.82 V.
Observe that the change in Q-point values in comparison to base-bias case is

much smaller.
In this case IB is also a function of .
22
+12 V
In the above circuit, Vcc is changed to 12 V.

Calculate the new Q-point values ( = 100).
Solutions:
VCC VBE
IB =
RB + RC ( + 1)
= 23
vin
270 k
A.
I CQ = I B = 2.3 mA.
VCEQ =
VCC RC (I C + I B )
= 6.89 V.
VBE
IB
(IC+IB)
IE
+
VEC
2.2 k
vout
pnp transistor in collector-tobase bias configuration.
23
Collector-To-Base Bias Circuit Design

R B=
I BQ VCEQ VBEQ
VCEQ VBEQ
RB =
I BQ
RC =
VCC VCEQ
.
I BQ + I CQ
+VCC
I CQ
=
=
I
put
, VBE 0.7 V for Si,
BQ
0.3 V for Ge
RC
(IC+IB)
IB
RB
vin
+
VBE
-
+
VCE
-
vout
IE
Design a collector-to-base bias circuit using a Si transistor with = 100 to fix the
Q-point at ICQ = 5 mA and VCEQ = 6 V. Use VCC = 15 V.
Solution:
I CQ
= 50
VBE =
A.
0.7 V.
106 k and RC =
1.78 k .
RB =
I B =
24
3. Voltage Divider Bias

+VCC
Most stable biasing scheme among the

three.
R1 and R2 form a voltage divider.
I1
I2 >>IB VB remains almost constant.
IB
VB
+VCC
I2
I1
R1
I1 = I2
VB
I2
R2
VTh
RTh
RC
R1
R2
+
VBE
IC
+
VCE
-
RE
IE
npn transistor in voltage divider

bias configuration.
The voltage divider and its Thevenin equivalent.
R=
R1 || R=
Th
2
R1R 2
R2
and V=
VCC
.
Th
R1 + R 2
R1 + R 2
25
Voltage Divider Bias: Analysis

+VCC
Input loop:
VTh = RTh I B +VBE + RE (I B + I C )

V VBE
I B = Th
. where I C = I B .
RTh + RE ( + 1)
RC
RTh
Output loop:
VCC = R C I C +VCE + RE (I B + I C )
VCC VCE
V VCE
I CQ
CC
RC + RE (1 + 1 ) RC + RE
IB
VTh
load line
IC
+
VBE
VCE
-
RE
IE
Voltage divider bias using the

Thevenin equivalent.
VCEQ =VCC (RC + RE ) I C RE I B .
=
At I C 0,=
VCE VCC
=
VCE 0,=
IC
VCC
VCC
.
RE + RC (1 + 1 ) RE + RC
26
Voltage Divider Bias

B
VCC /(RC+RE)
IC (mA)
15
= 30 A
10
= 20 A
= 10 A
Q-point
5
0
= 0 A
0
8
VCE (V)
12 V
CC
Load line and the Q-point on the

output characteristics.
27
Voltage Divider Bias

Calculate the Q-point values for = 100.
Recalculate the values for = 50. A Si
transistor has been used.
+18 V
33 k
Solution:
For = 100:
8.8
k
R=
R1 || R=
2
Th
IB
and
VTh VBE
37.3
=
A.
RTh + RE ( + 1)
V=
VCC
Th
R2
R1 + R 2
=4 8 V
IC
+
VCE
-
12 k
IE
1 k

bias configuration.
IC I E
V
VB VBE
I C I E = BE .
RE
RE
VB remains almost constant.
For = 50:
=
I B 68.6
IB
+
VBE
3.73 mA.
IC =
VCEQ =VCC (RC + RE ) I C RE I B =9.76 V.
1.2 k
=
IC
VCEQ = 10.39 V.
3 43 mA
Introduction of an emitter resistor RE

greatly improves the biasing stability.
28
Voltage Divider Bias Design

+VCC
I1
IB
VB
I2
RC
R1
R2
+
VBE
IC
RC
R1
IB
VC
VCE
-
RE
VE
IE

bias configuration.
R2
RE
Equivalent circuit as seen by

any AC source.
VB should be stable I2>>IB.

Avoid low input impedance choose low I2 (because R1||R2 w.r.t. the input
terminals).
VE>VBE.
29
Voltage Divider Bias Design

+VCC
Approximations:
1. I 2 I C 10
3. VE 3=
V for VCC 5 V
=
2. I 1 I 2= 5 V otherwise.
I1
V
I EQ
E
RE =
,
V VCEQ VE
RC = CC
,
I EQ
R2
=
R1
IB
VB
I2
VBQ
(V +VE ) ,
= 10 BEQ
I2
I CQ
RC
R1
R2
+
VBE
IC
VC
+
VCE
-
RE
VE
IE

bias configuration.
V (VBEQ +VE )
VCC VBQ
= 10 CC
.
I2
ICQ
Design a voltage divider bias circuit using a Si BJT with = 100. Fix the Q-point at
ICQ = 5 mA and VCEQ = 5 V. VCC = 15 V.
Answers:
RE =1k , RC =1k ,
R 2= 11.4 k , R1= 18.6 k .
Choose nearest available values of

resistors.
30
Bias Stability
250C
VBE decreases by 1.8 mV (Si) and 2.02 mV

(Ge) for 10C rise in temperature.
ICBO doubles for every 100C rise in
temperature
30
00C
500C
20
IB (A)
(hFE) widely varies from transistor to

transistor.
10
0
1. Q-point is changed.
2. Thermal runway.
+VCC
R1
Rule of thumb: take vcemax < VCC/2.

ICBO
RC
+
=
I C I E + I CBO
If ICBO increases, IC increases increases
temperature of the device cumulative effect
can permanently damage the device (burn out).
0.9
VBE(V)
Effects:
Thermal runway:
0.6
0.3
+
VBE
R2
VCE
-
RE
31
Thermal Stability
Change in ICBO can permanently damage the
device ICBO is the most important parameter.
+VCC
I1
IB
Stability factor:
VB
I C
S =
I CBO
I2
S depends on the circuit configuration and

the bias resistors.
S should be as small as possible.
Base bias:
RC
R1
R2
+
VBE
IC
VC
+
VCE
-
RE
VE
IE

bias configuration.
S= + 1
+1
1 + RC (RC + RB )
+1
S =
1 + RE (RE + R1 || R 2 )
Collector-to-base bias: S =
Voltage divider bias:
32
Thermal Stability
+18 V
+18 V
+18 V
2.2 k
470 k
+
VBE
-
2.2 k
+
VCE
-
1.2 k
+
270 k
Base bias configuration.
33 k
+
VBE
-
+
VCE
-
collector-to-base bias
configuration.
+
VBE
12 k
VCE
1 k
voltage divider bias

configuration.
Calculate the stability factor for the three biasing schemes. In each case, the
same Si transistor with = 100 has been used.
Base bias: S = 101
Collector-to-base bias: S = 56
Voltage divider bias: S = 9.
33
Diode Compensation
VCC
The diode can compensate for the changes in VBE.
V=
VR 2 +VD
B
= VBE +VE
V +VD VBE
I C I E =R 2
RE
V
[If the two junctions have similar
R2 .
RE
characteristics]
R1
RC
+
+
VD
R2
+
VBE
VCE
-
RE

configuration with diode
compensation.
34
AC Analysis of BJT Circuits

+VCC
R1
RC
R1
+VCC
+VCC
IB
vs
Rs
vs
-
R2
RE
Signal source incorrectly

direct-coupled to the
circuit.
Rs
VB = VCC
RS || R 2
. (DC condition)
R1 + RS || R 2
Signal source changes the Qpoint.
+
VBE
vs
R2
Rs
R2
RE
Signal source capacitorcoupled to the circuit.
VB is changed by the
direct-coupled signal
source.
Direct-coupled:
IB
C1
VB
+
VBE
RC
R1
Capacitor-coupled:
VB = VCC
R2
.
R1 + R 2
Always use a coupling capacitor C1

to avoid the change in Q-point by
the signal source.
35
AC Analysis of BJT Circuits

+VCC
+VCC
+VCC
RC
RC
R1
R1
VC
C2
C1
C1
RL
vs
Rs
RC
R2
RL
RE
RE
Load is incorrectly directcoupled to the circuit.
RL
RC + RL
R2
Rs
VC is changed by the
direct-coupled load.
RE
Load capacitor-coupled to
the circuit.
Capacitor-coupled:
Direct-coupled:
VC = VCC
RL
vs
Direct-coupled load changes the

Q-point.
V=
VCC I C RC .
C
Always use a coupling capacitor C2
to avoid the change in Q-point by
the load.
36
Negative Feedback and AC Degeneration

If IC increases above the design level, VCE
decreases.
+VCC
The reduced VCE level causes IB to be lower

than the design value.
RB /2
RC
RB /2
Because IC = IB, IC tends to decrease.

So, voltage change at the collector is fed back
to the base, where it tends to partially cancel
the signal.
CB
For collector-to-base bias RB and for voltage

divider bias RE are the feedback resistors.
+VCC
The above effect produces good bias stability.
C2
C1
The same reaction occurs when an ac signal

is applied to the circuit for amplification.
very low voltage gain.
RC
R1
Rs
AC bypass capacitors are connected to avoid

the above effect.
R2
RE
RL
CE
Corrected circuits.
37
AC and DC Equivalent Circuits

+VCC
+VCC
RC
R1
RC
R1
C2
C1
vs
Rs
R2
RE
CE
The amplifier circuit.
RL
vs
Rs
R1||
R2
RC||
RL
AC equivalent circuit of the

amplifier.
R2
RE
DC equivalent
circuit of the
amplifier.
AC equivalent circuit: replace all the capacitors by short circuits (assume the
capacitance to be high).
DC equivalent circuit: replace all the capacitors by open circuits (capacitors
block dc signal).
RC acts as a load in the ac equivalent circuit when external load RL is absent.
Draw a new load line for the ac source: ac load line.
38
AC Load Line
Q-point is fixed for the AC as well as
DC load lines.
AC load line
B
VCC /(RC+RE)
15
= 30 A
Consider extreme scenario:

When I CQ changes to zero,
I CQ RC
VCE =
IC (mA)
= 20 A
10
].
[consider RL =
= 10 A
Q-point
VCEQ + I CQ RC .
0 v ceQ =
At i c =
= 0 A
0
8
VCE (V)
12
VCC
VCEQ + ICQRC
DC and AC load lines on the output

characteristics.
DC load line remains the same as before.

39
AC Load Line
Draw the DC and AC load line for the following
amplifier (Si BJT with = 100).
+18 V
33 k
Solutions:
DC load line:
I CQ
1.2 k
VCC VCE
V VCE
CC
RC + RE (1 + 1 ) RC + RE
+
VBE
At =
I C 0, V=
V=
18 V
CE
CC
VCC
18
=
=
= 8.18 mA.
VCE 0,=
IC
RE + RC 1 + 1.2
12 k
VCE
1 k

configuration.
AC load line:
Calculate the Q-point values first.
=
=
mA, and VCEQ 9.76 V.
From slide 26: I CQ 3.73
At i c =0, Vce =VCEQ + I CQ RC
[ RL =0].
= 9.76 + 3.73 1.2 V

= 14.24 V.
40
AC Load Line (cont...)

AC load line
B
8.18
= 30 A
= 20 A
3.73
Q-point
IC (mA)
= 10 A
= 0 A
9.76
VCE (V)
18
+VCC
vB
(mV)
vs
(mV)
RC
R1
C1
C2
vE
(mV)
vs
Rs
vC
(V)
R2
RE
CE
vo
(V)
RL
14.24
DC and AC load lines on the output

characteristics.
Note that under any condition IC cannot be more than 8.18 mA (assuming
biasing circuit remains unaltered).
41
Small Signal Hybrid- Model

Assume linear device: only for small signal
Valid only in forward active region.
Small signal parameters:
1. Input resistance r (),
2. Current gain (dimension less),
3. Output resistance r0 (),
VBE : DC value,
v BE : total instantaneous value,
v be : instantaneous AC value.
Input parameters: ib, vbe.
Output parameters: ic, vce.
4. Transconductance gm (-1).
1. Input resistance r:
r =
change in input voltage

change in input current Q-point
i B
=
r v BE
1
i
= b
r v be
ic
+
ib
+
vbe
-
vce
ie
Q-point
BJT as a two-port
device.
Q-point
42

VT
v be
=
r
=
, VT is the thermal voltage,
i b Q-point I CQ
= =
re , re
30
IBQ
1/r
20
IB (A)
VT
called the emitter resistance.
I CQ
10
0
0.3
r is also called the diffusion resistance.
VBE(V)
It is a function of the Q-point.
Calculation of r from the

input characteristics.
2. Current gain :
change in output current

change in input current Q-point
i
= C
i B
i
= c
ib
0.6
VBEQ
IB = 40 A
IC (mA)
15
= 30 A
10
= 20 A
Q-point
5
Q-point
.
Q-point
= 10 A
= 0 A
8
12 VCC
43
VCE (V)
Calculation of .

IB = 40 A
3. Output resistance r0:

change in output voltage
r0 =
change in output current Q-point
=
=
=
v CE
i C
v ce
ic
VA
I CQ
IC (mA)
15
= 30 A
10
= 20 A
Q-point
5
Q-point
Q-point
= 10 A
= 0 A
8
12 VCC
VCE (V)
Calculation of r0.
where V A is the Early voltage.
Consider r0 as infinite if unspecified.
44

4. Transconductance gm:
gm =
change in output current

change in input voltage Q-point
i
= C
v BE
=
=
=
30
ic
v be
I CQ
VT
1
re
IBQ
1/r
20
IB (A)
10
0
Q-point
0.3
VBE(V)
Q-point
Calculation of r and hence gm

from the input characteristics.
where VT is the thermal voltage
1000
VT I CQ
= .
Now, r g m =
I CQ VT
= r g m .
Three parameters are required.
0.6
VBEQ
dc
100
|(j)|
0.707dc
10
1
f 1000
500
Freq. (kHz)
Frequency variation of .
fT
45

ic
ib
ib
ic
+
vce
+
vbe
-
ie
vbe
vce
r0
ib
ic
vce
ie
ib= gmv
Small signal hybrid model of a npn

ic
vbe
+
BJT as a two-port device.
ib
v g v
m
vbe
+
gmv
E
r0
vce
+
Small signal hybrid model of a pnp

46
Calculation of Voltage Gain

+VCC
RC
RB
RB
+
vi
vi
B
v gmv
r0
RC
BJT amplifier.
+
v0
-
AC equivalent circuit using the small

signal hybrid-.
Analysis steps:
Draw the AC equivalent circuit.
Replace the BJT by its small signal equivalent model.
Calculate the input impedance, output impedance and voltage gain of the
circuit.
47
Calculation of Voltage Gain

v =v i
r
.
r + R B
v 0 = g mv ( r0 || RC )
r R
r
=
g m 0 C v i
.
r0 + RC
r + R B
v0
Av =
vi
r R
r
=
g m 0 C
r0 + RC r + RB
r
= g m RC
for r0 .
r + R B
RB
+
vi
B
v gmv
+
r0
v0
RC
AC equivalent circuit using the small

signal hybrid-.
Parallel combination: 5 k||200 k = 4.87 k.
48

+18 V
Draw the small-signal hybrid- equivalence of the

following circuit (Si BJT with = 100 and VA = 500 V).
Solutions:
I CQ = 3.73 mA ( calculated previously).
V
V
26
r = T = 100
r0 = A = 134k.
I CQ
I CQ
3.73
I CQ
=
=
gm =
697 .
143.5 m 1.
VT
RB
R1||R2
v gmv
1.2 k
12 k
1 k

configuration.
+
+
vi
33 k
r0
RC
v0
-
AC equivalent circuit using the small signal hybrid-.

49
Small Signal Analysis of CE Amplifier

+VCC
RC
R1
C2
C1
vs
Rs
R2
CE
RE
vs
RL
Rs

amplifier.

RS
+
vi
-
R1||R2
RC||
RL
R1||
R2
v gmv
r0
RC||RL
v0
-
AC equivalent circuit using the small signal hybrid model.

50

RS
+
R1||R2
vs
r0
v gmv
v0
RC||RL
R1 || R 2 || r
.
v =vs
R1 || R 2 || r + Rs
v 0 = g mv ( r0 || RC || RL )
R1 || R 2 || r
=
g m ( r0 || RC || RL )
v s .
R1 || R 2 || r + Rs
v
vs
0
AVL =
=
g m ( r0 || RC || RL )
= g m (RC || RL )
=
(RC || RL )
Voltage gain without RL:

Av 0 = g m ( r0 || RC )
R1 || R 2 || r
R
g m RC = RC = C .
R1 || R 2 || r + Rs
r
re
R1 || R 2 || r
R1 || R 2 || r + Rs
for Rs 0 and r0 ,
( R || R L ) .
=
C
re
51

ii
+
RS
vi
R1||R2
ib
r
v gmv
iL
ic
r0
RC
+
RL
v0
-
Current gain:
( r0 || RC || RL )
io
Now,
i
=
g
v
o
m
Ai = .
RL
ii
( r0 || RC || RL ) RB || r
R1 || R 2 || r )
(
=
A
g
v
i
m
ib = ii
RL
i b r
r
RC RB
r
.
=
ii ib =
, [ where RB R1 || R 2 ].
R
+
R
R
+
r
(
)(
)
(RB || r )
C
L
B
Av A i .
Power gain: A=
p
52

RS
+
vi
B
r
R1||R2
v gmv
+
r0
RC
v0
-
Ri
Ro
Input resistance is the resistance seen by the AC source.

Output resistance is the resistance seen by the load.
Input resistance Ri = R1 || R 2 || r .
Output resistance
=
Ro r0 || RC RC .
Voltage gain mainly depends on RC and RL. We may end with attenuation
instead of amplification if RL is too small.
53

Calculate the input and output impedances
and the small signal voltage gain of the
amplifier (Si BJT with r = 2.1 k, = 75, ro
= 1 M).
12V
3.9 k
68 k
100 F
100 F
Solutions:
If unspecified, the small signal equivalent
parameters are to be calculated from the
DC biasing condition.
82 k
4.7 k
56 k
Input resistance
=
Ri R1 || R=
1.97k .
2 || r
Output resistance Ro= r0 || RC 3.9k .
47
F
RC =
139.3.
Voltage gain without the load: AV =
r
A
=
133.
(RC || RL ) =
Voltage gain with the load: VL
r
Recalculate the gain if the load is changed to 8 (e.g. a sound box speaker).
Answer: Voltage gain with the load: AVL ( r ) RL = 0.29 ( attenuation).
54
CE Amplifier With an Emitter Resistor

+VCC
RC
R1
C2
C1
vs
Rs
R2
CE
RE
vs
RL
Rs
RS
ic
ib
R1||R2
RC||
RL
RE

amplifier.
vs
R1||
R2
v gmv
r0
RC||RL
E
RE
v0
ib+ib
Equivalent small signal hybrid- model.

55

RS
+
vi
vs
v gmv
r0
RC
RE
v0
ib+ib
-
Rib
Ri
RL
ib
+
R1||R2
ic
Ro
Applying KVL,
v i = i b r + ( i b + i b ) R E
vi
=r + ( + 1) RE .
ib
Rib =
Emitter resistance is multiplied by a factor ( + 1) .
R1 || R 2 || Rib , and
Ri =
Ro RC || ro RC .
=
Output resistance remains almost

unchanged but input resistance increases.
56

RS
+
vs
vi
Ri
v gmv
r0
RC
RL
v0
E
RE
vi =
ic
+
R1||R2
Ri
ib
ib+ib
-
Rib
Ro
vs.
R i + Rs
v0
i R
Ri
For A VL , put (RC || RL ) instead of RC
Av 0 ==
b C
vs
vi
R i + Rs
i
Ri
Ri
1
RC b
= RC
v i R i + Rs
r + ( + 1) RE Ri + Rs
RC
for Rs 0 and ( + 1) RE >> r ,
R
1
+
(
) E
R
C .
Voltage gain decreases.
RE
57

Calculate the input and output impedances
and the small signal voltage gain of the
amplifier (Si BJT with r = 2.1 k, = 75, ro
= 1 M).
12V
3.9 k
68 k
100 F
Solutions:
Rib =r + ( + 1) RE =359.3 k .
Input resistance
Ri R1 || R 2 =
|| Rib 28.3k .
=
Output resistance Ro= r0 || RC 3.9k .
100 F
82 k
56 k
RC
=
0.82.
Voltage gain without the load: AV =
1
+
R
(
) E
4.7 k
58
Small Signal h-Parameter Model

ic
+
ib
+
vbe
-
ib
vce
ie
ic
B
hie (r)
vbe
hrevce
+-
hfeib
(gmib)
E
C
+
1/hoe
(r0)
vce
-
Small signal hybrid model of a npn transistor

in CE configuration and approximate
relationship with r parameters.
Input voltage and output current are expressed in terms of input current
and output voltage.
=
v be hie i b + hrev ce
=
i c hfe i b + hoev ce
59
Small Signal h-Parameter Model

=
v be hie i b + hrev ce
=
i c hfe i b + hoev ce
hie
=
hfe
hre =
=
hoe
v be
ib
ic
ib
r ,
small signal input resistance( ~k
) .
v ce =0
small signal current gain.
v ce =0
v be
v ce
ic
v ce
reverse transverse ratio or voltage feedback ratio( ~10-3 ) .

i b =0
1 ro ,
small signal output conductance( ~10-6 ) .
i b =0
60
Amplifier
Power gain( dB) ,
p
A p = 10log10 o dB
pi
v o2 RL
= 10log10 2
dB
v
R
i
i
v o
20log
=
10
dB [ only when Ri RL ],
v
i
io
20log
=
10
dB [ only when Ri RL ].
ii
Half-power points:
when po
p=
vi
i 2 i .e . v o
vi (mV)
io (po)
ii
(pi)
vo (V)
Ri
Ro
Representation of an amplifier.
2 ,
pi 2
p
i
= 10log10 (1 2 )
Ap = 10log10
= 3.01 3 dB.
61
Frequency Response of an Amplifier

fc1 and fc2 corresponds to the half-power
points and known as the lower and
higher cut-off frequencies, respectively.
30
Ap (dB) 20
The output voltage vo = 0.707vi at the

cut-off frequencies.
Half-power
bandwidth
10
fc1
0
The difference (fc1 - fc2) is known as the

half-power bandwidth of the amplifier.
f0 = (fc1 - fc2)/2 is called the mid-band
frequency or center frequency of the
amplifier.
3 dB
fc2
100 200 300 400

Freq. (kHz)
Frequency response of an amplifier.
1000
dc
100
|(j)|
0.707dc
10
1
f 1000
500
Freq. (kHz)
Frequency variation of .
fT
62
High Frequency Limitation of BJT

High frequency limitations:
1. Junction capacitances: base-emitter
and collector-base junctions are
associated with junction capacitances.
2. Transit time: charge carriers take
finite transit time.
ib
Cbc
ic
+
vbe
Cbe
gmv
vce
r0
Limitation is represented by a cutoff

frequency f where voltage gain falls
to 0.707 of the mid-band value.
High frequency small signal equivalent

circuit of a npn transistor in CE configuration.
Common-emitter cutoff frequency:

falls to 0.707 of the mid-band value
at fe (sometimes f).
Cbc: capacitance of the reversebiased C-B junction.
Common-base cutoff frequency:

falls to 0.707 of the mid-band value
at fb (sometimes f).
Cbe: capacitance of the forwardbiased B-E junction.
f b = f e .
63
High Frequency Limitation of BJT

Unity gain frequency:
fT : in CE configuration, where short-circuited current gain
is unity.
fT
gainbandwidth f b .
For a given device, the gain-bandwidth product

is a constant term that cannot be changed.
Cbe and Cbc are in pF range and their values
depend on the Q-point values.
C be
6.1I E
fT
VCC
RC
Cbc
Cbe
Representation of the
junction capacitances.
Miller effect:
If there is any capacitance (Cio) between the input and output terminals of an
inverting voltage amplifier (-Av), then the equivalent input capacitance (CM)
increases.
CM C io (1 + Av ) .
64
Miller Effect
VCC
VCC
RC
RC
Cbc
Cbe
CM
Cbe
Miller effect.
Change in output voltage Vo because of a change in input voltage V i ,

Vo =
Av V i .
Total collector-base voltage reduction,
VCB =
V i + Av V i =
V i 1 + Av .
Now, charge Q= C change in voltage.
Charge supplied to the input.
Q = C bc (1 + Av ) V i
In CE configuration, total input

capacitance is
C in = C be + (1 + Av )C bc
= C M V i .
65
Frequency Response of a CE Amplifier

+VCC
RC
R1
C1
+
vs
Rs
Rin
vin
Cs
RL
Ro
RC highpass filter.
C1
+
Avvi
C2
vo
vs
Rs
RC lowpass filter.
R2
RE
CE
RL
BJT in CE configuration.
The coupling capacitors (C1 and C2) block low frequency signal: highpass
filtering.
1
For the input side, the corresponding cutoff frequency: f c 1 =
2 RinC1
The input capacitance Cin + stray capacitance (a few hundred pF together)
bypasses high frequency components: lowpass filtering.
Miller effect does not occur in common-base configuration: operates to a much
higher frequency.
66
Noise in BJT Circuit

Thermal noise: because of random thermal motion of electrons in a metal.
Resistors are the main source of noise
rms value of this noise voltage is
en
4h f BR
4kTBR Volt,
exp( hf kt ) 1
[ for
hf <<kT ]
where h 6.626 10 34 J-S is Planck's const.
k 1.37 10 23 J/K is Boltzmann's const.

T temperature( K)
B bandwidth, f - center frequency( Hz)
R resistance(
)
Some other noises: Shot noise (independent of f and T), Flicker noise (1/f),
Transit-time noise (at high frequencies) etc.
Noise =
figure F
S in N in
1( also expressed in dB )
Sout N out
67
Power Dissipation
Power dissipation at an ambient temperature,
PD = I CVCE .
When designing a circuit, consider maximum possible values of the current and
voltage.
PD =
I C maxVCE max
The amplifier shown in the figure uses a 2N3904 BJT (PD = 625 mW at 250C).
Calculate the maximum value of VCC that can be applied without damaging the
device.
VCC
PD = VCC VCC RC
37 V .
VCC =
IC
IB
470 k
+
VBE
-
2.2 k
+
VCE
IE
68
Transfer Characteristics
+12 V
Draw the transfer characteristic of the following

amplifier with = 100.
IC
Solution:
OFF state:
Vi <0.7 (cutoff condition) Vo= 12 V.
Vi
10 k
Vo
IB
470 k
IE
ON state: Vi>0.7 (forward active region)

V 0.7
IC = i
470k
Vo = 12 I C 10k = 12 100
V i 0.7
470k
12
10k
Vo (V)
When BJT is in saturation Vo= 0.2 V

12 0.2 =12 100
V i 0.7
470k
10k
Vi =
4.85 V
0.2
0.7
4.85
Vi (V)
69
Switching Circuit
OFF state (Vout = VCE VCC):
VCC
Vi is low/ negative IB 0
IC = ICBO.
vs
ON state (Vout = VCE 0.2 V):

Vi is high
Capacitor-coupled switching
circuit.
IC VCC /RC.
Design equations:
Off state: check V i
Now , I B I C max
min
VCC
I C max
cut-in voltage.
[choose IC max = 1mA if unspecified]
(V
V
RB RC 1 i max
VCC
CC
V i
RB
max
) V
1
RC 1 i max
Choose RB=
2
VCC
IB = 40 A
VCC /RC
12
IC (mA)
= 30
RC = 1 k
= 3 k
= 20
= 10
CC
RC
+
VCE
-
+
VBE
-
IB = IBmax
the BJT is in saturation,
On state:RC =
RC
RB
the BJT is in cutoff,
6
VCE (V)
=0
VCC = 12
70
Switching Circuit
+6 V
Design a capacitor-coupled stitching circuit using

base-bias configuration. IC should not exceed 1 mA.
The input is a positive square wave of amplitude 5 V
with a PRF = 10 kHz, VCC = 6 V, a Si-BJT with =
100 is to be used.
Solutions:
VCC
= 6 k .
R=
C
I C max
5
RB 100 6 1
6
RB 100 k .
Take =
RB 50 k .
6 k
50 k
vs
+
VCE
-
+
VBE
-
Direct-coupled switching circuit.

VCC
RC
RB
C
+
VBE
-
+
VCE
-
Capacitor-coupled switching circuit.

71
Problems on BJT -1
P1. In the following circuit, a Si BJT with = 150 is used
to design an amplifier. Calculate the emitter resistance re,
Ri, Ro and the small signal voltage gain of the amplifier.
+12 V
IE
IB
Solution:
470 k
12 0.7
= 24.04 A
470k
IC =
3.61 mA
26 mV
re =
= 7.2 .
3.61 mA
ib
B
re
470 k
2.2 k
IC
IB
Ri 470k || 1080
=
= 1077
Ro 2.2 k
=
Now, v o = i b Rc , and v i = i b re .
2.2 k
R
Av =
C =
=
305.5.
7.2
re
+
VEC
-
v gmv
ic
2.2
k
Small signal equivalent circuit.

72
Problems on BJT -2
P2. In the following circuit, a Si BJT with = 100 is used
to design an amplifier. Calculate the emitter resistance re,
Ri, Ro and the small signal voltage gain of the amplifier.
+18 V
2.2 k
100 k 100 k
Solution:
= I B ( + 1) 2.2k + I B 200k
12
18 0.7
= 40.98
A.
200k + 101 2.2k
4.1 mA.
IC =
26 mV
r=
= 6.34 .
e
4.1 mA
IB
Ri = 100k || (100 6.34 )= 630

Ro
100k || 2.2 k =2.15 .
Now, v o =
i b Ro , and v i =
i b re .
2.2k || 100k
Av =
=
339.
6.34
100 k
2.2 k
100 k
AC equivalent circuit.
73
Problems on BJT
P3. In the following circuit, a Si BJT with = 100 is
used to design an amplifier. Calculate the emitter
resistance re, Ri, Ro and the small signal voltage
gain of the amplifier.
18V
2.2 k
330 k
47 F
47 F
Solution:
18
= I B ( + 1) 1 k + I B 330k
IB
18 0.7
= 40.14
A.
330k + 101 1k
10 F
1 k
IC =
4.01 mA.
r=
e
26 mV
= 6.48 .
4.01 mA
R=
330k || (100 6.48=
) 646.7
i
ib
re
330 k
Ro 2.2 k.
Now, v o =
i b re .
i b Ro , and v i =
2.2k
R
Av =
C =
=
339.5.
6.48
re
B
v gmv
ic
2.2
k
Small signal equivalent circuit.
74
Questions
Q1. In the following circuit, a Si BJT with
= 100 is used to design an amplifier.
Calculate the change in no-load voltage
gain if is changed to 200.
12V
4.7 k
33 k
100 F
100 F
100 k
Q2. Design a collector-to-base bias

circuit using a 12 V DC source and a pnp
type Si BJT with = 150 and fix the Qpoint at (5V, 1 mA). Draw the load line.
Redraw the load line if is changed to
200.
22 k
47
F
3.3 k
+VCC
IC
IB
+VBB
RB
VBE
RC
+
VCE
IE
75
Thank you
?
Ph. +91-3222-283550 (o)
Department of E. & E.C.E.
I.I.T. Kharagpur, 721302.
76

Intro To Electronics BJT 2015

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Intro To Electronics BJT 2015

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Introduction to Electronics

Bipolar Junction Transistor (BJT)

The first transistors.

Bipolar Junction Transistor (BJT)

Analogy with a water tap point.

Different types of transistors.

emitter base collector

pnp- transistor biasing

Holes are the majority charge

Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur

emitter base collector

npn- transistor biasing

Electrons are the majority

Forward bias base-emitter junction works as a diode: majority carriers electron

BJT Voltages and Currents

pnp-transistor biasing: common

Common base current gain: dc = I C I E .

npn-transistor biasing: common

npn-transistor biasing: common base

Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur

Common base (CB) configuration.

Common emitter (CE) configuration.

Common collector (CC) configuration.

BJT Characteristics: Input Characteristics

npn-transistor in common emitter (CE)

Input parameters: I B , VBE

BJT Characteristics: Output Characteristics

Active region: base-emitter junction is in FB but base-collector junction is in

Some Important Characteristics

Output characteristics for a npn transistor in

Maximum possible variation in VCE =

Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur

Why Need Biasing?

Biasing: to set the dc

In lab. experiment, dont forget to

Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur

= 24 V (> VCC ) wrong .

High IB drives the BJT in saturation.

Neglecting the contribution of ICBO.

Calculate IB and IC. Given that = 100, RB =

So, the transistor is in saturation.

Applying KVL in the output loop,

VCC VCE 12 0.2

Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur

In forward active region:

VBE = 0.7 V( Si),

Base bias configuration (npn-BJT).

Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur

Calculate the Q-point values ( = 100).

Recalculate the Q-point values for = 50.

A BJT with the same number

VCEQ changes by 41% when changes by 50%.

pnp transistor in base bias configuration.

=12 2.4 2.2

The transistor is working in the

Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur

Base Bias Circuit Design

In forward active region:

VBE = 0.7 V( Si),

Base bias configuration (npn-BJT).

Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur

npn transistor in collector-tobase bias configuration.

Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur