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Energy Gap
Metal
none
Semiconductor
0.5-3 eV
Insulator
> 3 eV
Fermi-Dirac Statisitcs
Gives the probability of occupation of energy levels:
F(E) =
1
1+ e(E "E F )/ kT
n=
Et
Ec
Ec
dE
(E $E F )/ kT
Ec
Ev
Ev
Ev
e(E #E F )/ kT dE
p = " N h (E)dE = " N h (E)dE = " Z (E)
1+ e(E #E F )/ kT
Eb
#$
#$
If the Fermi level is in the middle of the energy gap,
the material is referred to as intrinsic, and we have:
!
n = p = ni
Activation
Energy
V Group
Activation
Energy
0.045 eV
0.045 eV
Al
0.067 eV
As
0.054 eV
Ga
0.072 eV
Sb
0.039 eV
In
0.160 eV
n ~ ND
for p-type
p ~ NA
The Fermi level is shifted with respect to the intrinsic level of the amount:
"F = #
kT $ n i '
kT $ N '
ln& ) for p-doping [V]; "F = # ln& D ) for n-doping [V];
q % NA (
q % ni (
Properties of Silicon
Property
Value
Dimensions
Atomic density
51022
Atoms/cm3
Density
2.33
g/cm3
Atomic weight
28.1
g/mole
Reticular constant
0.543
nm
Thermal conductivity
1.41
!/cm C
Intrinsic resistivity
2.5105
!cm
11.9
8.861014
F/cm
Conductivity
!= !n + !p = q(nn + pp)
for a doped material we have
n~ND
for n-doping
p~NA
np = ni2
hence:
! = qNDn
! = q NAp
for p-doping
for n-doping
for p-doping
Mobility
The following figures show the surface mobility of electrons and holes
as a function of the doping (at room temperature) and a resistivity as a
function of the doping (at room temperature).
Homogeneous material
R=
"L
L
=R
hW
W
Diffused layer
1 W
G= =
R L
1 W
L
# " (z)dz = R $
0
Polysilicon
Grown from pyrolytic decomposition of silane (SiH4) at about 600C.
The polycrystalline structure is made of monocrystal grains size in the
range of 0.1 - 1 "m.
The typical layer are 200 - 600 nm thick with long term standard deviation
in the 2% range.
The mobility is low because of the grain border resistance (30-40 cm2/Vs).
In order to have a low sheet resistance the polysilicon must be strongly
doped (1020-1021 cm-3). Part of the doping saturates the localized levels
due to the grain border. The sheet resistance is in the range 20 - 40 !/".
The sheet resistance can be reduced by using sandwich layers
(polysilicide) made of 200 nm of polysilicon covered with a film of
refractory metal silicide (WSi2, MoSi2 , TiSi2). The sheet resistance is
reduced to 1 - 5 !/".
Analog Design for CMOS VLSI Systems
Franco Maloberti
Silicon dioxide
Thermally grown from silicon in dry or wet conditions at 800 - 1100C.
Property
Value
Dimension
2.22
g/cm3
dielectric strength
2 - 8 106
V/cm
1015
! cm
density
1017
3.4 - 4.2
Growth speed:
Silicon dioxide can also be grown from chemical vapour deposition (CVD):
SiH4 + 2O2 # SiO2 + 2H2O
by pyrolytic decomposition of silane in the presence of oxygen,
at atmospheric pressure (AP-CVD) or at low pressure (LP-CVD).
Analog Design for CMOS VLSI Systems
Franco Maloberti
Value
Dimension
2.22
g/cm3
dielectric strength
2 - 8 106
V/cm
1015 - 1017
! cm
2.7 - 4.2
density
Silicon nitride
Its major use is to protect surface.
It is grown by decomposition of silane or dichlorosilane and
ammonia at 700 - 800C.
3SiH4 + 4NH3 # Si3H4 + 12H2
3SiH2Cl2 + 4NH3 # Si3N4 + 6HCl + 6H2
Growth speed: 10 - 20 nm/min
Resistivity: 1014 - 1016 !/cm
Dielectric strength: 5 - 10 MV/cm
Long term standard deviation: 3 - 4%
Analog Design for CMOS VLSI Systems
Franco Maloberti
CMOS technology
$
$
$
$
Eg
+ " FS
2q
VFB, real =
Eg
Q
+ "FS # SS
2q
Cox
(V
Th
!
Analog Design for CMOS VLSI Systems
Franco Maloberti
2"
VSB # 2$FS
qNA
1. The MOS Transistor
22
QSS + Qimp
Eg
VTh =
" #FS +
+ $ VSB " 2#FS
2q
Cox
"=
!
2q#NA
Cox
!
VTh,0 = VFB, real " 2#FS + $ 2#FS
The threshold voltage can be expressed as:
%
(
VTh = VTh,0 + " ' VSB # 2$FS # 2$FS *
&
)
I-V characteristics
Saturation region
)
1. The MOS Transistor
25
!
dx
dx
dR =
=
"A Qinv (x)W
The drop voltage across the element is:
dV = ID dR =
ID dx
Qinv (x)W
1. The MOS Transistor
26
VDS =
# "V dx
0
We get:
ID = Cox
3/2
3 / 2 (.
!
W+
1 2 2%
" VDB " 2$F *0
- VGS "VTh,0 " # 2$F VDS " VDS + ' VSB " 2$F
)/
L ,
2
3&
ID = Cox
W%
1 2(
' VGS "VTh,0 " # 2$F VDS " VDS *
L &
2
)
Saturation region
As V(x) increases Qinv(x) decreases. Its minimum is at the drain is
if
!
!
"L =
Analog Design for CMOS VLSI Systems
Franco Maloberti
2#
VDS $Vsat
qNA
)
1. The MOS Transistor
28
ID =
#
107
"=
$
qNAL2 L NA
hence in saturation:
ID =
1
W
Cox
VGS "VTh
2
L
) (1+ #V )
DS
Non linear
current source
resistors
diodes
CGS,ov, CGD,ov
Typically: RD # RS # 10 - 50 !
CGS,ov = CGD,ov = W xov Cox
Diodes reversely biased; the reverse current is dominated by
generation recombination term.
IGR = A
qni x j
2" 0
Transconductance
$ Subthreshold region (like a bipolar transistor):
gm = "gmb =
ID
kT
n
q
$ Linear region:
gm = Cox
W
VDS
L
$ Saturation region:
gm = C!ox
W
2ID
W
VGS "VTh =
= 2Cox
ID
L
VGS "VTh
L
1
V
1+ DS
LEsat
$
ucrit"si
= 0 &
& C V #V # u #V
% ox GS on tra DS
'uexp
)
)
(
W
VGS "VTh "VDS
L
$ Saturation region (first order):
gds = Cox
gds = "ID
!
) (
gds = "ID # gm
(first order)
(short channel)
$VTh ID $
$I
+
+ S
$VDS $VDS $VDS
(velocity saturation)
(avalanching)
1. The MOS Transistor
39
Capacitances
$ Linear region:
Ci = CoxWL
Cdep =
"Si
WL
xdep
Cgs = Cgsov +
Ci
2
Cgd = Cgdov +
Ci
2
Csb = Cjs +
Cdep
2
Cdb = Cjd +
Cdep
2
Cgs = Cgsov +
2Ci
3
Csb = Cjs +
2Cdep
3
Cdb = Cjd
!
!
Cj 0
Cj =
1"
Cgb
V
#T
1
"
Ci
10
KT # ND NA &
"T =
ln%
(
q $ ni2 '
Noise
Thermal noise
Due to the finite output resistance:
2
vnth
1
= 4#kT
"f
gm
# = 2/3, for ID = 50 "A, (VGS - VTh) =
300 mV, Vnth = 5.6 nV/'Hz
V =
f2
f1
2
vnth
2
1
df = 4 kT
BW
"f
3
gm
Flicker noise
Due to the trapping and detrapping of carriers by surface
states at different energy levels.
Modeled as:
inf2
2K I
= k f2 D #
"f Coxc L f
vnf2
inf2
2 Kf ID
Kf
=
=
=
kc 2 #
k c +1
"f !"f gm2 Cox
L f gm2 Cox
W L f#
Typically ( ) 1, kf ) 1, kc + 1 ) 1,
Vnf = 40 nV/'Hz at 1 kHz with WL = 1000 "m2.
!
Analog Design for CMOS VLSI Systems
Franco Maloberti
Avalanche noise
Due to the statistical fluctuation in the number of carriers of
the avalanche current (shot noise). Modeled as:
2
2
vnav
inav
=
=
2
"f
"f gm
q Iav
W
Cox
ID
L
If we compare thermal noise and avalanche noise, we have:
2
nav
i
= 2 q Iav
"f
2
vnav
=
2
vnth
q Iav
gm
VGS #VTh Iav
=
!
W
4"kT
k T ID
Cox
ID
4"
L
q
we get comparable noise if ID / Iav is of the same order of
(VGS - VTh) / (kT/q). The avalanche current at VDS = 5 V can
be of the order of 0.5 1 "A.
!
To minimize noise
$ Thermal noise:
$ use large gm (large W / L)
$ use low series resistance (connection and gate
resistance)
$ Flicker noise:
$ use large device area (W L)
$ use thin oxide (high Cox)
$ use "clean" technology (low NSS)
$ try to get buried channel
$ use p-channel devices
$ Avalanche noise:
$ reduce VDS
$ use p-channel devices
Analog Design for CMOS VLSI Systems
Franco Maloberti
Layout
Rules
$ Use poly connections only for signal, never for current because the
offset R I # 15 mV.
$ Minimize line length, especially for lines connecting high impedance
nodes (if they are not the dominant node).
$ Use matched structure. If necessary common centroid arrangement.
$ Respect symmetries (even respect power devices).
$ Only straight-line transistors.
$ Separate (or shield) the input from the output line, to avoid feedback.
$ Shielding of high impedance nodes to avoid noise injection from the
power supply and the substrate.
$ Regular shape.
Analog Design for CMOS VLSI Systems
Franco Maloberti
Layout of transistors
The MOS transistor is a overlap of two rectangles: active area
(not protected, to originate the source and the drain) and
polysilicon gate.
Key points:
$ parasitic resistance at
source and drain must kept
as low as possible
$ parasitic capacitances must
be minimized
$ matching between paired
elements is very important
Analog Design for CMOS VLSI Systems
Franco Maloberti