Low Power 10-Transistor Full Adder Design Based on

Degenerate Pass Transistor Logic

Jin-Fa Lin

Yin-Tsung Hwang

Ming-Hwa Sheu

Dept. of Info. & Comm. Engr.

Taichung, Taiwan

Dept. of Electrical Engr.

Taichung, Taiwan

Dept. of Electronic Engr.,

Yunlin, Taiwan

AbstractA low power, low complexity full adder design based on

degenerate pass transistor logic (PTL) is described. The design
kernel is a logically degenerate 5-transistor XOR-XNOR module
supporting complementary outputs. In spite of the logic deficiency,
this module functions properly in the context of full adder
applications. The threshold loss problem common in most PTL
designs can be alleviated due to the availability of complementary
control signals. Combining this module with multiplexing modules,
a novel full adder design using as few as 10 transistors us derived.
The proposed full adder design features the least output signal
degradation and the smallest Vdd operations against other 10-T
counterpart designs. The performance edges in speed, power and
power-delay product are also proved via post layout simulations.

(a)

Fig. 1. XOR-XNOR designs using 5 transistors. (a) Inverter-based design. (b)

Proposed design. (c) Truth table of proposed design.

Since the XOR module implements the carry propagate signal,

any signal degradation causes further signal degradation in the
following PTL modules. The consequence is multiple threshold
voltage loss at full adder outputs. Complementary XOR-XNOR
signals help alleviate the problem in that transmission gate (TG)
logic can be used in lieu of PTL in the following stages. This,
however, calls for extra transistors. In [9], a 5-T XOR-XNOR
design [9] using the combination of pseudo NMOS and PTL
design is proposed to support complementary outputs. In spite of
its effort in minimizing the transistor count, the design suffers
from a severe DC power consumption problem. In [3], a cross
coupled 6-T XOR-XNOR design is presented. The signal feedback
provides a certain degree of output level restoring but induces
extra power consumption in overwriting the latch output (latch
breaking problem) [2]. So far, no satisfactory low gate count
XOR-XNR designs have been devised.
In this paper, as shown in Fig. 1(a), a 5-T XOR-XNOR design is
devised by removing the weak pull-up transistor at the XNOR
output from the 6-T design. The implication of this design
measure is three fold. Firstly, this helps eliminate the latch
breaking problem to achieve a higher switching speed. Secondly,
the design is Vdd free for low power operations. Thirdly,
minimum size transistors can be employed due to the absence of
signal cross coupling.

I. INTRODUCTION
Full Adder is probably the most basic element in all
arithmetic module design. Numerous full adder designs have
been proposed targeting on various design emphases such as
power, speed and circuit complexity. Among them, low
transistor count full adder designs in pass transistor logic (PTL)
have been actively pursued to reduce the circuit complexity for
low power operations. Designs using as few as 10 transistors
(10-T) were reported in the literature [4-6]. In spite of the circuit
simplicity, these designs suffer from severe output signal
degradation problem and cannot sustain low voltage operations
[7]. In this paper, a new 10-T full adder design aimed at
alleviating these shortcomings is presented. The key of the
design is the employment of a degenerate (logically incomplete)
XOR-XNOR module using only 5 transistors. Although the
module is not logically complete under all input combinations, it
is sufficient to function properly in full adder applications. Its
capability of providing complementary propagate control
signals helps reduce the voltage degradation in the output
generation stages. Compared to its design counterpart [8], the
proposed XOR-XNOR design is also free of DC power
consumption and latch breaking problem. Combining the 5T
XOR-XNOR logic with multiplexer based sum and carry
modules leads to our 10T full adder design. Extensive
simulations are conducted to show the merits of our design.

The truth table of the design is given in Fig. 1(b), where 0+

and 1 indicate degraded signals, i.e. |Vtp| and (Vdd-Vtn), due
to threshold voltage loss. Further analysis shows that
degradation occurs only when both inputs are equal. In the case
of both inputs equal to 1, the XNOR output encounters one
threshold voltage loss. In the case of both inputs equal to 0, the
XNOR output becomes floating. The design is thus considered
logically degenerate. In spite of this, it will be shown later that
the design can function properly in the context of full adder
operations.

II. PROPOSED 10T FULL ADDER DESIGN

A. Degenerate XOR-XNOR Design
Most low transistor count full adder designs adopt 3-module
implementations, i.e. XOR (XNOR), sum and carry modules [1].
For PTL based designs, as few as 4 transistors can be used to
implement a XOR (or XNOR) module [5,8] but the design
encounters severe threshold voltage loss problems.

978-1-4673-0219-7/12/$31.00 2012 IEEE

(b)

496

B. 10-T Full Adder Design

The proposed 10-T full adder design incorporating the
aforementioned XOR-XNOR module is shown in Fig.2. It follows
conventional 3-module implementations but is facilitated with
complementary signals (XOR-XNOR). The Boolean equations of
Sum and Cout are
Sum = ( A B) C + ( A B) C
Cout = ( A B) C + ( A B) A

(a) sum module

(1)
(2)

With the availability of complementary control signals, the

selection of the pass transistor types in realizing the sum and
carry modules becomes more flexible to avoid the occurrence of
multiple threshold voltage loss. The degradation in output
voltage swing can thus be minimized, which makes the design
more sustainable in low Vdd operations. We next examine the
sum module, which implements an XOR function ( Sum = P C )
by way of 3 pass transistors. In Fig. 3(a), the truth table is
decomposed into three sub-tables, each implemented by a pass
transistor. For logically intact XOR-XNOR modules, pass
transistors P1 and N1 are sufficient to realize the XOR function in
the sum module. Because the ~P (XNOR input) signal could
become floating, additional pass transistor P2 is added to tackle
the problem. P2 can also collaborate with N1 in the case of
non-floating but degraded ~P to achieve an intact output "1".
When C equals "0", P2 along with P1 are used to drive signal "0".
Since both P1 and P2 are p type pass transistors, this pMOS
transistor pair helps speed up the signal propagation, although
one |Vtp| loss is still inevitable. The resultant truth table of the
sum module indicates the design can function properly and be
able to deliver intact signal 1.
We will next address the behaviors of ~P & P signals in the
presence of sum module. Recall that ~P is floating when (A,B)
equals (0,0). If C equals 1 when (A,B) equals (0,0), both P2
and N1 are turned on and signal C propagates not only to the
output node but also to node ~P as signal 1 . This turns on
transistor Nd and the P (XOR) signal can be fully discharged to
GND. If C equals 0 when (A,B) is (0,0), the pull-up path no
longer exists and node ~P retains its previous value, which is
either 1 or 0. The former conforms to the case of C equal to
1 while the latter leads to a situation where P and ~P equal
0+ and 0, respectively. This, however, does not interfere in
the functionality of the carry module. The truth table of the
degenerate XOR-XNOR module in presence of sum module is
given in Fig. 3(b).

Fig. 2. Proposed 10-T full adder design.

497

(b) the degenerate XOR/XNOR module

Fig. 3. Truth Tables of PTL design modules

The carry module is actually a 2-to-1 multiplexer, which

implements the Boolean expression Cout = P C + P A . The
multiplexer is realized by two pMOS, rather than nMOS,
transistors to avoid the threshold voltage loss in propagating
signal 1. Transistor P3 is responsible for the term P A while
transistor P4 implements the term P C . Note that signal P
exhibits full voltage swing due to the signal feedback from the
sum module. Signal ~P has an intact output 0 and a degraded
output 1 , which puts P4 on the brink of conduction but does
not cause any obvious side effect. When P and ~P equal 0+
and 0, respectively, they are no longer complementary and
cause both P3 and P4 turned on. Despite the loss of
complementary property, no signal conflict occurs because
signals A and C are both equal to zero. Furthermore, P3 and P4
now work in parallel to enhance the propagation of signal "0".
Although our carry module design has degraded signal 0+, its
output signal 1 remains level intact, which is beneficial to the
carry propagation speed in ripple adder applications.
III. SIMULATION RESULTS
To verify the performance edges of the proposed design,
seven 10T full adder designs in total are compared. The circuit
schematics of these designs are shown in Figure 4. They all
adopt 3-module implementations and are named as XOR-FA [4],
9A [5], 9B [5],13A [5], CLRCL [6] and CP-FA, respectively.
CLRCL (Complementary and Level Restoring Carry Logic) is
our previous version of 10-T full adder design featuring low
power operations and fast carry signal propagation. CP-FA
design differs from the proposed one by replacing the
degenerate XOR-XNOR module with the design shown in Fig.
1(a). All but the proposed and the CP-FA designs do not provide
complementary XOR-XNOR signals. The simulation is done by
using HSPICE and the TSMC 1P6M 0.18um CMOS process
technology. The simulation conditions are 100MHz input
toggling rate and 1.8V Vdd. Typical transistor sizes, i.e. (pMOS
/nMOS)=1.0m/0.5m in width and 0.18m (minimum feature
size) in length are applied to all but the weak pull-up pMOS in
CP-FA design. The test sequence consists of 56 (87) patterns
to enumerate all possible input transitions. Both input and output
signals are buffered with inverters. The outputs are further
loaded with a 5.6fF capacitor (FO4).
DC analysis results of these 10T full adder designs are
compiled into Table I. Each Cout table entry for CLRCL design
has two values because it is available in a complementary form.

TABLE I. DC ANALYSIS RESULTS OF 10T FULL ADDER DESIGNS

10T FA Designs Cout_Himin Cout_Lomax Sum_Himin Sum_Lomax

XOR-FA [4]
Vdd-Vtn
2|Vtp|
13A / 9A / 9B [5] Vdd-2Vtn
|Vtp|
CLRCL [6]
Vdd-Vtn /Vdd |Vtp| /Gnd
CP-FA
Vdd
|Vtp|
Proposed 10T
Vdd
|Vtp|
(a) XOR-FA [4

(b) 9A [5]

(c) 9B [5]

Vdd
Vdd-2Vtn
Vdd-Vtn
Vdd
Vdd

threshold voltage loss problems.

In terms of power consumptions, the proposed design leads
again. Although the CP-FA design differs from the proposed
design in the XOR-XNOR module only, its power consumption is
15% more power than that of the proposed design. Our design,
along with 13A, 9A and 9B designs, has a quite small DC
(leakage) power consumption at a range of several nano-watts.
CLRCL design sees a bigger power consumption number owing
to the DC power consumption of two level restoring inverters. It
is of no surprise that the CP-FA design, employing pseudo
nMOS logic in its XOR-XNOR module, is ranked in the last place
in DC power consumption.
The proposed design also excels the rest of the 10T FA
designs by a large margin in a compound performance metric
PDP. The runner-up is the CLRCL design. CP-FA design,
thanks to its speed advantage, compensates the loss in power
consumption and takes the third place. All designs using unitary
propagate control signal except the CLRCL design are inferior
in this performance category. More performance analyses on
delay and PDP versus supply voltage are shown in Fig. 5. The
supply voltage varies from 1.6V to 2.4V and the working
frequency remains as 100MHz. Again, the proposed design
outperforms the other designs in all cases. Note that not all
designs function properly under these settings. Only the
proposed design, the CLRCL and the CP-FA designs survive in
all supply voltages.
Table II also lists the actual layout areas of all designs. No
significant variation in layout areas is observed except for the
CP-FA design, which employs a pseudo nMOS XOR-XNOR
module. Fig.6 shows the simulation waveforms of the proposed
design. All 56 possible transitions are included in the input
patterns. The Sum and Cout waveforms are probed before the
output buffers. Both waveforms show level intact 1 signals.
Degraded Sum signal occurs when (A,B,C) equals (0,0,0) and
(1,1,0). Note that the voltage deviation is somewhat bigger than
the generic threshold voltage due to the influence of body effect.
For the Cout signal, output 0 deviates with one threshold
voltage. A subtle difference in Cout values between the case of
input as (0,0,0) and the case of other input combinations exists.

(d) 13A [5]

(e) CLRCL [7]

Fig. 4. 10-T full adder designs.

For output voltage levels, the proposed design and CP-FA

design suffer the least output voltage swing degradation. The
XOR-FA design exhibits the severest threshold voltage loss (up
to three Vts). Since the proposed design faces only signal 0
degradation, the adverse effect on the trailing stages DC power
consumption can be alleviated by tweaking the size of pull down
nMOS transistor. If both signal 0 and signal 1 degradations
occur, a much more expensive latch based signal keeper circuit
must be employed to remedy the problem. The range of output
voltage swing also affects the minimum supply voltage. As
shown in Table II. The proposed design can operate at a Vdd as
low as 1.4V. CP-FA design ranks in the second place followed
by CLRCL design. Designs 9A, 9B and 13A all need a 1.8V Vdd
to function properly at 100MHz [2]. XOR-FA design requires
the largest Vdd value (2.1V) and fails to function correctly under
our simulation setting (100MHz/1.8V).
The proposed design also features the shortest Cout delay
(0.85ns) trailed by the CLRCL design. The CP-FA design
assumes the third spot. The remaining 13A, 9A and 9B designs
show much longer Cout delays mostly attributed to their severe

TABLE II. 10-T FULL ADDER DESIGN SIMULATION RESULTS @1.8V/100MHZ

10T Full Adder Designs

XOR-FA

13A

Layout Area (um2)

Minimum Supply Voltage
Cout Delay (nS)
Average Power Consumption (uW)
DC Power Consumption (nW)
Power-Delay-Product (pJ)

60.63
2.1

66.12
3.84
39.01
2.48
149.8

|Vtp|
|Vtp|
|Vtp|
|Vtp|
|Vtp|

9A

9B

CLRCL

CP-FA

Proposed 10T

3.92
43.07
3.93
168.83

59.35
1.55
1.52
39.82
383
60.53

80.42
1.5
2.18
38.24
8260
83.36

64.99
1.4
0.85
33.25
5.26
28.26

64.84
1.8
4.11
36.68
5.36
150.75
498

4.5

9A

9B

13A

CP-FA

CLRCL

Proposed

300

XOR-FA

9A

9B

13A

CP-FA

CLRCL

Proposed

XOR

4
250

Power Delay Product (fJ)

Delay (nS)

3.5
3
2.5
2
1.5

200

150

100

1
50

0.5
0

1.6v

1.6V
1.8V
2.0V
2.0v
2.2v
2.4v
Voltage
Supply Voltage
(a)
(b)
Fig. 5. 10-T full adder design performances versus supply voltages (a) Delay. (b) Power-Delay Product.

1.8v

2.2V

2.4V

In the former case, both pMOS transistors (P3 & P4) are turned
on simultaneously to propagate signal 0. A slightly smaller
output threshold voltage loss is thus observed.
IV. CONCLUSION
In conclusion, a 10-T full adder design based on degenerate
PTL module is presented. Complementary propagate control
signals are provided, though not "logically complete", are
provided by a 5-T XOR/XNOR logic module. With this
measure, multiple-threshold-voltage loss problem common in
PTL full adder designs can be greatly alleviated, which leads to
better speed and power performance than other counterpart
designs. The carry and sum module designs are based on two
multiplexing structures and employ only 5 transistors.
Simulation results did indicate that the proposed design
outperforms other 10T counterparts in various metrics such as
power, delay and power-delay product.

Fig. 6.Simulation waveforms of proposed 10-T full adder design.

[5] H. T. Bui, Y. Wang, and Y. Jiang, Design and analysis of

low-power 10-transistor full adders using XORXNOR gates,
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol.
49, no. 1, pp. 2530, Jan. 2002.
[6] J.-F. Lin, Y.-T. Hwang, M.-H. Sheu and C.-C. Ho, A novel high
speed and energy efficient 10-transistor full adder design, IEEE
Trans. Circuits Syst. I, vol. 54, no. 5, pp. 10501059, May 2007.
[7] Y. Jiang, Al-Sheraidah. A, Y. Wang, Sha. E, and J. G. Chung, A
novel multiplexer-based low-power full adder, IEEE Trans.
Circuits Syst. II, Analog Digit. Signal Process., vol. 51,
pp.345348, July 2004.
[8] J. Wang, S. Fang, and W. Feng, New efficient designs for XOR
and XNOR functions on the transistor level, IEEE J. Solid-State
Circuits, vol. 29, pp. 780786, July 1994.
[9] J.-B. Kim, et al., New circuits for XOR and XNOR circuits,
International Journal of Electronics, vol. 82, pp. 131143, Feb.
1997.

REFERENCES
[1] S. Goel, A. Kumar, and M. A. Bayoumi, Design of robust,
energy-efficient full adders for deep-submicrometer design using
hybrid-CMOS logic style, IEEE Trans. Very Large Scale Integr.
(VLSI) Syst., vol. 14, no. 12, pp. 13091321, Dec. 2006.
[2] C.-H. Chang, J. Gu, and M. Zhang, A review of 0.18-um full
adder performances for tree structured arithmetic circuits, IEEE
Trans. VLSI, vol. 13, no. 6, pp. 686695, Jun. 2005.
[3] D. Radhakrishnan, Low-voltage low-power CMOS full adder,
IEE Proc. Circuits Devices Syst., vol. 148, no. 1, pp. 1924, Feb.
2001.
[4] A. Fayed and M. A. Bayoumi, A low-power 10 transistor full
adder cell for embedded architectures, in Proc. IEEE Int. Symp.
Circuits Syst., 2001, pp.226229.

499