Beruflich Dokumente
Kultur Dokumente
MC68HSC705C8A
Technical Data
M68HC05
Microcontrollers
MC68HC705C8A/D
Rev. 3, 3/2002
WWW.MOTOROLA.COM/SEMICONDUCTORS
MC68HC705C8A
MC68HSC705C8A
Technical Data
Motorola and the Stylized M Logo are registered trademarks of Motorola, Inc.
DigitalDNA is a trademark of Motorola, Inc.
0&+&&$ 5HY
027252/$
7HFKQLFDO'DWD
Technical Data
Revision History
Date
May, 2001
March, 2002
7HFKQLFDO'DWD
Revision
Level
2.1
Description
Page
Number(s)
29
33
192
195
0&+&&$ 5HY
027252/$
List of Sections
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
List of Sections
List of Sections
Technical Data
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Table of Contents
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.4
Programmable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.6
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.7
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
1.7.1
VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.7.2
VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.7.3
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.7.4
External Reset Pin (RESET) . . . . . . . . . . . . . . . . . . . . . . . .32
1.7.5
External Interrupt Request Pin (IRQ) . . . . . . . . . . . . . . . . . . 32
1.7.6
Input Capture Pin (TCAP) . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.7.7
Output Compare Pin (TCMP) . . . . . . . . . . . . . . . . . . . . . . . .33
1.7.8
Port A I/O Pins (PA7PA0). . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.7.9
Port B I/O Pins (PB7PB0). . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.7.10 Port C I/O Pins (PC7PC0) . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.7.11 Port D I/O Pins (PD7 and PD5PD0) . . . . . . . . . . . . . . . . . . 33
Section 2. Memory
2.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.3
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.4
Input/Output (I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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2.5
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.6
EPROM/OTPROM (PROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.7
Bootloader ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.2
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.4
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.4
Section 4. Interrupts
4.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.3
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.3.1
Software Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.3.2
External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.3.3
Port B Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
4.3.4
Capture/Compare Timer Interrupts . . . . . . . . . . . . . . . . . . .55
4.3.5
SCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.3.6
SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.4
Section 5. Resets
5.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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5.3
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.3.1
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3.2
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3.3
Programmable and Non-Programmable
COP Watchdog Resets . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3.4
Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.3
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.3.1
SCI During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
6.3.2
SPI During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.3.3
Programmable COP Watchdog in Stop Mode . . . . . . . . . . . 71
6.3.4
Non-Programmable COP Watchdog in Stop Mode . . . . . . . 73
6.4
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.4.1
Programmable COP Watchdog in Wait Mode . . . . . . . . . . . 75
6.4.2
Non-Programmable COP Watchdog in Wait Mode . . . . . . . 75
6.5
Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
7.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7.3.1
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7.3.2
Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.3.3
Port A Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.4.1
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.4.2
Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.4.3
Port B Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
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7.5
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.5.1
Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.5.2
Data Direction Register C. . . . . . . . . . . . . . . . . . . . . . . . . . . 86
7.5.3
Port C Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.6
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
8.3
Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
8.3.1
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
8.3.2
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
8.4
Timer I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
8.4.1
Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
8.4.2
Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8.4.3
Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
8.4.4
Alternate Timer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 98
8.4.5
Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 100
8.4.6
Output Compare Registers. . . . . . . . . . . . . . . . . . . . . . . . . 101
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
9.3
EPROM/OTPROM (PROM) Programming . . . . . . . . . . . . . . . 104
9.3.1
Program Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
9.3.2
Preprogramming Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
9.4
PROM Programming Routines . . . . . . . . . . . . . . . . . . . . . . . . 111
9.4.1
Program and Verify PROM. . . . . . . . . . . . . . . . . . . . . . . . . 111
9.4.2
Verify PROM Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
9.4.3
Secure PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
9.4.4
Secure PROM and Verify . . . . . . . . . . . . . . . . . . . . . . . . . . 113
9.4.5
Secure PROM and Dump. . . . . . . . . . . . . . . . . . . . . . . . . . 113
9.4.6
Load Program into RAM and Execute . . . . . . . . . . . . . . . . 114
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9.4.7
9.4.8
9.5
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
9.5.1
Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
9.5.2
Mask Option Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
9.5.3
Mask Option Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9.6
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
10.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
10.4
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
11.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
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11.6
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.6
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Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
13.3
13.4
13.5
13.6
13.7
13.8
13.9
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
14.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
14.3
14.4
14.5
14.6
14.7
14.8
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Section 15. Ordering Information
15.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
15.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
15.3
Appendix A. MC68HSC705C8A
A.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
A.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
A.3
A.4
A.5
A.6
A.7
A.8
A.9
Index
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
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List of Figures
Figure
Title
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
1-10
1-11
2-1
2-2
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3-1
3-2
3-3
3-4
3-5
3-6
4-1
4-2
4-3
4-4
4-5
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List of Figures
Figure
5-1
5-2
5-3
5-4
6-1
6-2
6-3
Title
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-10
8-9
8-11
8-12
9-1
9-2
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Figure
Title
9-3
9-4
9-5
9-6
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
13-1
13-2
13-3
13-4
13-5
13-6
13-7
13-8
13-9
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List of Figures
Figure
14-1
14-2
14-3
14-4
14-5
14-6
Title
Technical Data
18
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List of Tables
Table
Title
2-1
Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4-1
5-1
7-1
7-2
7-3
9-1
9-2
10-1
10-2
10-3
11-1
12-1
12-2
12-3
12-4
12-5
12-6
12-7
15-1
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List of Tables
Table
A-1
A-2
Title
Technical Data
20
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1.1 Contents
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.4
Programmable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.6
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.7
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
1.7.1
VDD and VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.7.2
VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.7.3
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.7.3.1
Crystal Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.7.3.2
Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.7.3.3
External Clock Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.7.4
External Reset Pin (RESET) . . . . . . . . . . . . . . . . . . . . . . . .32
1.7.5
External Interrupt Request Pin (IRQ) . . . . . . . . . . . . . . . . . . 32
1.7.6
Input Capture Pin (TCAP) . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.7.7
Output Compare Pin (TCMP) . . . . . . . . . . . . . . . . . . . . . . . .33
1.7.8
Port A I/O Pins (PA7PA0). . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.7.9
Port B I/O Pins (PB7PB0). . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.7.10 Port C I/O Pins (PC7PC0) . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.7.11 Port D I/O Pins (PD7 and PD5PD0) . . . . . . . . . . . . . . . . . . 33
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Technical Data
General Description
21
General Description
1.2 Introduction
The MC68HC705C8A, an enhanced version of the MC68HC705C8, is a
member of the low-cost, high-performance M68HC05 Family of 8-bit
microcontroller units (MCU). The MC68HSC705C8A, introduced in
Appendix A. MC68HSC705C8A, is an enhanced, high-speed version of
the MC68HC705C8A. The M68HC05 Family is based on the
customer-specified integrated circuit (CSIC) design strategy. All MCUs
in the family use the M68HC05 central processor unit (CPU) and are
available with a variety of subsystems, memory sizes and types, and
package types.
1.3 Features
Features of the MC68HC705C8A include:
Clock monitor
Bootstrap capability
Technical Data
22
MC68HC705C8A Rev. 3
General Description
MOTOROLA
General Description
Programmable Options
NOTE:
A line over a signal name indicates an active low signal. For example,
RESET is active high and RESET is active low. Any reference to voltage,
current, or frequency specified in this document will refer to the nominal
values. The exact values and their tolerance or limits are specified in
Section 13. Electrical Specifications.
These options are programmable in the option register (see Figure 1-1):
Address:
$1FDF
Bit 7
RAM0
RAM1
SEC*
Read:
Bit 0
IRQ
Write:
Reset:
U = Unaffected
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
General Description
23
General Description
RAM0 Random-Access Memory Control Bit 0
1 = Maps 32 bytes of RAM into page zero starting at address
$0030. Addresses from $0020 to $002F are reserved. This bit
can be read or written at any time, allowing memory
configuration to be changed during program execution.
0 = Provides 48 bytes of PROM at location $0020$005F.
RAM1 Random-Access Memory Control Bit 1
1 = Maps 96 bytes of RAM into page one starting at address $0100.
This bit can be read or written at any time, allowing memory
configuration to be changed during program execution.
0 = Provides 96 bytes of PROM at location $0100.
SEC Security Bit
This bit is implemented as an erasable, programmable read-only
memory (EPROM) cell and is not affected by reset.
1 = Bootloader disabled; MCU operates only in single-chip mode
0 = Security off; bootloader can be enabled
IRQ Interrupt Request Pin Sensitivity Bit
IRQ is set only by reset, but can be cleared by software. This bit can
be written only once.
1 = IRQ pin is both negative edge- and level-sensitive.
0 = IRQ pin is negative edge-sensitive only.
Bits 5, 4, and 0 Not used; always read 0
Bit 2 Unaffected by reset; reads either 1 or 0
Technical Data
24
MC68HC705C8A Rev. 3
General Description
MOTOROLA
General Description
Block Diagram
PA0
PA1
PA2
PORT A
PROGRAM REGISTER
DATA DIRECTION A
VPP
EPROM PROGRAMMING
CONTROL
PA3
PA4
PA5
PA6
PA7
OPTION
REGISTER
PB1*
PB2*
PORT B
DATA DIRECTION B
PB0*
PB3*
PB4*
PB5*
PB6*
PB7*
RESET
ARITHMETIC
LOGIC UNIT
PC0
M68HC05 CPU
CPU REGISTERS
ACCUMULATOR
INDEX REGISTER
PC1
PC2
PORT C
CPU
CONTROL
DATA DIRECTION C
IRQ
PC3
PC4
PC5
PC6
STACK POINTER
PC7
PROGRAM COUNTER
CONDITION CODE REGISTER
PD7
RDI (PD0)
SCI
OSC1
OSCILLATOR
PORT D
OSC2
TDO (PD1)
INTERNAL
PROCESSOR
CLOCK
MISO (PD2)
MOSI (PD3)
SPI
SCK (PD4)
COP WATCHDOG
AND
CLOCK MONITOR
VDD
VSS
SS (PD5)
BAUD RATE
GENERATOR
POWER
16-BIT
CAPTURE/COMPARE
TIMER SYSTEM
TCMP
TCAP
Technical Data
General Description
25
General Description
1.6 Pin Assignments
The MC68HC705C8A is available in six packages:
The pin assignments for these packages are shown in Figure 1-3,
Figure 1-4, Figure 1-5, and Figure 1-6.
RESET
40
VDD
IRQ
39
OSC1
VPP
38
OSC2
PA7
37
TCAP
PA6
36
PD7
PA5
35
TCMP
PA4
34
PD5/SS
PA3
33
PD4/SCK
PA2
32
PD3/MOSI
PA1
10
31
PD2/MISO
PA0
11
30
PD1/TDO
PB0
12
29
PD0/RDI
PB1
13
28
PC0
PB2
14
27
PC1
PB3
15
26
PC2
PB4
16
25
PC3
PB5
17
24
PC4
PB6
18
23
PC5
PB7
19
22
PC6
VSS
20
21
PC7
MC68HC705C8A Rev. 3
General Description
MOTOROLA
PA6
PA7
VPP
NC
IRQ
RESET
VDD
OSC1
OSC2
TCAP
NC
44
43
42
41
40
28
PD7
TCMP
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TDO
PD0/RDI
PC0
PC1
PC2
PC3
25
PC6
27
24
PC7
PC4
23
NC
26
22
VSS
PC5
21
PB7
20
PB6
NC
18
PA1
PA0
PB0
PB1
PB2
PB3
PB4
37
36
35
34
33
32
31
30
29
10
11
12
13
14
15
16
17
19
PA3
PA2
39
38
7
8
9
PB5
PA5
PA4
General Description
Pin Assignments
PC3
PC2
PC1
PC0
PD0/RDI
PD1/TDO
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
TCMP
PC6
VDD
38
18
PC7
NC
39
17
VSS
NC
40
16
NC
RESET
41
15
PB7
IRQ
42
14
PB6
VPP
43
13
PB5
PB4
12
10 11
PB3
PA6
PA7
44
1
PB2
PC5
19
PB1
20
37
PB0
36
OSC1
PA0
OSC2
PA1
PC4
PA2
21
PA3
35
PA4
NC
TCAP
PA5
33 32 31 30 29 28 27 26 25 24 23
34
22
PD7
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
General Description
27
General Description
RESET
42
VDD
IRQ
41
OSC1
VPP
40
OSC2
PA7
39
TCAP
PA6
38
PD7
PA5
37
TCMP
PA4
36
PD5/SS
PA3
35
PD4/SCK
PA2
34
PD3/MOSI
PA1
10
33
PD2/MISO
PA0
11
32
PD1/TDO
PB0
12
31
PD0/RDI
PB1
13
30
PC0
PB2
14
29
PC1
PB3
15
28
PC2
NC
16
27
NC
PB4
17
26
PC3
PB5
18
25
PC4
PB6
19
24
PC5
PB7
20
23
PC6
VSS
21
22
PC7
Technical Data
28
MC68HC705C8A Rev. 3
General Description
MOTOROLA
General Description
Pin Functions
V+
VDD
+
MCU
C1
C2
VSS
1.7.2 VPP
This pin provides the programming voltage to the EPROM array. For
normal operation, VPP shuld be tied to VDD.
NOTE:
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
General Description
29
General Description
1.7.3 OSC1 and OSC2
The OSC1 and OSC2 pins are the control connections for the 2-pin
on-chip oscillator. The oscillator can be driven by:
NOTE:
Crystal resonator
Ceramic resonator
The frequency of the internal oscillator is fOSC. The MCU divides the
internal oscillator output by two to produce the internal clock with a
frequency of fOP.
NOTE:
OSC1
10 M
XTAL
2 MHz
22 pF
OSC2
22 pF
Use an AT-cut crystal and not a strip or tuning fork crystal. The MCU
might overdrive or have the incorrect characteristic impedance for a strip
or tuning fork crystal.
Technical Data
30
MCU
MC68HC705C8A Rev. 3
General Description
MOTOROLA
General Description
Pin Functions
MCU
OSC1
CERAMIC
RESONATOR
OSC2
MCU
OSC1
OSC2
CERAMIC
RESONATOR
NOTE:
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
General Description
31
General Description
1.7.3.3 External Clock Signal
OSC2
MCU
OSC1
EXTERNAL
CMOS CLOCK
NOTE:
The bus frequency (fOP) is one-half the external frequency (fOSC) while
the processor clock cycle is two times the fOSC period.
Technical Data
32
MC68HC705C8A Rev. 3
General Description
MOTOROLA
General Description
Pin Functions
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
General Description
33
General Description
Technical Data
34
MC68HC705C8A Rev. 3
General Description
MOTOROLA
Section 2. Memory
2.1 Contents
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.3
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.4
Input/Output (I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.5
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.6
EPROM/OTPROM (PROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.7
Bootloader ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.2 Introduction
This section describes the organization of the on-chip memory.
Technical Data
Memory
35
Memory
subroutine call to save the CPU state. The stack pointer decrements
during pushes and increments during pulls.
Figure 2-1 is a memory map of the MCU. Addresses $0000$001F,
shown in Figure 2-2, contain most of the control, status, and data
registers. Additional I/O registers have these addresses:
2.5 RAM
One of four selectable memory configurations is selected by the state of
the RAM1 and RAM0 bits in the option register located at $1FDF. Reset
or power-on reset (POR) clears these bits, automatically selecting the
first memory configuration as shown in Table 2-1. See 9.5.1 Option
Register.
Table 2-1. Memory Configurations
NOTE:
RAM0
RAM1
RAM Bytes
PROM Bytes
176
7744
208
7696
272
7648
304
7600
Technical Data
36
MC68HC705C8A Rev. 3
Memory
MOTOROLA
Memory
EPROM/OTPROM (PROM)
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Memory
37
Memory
$0000
$001F
$0020
$002F
$0030
$004F
$0050
I/O REGISTERS
32 BYTES
UNUSED
16 BYTES
USER PROM
48 BYTES
RAM
32 BYTES
RAM0 = 1(1)
$00BF
$00C0
RAM0 = 0(1)
RAM
176 BYTES
STACK
64 BYTES
$00FF
$0100
$015F
$0160
$1EFF
$1F00
$1FDE
$1FDF
$1FE0
USER PROM
96 BYTES
RAM
96 BYTES
RAM1 = 0(1)
RAM1 = 1(1)
USER PROM
7584 BYTES
BOOTLOADER ROM
240 BYTES
OPTION REGISTER
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
RESERVED
RESERVED
SPI INTERRUPT VECTOR (HIGH)
SPI INTERRUPT VECTOR (LOW)
SCI INTERRUPT VECTOR (HIGH)
SCI INTERRUPT VECTOR (LOW)
TIMER INTERRUPT VECTOR (HIGH)
TIMER INTERRUPT VECTOR (LOW)
EXTERNAL INTERRUPT VECTOR (HIGH)
EXTERNAL INTERRUPT VECTOR (LOW)
SOFTWARE INTERRUPT VECTOR (HIGH)
SOFTWARE INTERRUPT VECTOR (LOW)
RESET VECTOR (HIGH)
RESET VECTOR (LOW)
$1FF2
$1FF3
$1FF4
$1FF5
$1FF6
$1FF7
$1FF8
$1FF9
$1FFA
$1FFB
$1FFC
$1FFD
$1FFE
$1FFF
$1FF1
$1FF2
$1FFF
(1)
MC68HC705C8A Rev. 3
Memory
MOTOROLA
Memory
Bootloader ROM
Addr.
Register Name
Read:
Port A Data Register
(PORTA) Write:
See page 78.
Reset:
$0000
Read:
Port B Data Register
(PORTB) Write:
See page 81.
Reset:
$0001
Read:
Port C Data Register
(PORTC) Write:
See page 85.
Reset:
$0002
$0003
Read:
Port D Fixed Input Register
(PORTD) Write:
See page 88.
Reset:
$0004
$0005
$0006
Bit 7
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB2
PB1
PB0
PC2
PC1
PC0
MISO
TDO
RDI
Unaffected by reset
PB7
PB6
PC7
PC6
Unimplemented
$0009
Unimplemented
PC5
SS
PD7
PC4
PC3
SCK
MOSI
Unaffected by reset
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
Read:
Port C Data Direction
DDRC7 DDRC6
(DDRC) Write:
See page 86.
Reset:
0
0
$0008
PB3
Unaffected by reset
Read:
Port B Data Direction
DDRB7
Register (DDRB) Write:
See page 82.
Reset:
0
Unimplemented
PB4
Unaffected by reset
Read:
Port A Data Direction
DDRA7
Register (DDRA) Write:
See page 79.
Reset:
0
$0007
PB5
= Unimplemented
U = Unaffected
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Memory
39
Memory
Addr.
Register Name
Read:
SPI Control Register
(SPCR) Write:
See page 149.
Reset:
$000A
Read:
SPI Status Register
(SPSR) Write:
See page 151.
Reset:
$000B
Read:
SPI Data Register
(SPDR) Write:
See page 149.
Reset:
$000C
Read:
Baud Rate Register
(Baud) Write:
See page 136.
Reset:
$000D
$000E
$000F
Read:
SCI Control Register 1
(SCCR1) Write:
See page 130.
Reset:
Read:
SCI Control Register 2
(SCCR2) Write:
See page 131.
Reset:
Bit 0
SPIE
SPE
MSTR
CPOL
CPHA
SPR1
SPR0
SPIF
WCOL
MODF
Bit 7
Bit 6
Bit 3
BIt 2
Bit 1
Bit 0
Read:
SCI Data Register
(SCDR) Write:
See page 129.
Reset:
$0011
Read:
Timer Control Register
(TCR) Write:
See page 94.
Reset:
SCR2
SCR1
SCR0
Bit 5
Bit 4
Unaffected by reset
SCP1
SCP0
R8
T8
WAKE
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
TC
RDRF
IDLE
OR
NF
FE
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read: TDRE
SCI Status Register
(SCSR) Write:
See page 133.
Reset:
1
$0010
$0012
Bit 7
Bit 7
Unaffected by reset
ICIE
OCIE
TOIE
IEDG
OLVL
= Unimplemented
U = Unaffected
MC68HC705C8A Rev. 3
Memory
MOTOROLA
Memory
Bootloader ROM
Addr.
Register Name
$0014
$0015
$0017
Bit 0
ICF
OCF
TOF
Read: Bit 15
Input Capture Register
High (ICRH) Write:
See page 100.
Reset:
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Read:
Input Capture Register
Low (ICRL) Write:
See page 100.
Reset:
Bit 6
Bit 2
Bit 1
Bit 0
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Read:
Timer Status Register
(TSR) Write:
See page 96.
Reset:
$0013
$0016
Bit 7
Bit 7
$0018
$0019
$001A
$001B
Bit 5
Bit 4
Bit 3
Unaffected by reset
Unaffected by reset
Bit 7
Bit 14
Bit 13
Bit 12
Bit 11
Unaffected by reset
Bit 6
Bit 5
Bit 4
Bit 3
Unaffected by reset
Read: Bit 15
Timer Register High
(TRH) Write:
See page 97.
Reset:
Bit 14
Read:
Timer Register Low
(TRL) Write:
See page 97.
Reset:
Bit 6
Bit 7
Bit 13
Bit 12
Bit 11
Bit 4
Bit 3
Read: Bit 15
Alternate Timer Register
High (ATRH) Write:
See page 99.
Reset:
Bit 14
Read:
Alternate Timer Register
Low (ATRL) Write:
See page 99.
Reset:
Bit 6
Bit 7
Bit 13
Bit 12
Bit 11
Bit 4
Bit 3
U = Unaffected
Technical Data
Memory
41
Memory
Addr.
$001C
$001D
$001E
Register Name
Read:
EPROM Programming
Register (PROG) Write:
See page 109.
Reset:
Read:
Programmable COP Reset
Register (COPRST) Write:
See page 64.
Reset:
Read:
Programmable COP Control
Register (COPCR) Write:
See page 64.
Reset:
Bit 7
Bit 0
LAT
PGM
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
COPF
CME
PCOPE
CM1
CM0
IRQ
$001F
Unimplemented
$1FDF
Read:
Option Register
RAM0
(Option) Write:
See page 116.
Reset:
0
RAM1
SEC*
PBPU6
PBPU5
PBPU4
PBPU3
PBPU2
PBPU1
PBPU0/
COPC
$1FF0
$1FF1
Read:
Mask Option Register 1
PBPU7
(MOR1) Write:
See page 117.
Reset:
Unaffected by reset
Read:
Mask Option Register 2
(MOR2) Write:
See page 118.
Reset:
NCOPE
Unaffected by reset
= Unimplemented
U = Unaffected
Technical Data
42
MC68HC705C8A Rev. 3
Memory
MOTOROLA
3.1 Contents
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.2
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.4
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.4
3.2 Introduction
This section describes the central processor unit (CPU) registers.
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Central Processor Unit (CPU)
43
Bit 7
Bit 0
ACCUMULATOR (A)
Bit 7
Bit 0
INDEX REGISTER (X)
Bit 12 11
10
Bit 12 11
10
Bit 0
STACK POINTER (SP)
Bit 0
PROGRAM COUNTER (PC)
Bit 7
Bit 0
HALF-CARRY FLAG
INTERRUPT MASK
NEGATIVE FLAG
ZERO FLAG
CARRY/BORROW FLAG
Technical Data
44
MC68HC705C8A Rev. 3
Central Processor Unit (CPU)
MOTOROLA
3.3.1 Accumulator
The accumulator (A) shown in Figure 3-2 is a general-purpose 8-bit
register. The CPU uses the accumulator to hold operands and results of
arithmetic and non-arithmetic operations.
Bit 7
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Bit 7
Bit 0
Read:
Write:
Reset:
Unaffected by reset
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Central Processor Unit (CPU)
45
Read:
Bit 12
11
10
Bit 0
Write:
Reset:
= Unimplemented
11
10
Bit 0
Read:
Write:
Reset:
MC68HC705C8A Rev. 3
Central Processor Unit (CPU)
MOTOROLA
Read:
Bit 7
Bit 0
Write:
Reset:
= Unimplemented
U = Unaffected
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Central Processor Unit (CPU)
47
Technical Data
48
MC68HC705C8A Rev. 3
Central Processor Unit (CPU)
MOTOROLA
Section 4. Interrupts
4.1 Contents
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.3
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.3.1
Software Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.3.2
External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.3.3
Port B Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
4.3.4
Capture/Compare Timer Interrupts . . . . . . . . . . . . . . . . . . .55
4.3.5
SCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.3.6
SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.4
4.2 Introduction
This section describes how interrupts temporarily change the normal
processing sequence.
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Interrupts
49
Interrupts
4.3 Interrupt Sources
These sources can generate interrupts:
Port B pins
The IRQ pin, port B pins, SCI, and SPI can be masked (disabled) by
setting the I bit of the condition code register (CCR). The software
interrupt (SWI) instruction is non-maskable.
An interrupt temporarily changes the program sequence to process a
particular event. An interrupt does not stop the execution of the
instruction in progress but takes effect when the current instruction
completes its execution. Interrupt processing automatically saves the
central processor unit (CPU) registers on the stack and loads the
program counter with a user-defined vector address.
Technical Data
50
MC68HC705C8A Rev. 3
Interrupts
MOTOROLA
Interrupts
Interrupt Sources
IRQ latch
NOTE:
The internal interrupt latch is cleared in the first part of the interrupt
service routine. Therefore, a new external interrupt pulse could be
latched and serviced as soon as the I bit is cleared.
If the IRQ pin is not in use, connect it to the VDD pin.
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Interrupts
51
Interrupts
EXTERNAL
INTERRUPT
REQUEST
I BIT (CCR)
IRQ LATCH
INTERRUPT PIN
Q
POR
R
INTERNAL RESET (COP)
EXTERNAL RESET
EXTERNAL INTERRUPT BEING SERVICED
(VECTOR FETCH)
tILIL
tILIH
IRQ PIN
a. Edge-Sensitive Trigger Condition. The minimum pulse width (tILIH) is either 125 ns (fOP = 2.1 MHz)
or 250 ns (fOP = 1 MHz). The period tILIL should not be less than the number of tCYC cycles it takes to
execute the interrupt service routine plus 19 tCYC cycles.
IRQ1
NORMALLY
USED WITH
WIRED-OR
CONNECTION
tILIH
.
.
.
IRQn
IRQ
(INTERNAL)
b. Level-Sensitive Trigger Condition. If the interrupt line remains low after servicing an interrupt, then the
CPU continues to recognize an interrupt.
MC68HC705C8A Rev. 3
Interrupts
MOTOROLA
Interrupts
Interrupt Sources
The clear interrupt mask (CLI) instruction has cleared the I bit in
the CCR.
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Interrupts
53
Interrupts
VDD
PBPU7
FROM MOR1
READ $0005
WRITE $0005
RESET
WRITE $0001
DATA DIRECTION
REGISTER B
BIT DDRB7
PORT B DATA
REGISTER
BIT PB7
PB7
READ $0001
IRQ
FROM OPTION
REGISTER
VDD
D
FROM OTHER
PORT B PINS
EXTERNAL
INTERRUPT
REQUEST
Q
I BIT
FROM CCR
IRQ
RESET
EXTERNAL INTERRUPT VECTOR FETCH
Technical Data
54
MC68HC705C8A Rev. 3
Interrupts
MOTOROLA
Interrupts
Interrupt Sources
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Interrupts
55
Interrupts
SCI Receiver Input Idle Interrupt The receiver input idle bit
(IDLE) indicates that the SCI receiver input is not receiving data.
IDLE becomes set when 10 or 11 consecutive logic 1s appear on
the receiver input. IDLE generates an interrupt request if the idle
line interrupt enable bit (ILIE) is set also.
SPI Mode Fault Interrupt The mode fault bit (MODF) in the SPI
status register indicates an SPI mode error. MODF becomes set
when a logic 0 occurs on the PD5/SS pin while the master bit
(MSTR) in the SPI control register is set. MODF generates an
interrupt request if the SPIE bit is set also.
Technical Data
56
MC68HC705C8A Rev. 3
Interrupts
MOTOROLA
Interrupts
Interrupt Processing
Source
Reset
Power-on
logic
Local
Mask
Global
Mask
Priority
(1 = Highest)
Vector Address
None
None
$1FFE$1FFF
None
None
Same priority
as any
instruction
$1FFC$1FFD
None
I bit
$1FFA$1FFB
I bit
$1FF8$1FF9
I bit
$1FF6$1FF7
I bit
$1FF4$1FF5
RESET pin
Software
interrupt
(SWI)
External
interrupt
Timer
interrupts
User code
IRQ pin
Port B pins
ICF bit
ICIE bit
OCF bit
OCIE bit
TOF bit
TOIE bit
TDRE bit
TCIE bit
TC bit
SCI
interrupts
RDRF bit
RIE bit
OR bit
IDLE bit
SPI
interrupts
ILIE bit
SPIF bit
SPIE
MODF bit
Technical Data
Interrupts
57
Interrupts
ACCUMULATOR
INDEX REGISTER
STACKING
ORDER
$00FD
$00FE
$00FF (TOP OF STACK)
NOTE:
If more than one interrupt request is pending, the CPU fetches the vector
of the higher priority interrupt first. A higher priority interrupt does not
interrupt a lower priority interrupt service routine unless the lower priority
interrupt service routine clears the I bit. See Table 4-1 for a priority
listing.
Figure 4-5 shows the sequence of events caused by an interrupt.
Technical Data
58
MC68HC705C8A Rev. 3
Interrupts
MOTOROLA
Interrupts
Interrupt Processing
FROM
RESET
YES
I BIT IN
CCR REGISTER
SET?
NO
EXTERNAL
IRQ
INTERRUPT?
YES
NO
TIMER
INTERRUPT?
YES
NO
SCI
INTERRUPT?
YES
NO
SPI
INTERRUPT?
YES
NO
1. STACK PC, X, A, CCR
2. SET I BIT
3. LOAD PC WITH VECTOR
SWI: $1FFC$1FFD
IRQ: $1FFA$1FFB
TIMER: $1FF8$1FF9
SCI: $1FF6$1FF7
SPI: $1FF4$1FF5
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION?
YES
NO
RTI
INSTRUCTION?
YES
NO
EXECUTE INSTRUCTION
Technical Data
Interrupts
59
Interrupts
Technical Data
60
MC68HC705C8A Rev. 3
Interrupts
MOTOROLA
Section 5. Resets
5.1 Contents
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.3
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.3.1
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3.2
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3.3
Programmable and Non-Programmable
COP Watchdog Resets . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3.3.1
Programmable COP Watchdog Reset . . . . . . . . . . . . . . .63
5.3.3.2
Non-Programmable COP Watchdog . . . . . . . . . . . . . . . . 66
5.3.4
Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.2 Introduction
This section describes how resets initialize the microcontroller unit
(MCU).
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Resets
61
Resets
5.3.1 Power-On Reset (POR)
A positive transition on the VDD pin generates a power-on reset (POR).
The POR is strictly for the power-up condition and cannot be used to
detect drops in power supply voltage.
A 4064 tCYC (internal clock cycle) delay after the oscillator becomes
active allows the clock generator to stabilize. If the RESET pin is at
logic 0 at the end of 4064 tCYC, the MCU remains in the reset condition
until the signal on the RESET pin goes to logic 1.
MC68HC705C8A Rev. 3
Resets
MOTOROLA
Resets
Reset Sources
INTERNAL
CLOCK
(fOP)
2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2
213
CM0
CM1
215
217
RESET
219
2 2
2 2
2 2
221
PCOPE
COPRST
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Resets
63
Resets
Address:
$001D
Bit 7
Bit 0
Write:
Bit 7
Bit 0
Reset:
Read:
= Unimplemented
U = Unaffected
Address:
Read:
$001E
Bit 7
Bit 0
COPF
CME
PCOPE
CM1
CM0
Write:
Reset:
= Unimplemented
U = Unaffected
Technical Data
64
MC68HC705C8A Rev. 3
Resets
MOTOROLA
Resets
Reset Sources
NOTE:
NOTE:
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Resets
65
Resets
Table 5-1. Programmable COP Timeout Period Selection
Programmable COP Timeout Period
CM1:CM0
COP
Timeout Rate
00
fOP 215
16.38 ms
18.31 ms
32.77 ms
65.54 ms
01
fOP 217
65.54 ms
73.24 ms
131.07 ms
262.14 ms
10
fOP 219
262.14 ms
292.95 ms
524.29 ms
1.048 s
11
fOP 221
1.048 s
1.172 s
2.097 s
4.194 s
262,144
fOSC
NOTE:
Technical Data
66
MC68HC705C8A Rev. 3
Resets
MOTOROLA
Resets
Reset Sources
NOTE:
2 2 2 2 2 2 2 2 2 2 2 2
NCOPE
2 2 2 2 2
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Resets
67
Resets
The clock monitor is a useful backup to the COP watchdog system.
Because the watchdog timer requires a clock to function, it cannot
indicate a system clock failure. The clock monitor would detect such a
condition and force the MCU to a reset state. Clocks are not required for
the MCU to reach a reset condition. They are, however, required to bring
the MCU through the reset sequence and back to run condition.
Technical Data
68
MC68HC705C8A Rev. 3
Resets
MOTOROLA
6.1 Contents
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.3
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.3.1
SCI During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
6.3.2
SPI During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.3.3
Programmable COP Watchdog in Stop Mode . . . . . . . . . . . 71
6.3.4
Non-Programmable COP Watchdog in Stop Mode . . . . . . . 73
6.4
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.4.1
Programmable COP Watchdog in Wait Mode . . . . . . . . . . . 75
6.4.2
Non-Programmable COP Watchdog in Wait Mode . . . . . . . 75
6.5
Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.2 Introduction
This section describes the three low-power modes:
Stop mode
Wait mode
Data-retention mode
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Low-Power Modes
69
Low-Power Modes
STOP
WAIT
STOP OSCILLATOR
AND ALL CLOCKS
CLEAR I BIT
OSCILLATOR ACTIVE
TIMER, SCI, AND SPI
CLOCKS ACTIVE
CPU CLOCKS STOPPED
CLEAR I BIT
RESET
RESET
NO
NO
EXTERNAL
INTERRUPT
(IRQ)
NO
YES
YES
YES
EXTERNAL
INTERRUPT
(IRQ)
NO
YES
INTERNAL TIMER
INTERRUPT
YES
TURN ON OSCILLATOR
WAIT FOR TIME
DELAY TO STABILIZE
NO
RESTART CPU CLOCK
YES
INTERNAL SCI
INTERRUPT
NO
YES
INTERNAL SPI
INTERRUPT
NO
Technical Data
70
MC68HC705C8A Rev. 3
Low-Power Modes
MOTOROLA
Low-Power Modes
Stop Mode
NOTE:
Although a slave SPI in stop mode can exchange data with a master SPI,
the status bits of a slave SPI are inactive in stop mode.
Technical Data
Low-Power Modes
71
Low-Power Modes
NOTE:
If the clock monitor is enabled (CME = 1), the STOP instruction causes
the clock monitor to time out and reset the MCU.
STOP
EXTERNAL
RESET?
YES
NO
NO
EXTERNAL
INTERRUPT?
YES
YES
NO
END OF
STABILIZATION
DELAY?
YES
NO
TURN ON INTERNAL CLOCK
Technical Data
72
MC68HC705C8A Rev. 3
Low-Power Modes
MOTOROLA
Low-Power Modes
Wait Mode
If the RESET pin brings the MCU out of stop mode, the COP watchdog
begins counting immediately. The reset function clears the COP counter
again after the 4064-tCYC clock stabilization delay.
If the IRQ pin brings the MCU out of stop mode, the COP watchdog
begins counting immediately. The IRQ function does not clear the
COP counter again after the 4064-tCYC clock stabilization delay. See
Figure 6-3.
NOTE:
If the clock monitor is enabled (CME = 1), the STOP instruction causes
it to time out and reset the MCU.
Stops the CPU clock, but allows the internal clock to drive the
capture/compare timer, SCI, and SPI
The WAIT instruction does not affect any other registers or I/O lines. The
capture/compare timer, SCI, and SPI can be enabled to allow a periodic
exit from wait mode.
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Low-Power Modes
73
Low-Power Modes
STOP
EXTERNAL
RESET?
YES
NO
NO
EXTERNAL
INTERRUPT?
YES
END OF
STABILIZATION
DELAY?
YES
NO
END OF
STABILIZATION
DELAY?
YES
NO
CLEAR COP COUNTER
TURN ON INTERNAL CLOCK
Technical Data
74
MC68HC705C8A Rev. 3
Low-Power Modes
MOTOROLA
Low-Power Modes
Data-Retention Mode
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Low-Power Modes
75
Low-Power Modes
Technical Data
76
MC68HC705C8A Rev. 3
Low-Power Modes
MOTOROLA
7.1 Contents
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
7.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7.3.1
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7.3.2
Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.3.3
Port A Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.4.1
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.4.2
Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.4.3
Port B Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.5
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.5.1
Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.5.2
Data Direction Register C. . . . . . . . . . . . . . . . . . . . . . . . . . . 86
7.5.3
Port C Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.6
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
7.2 Introduction
This section describes the programming of ports A, B, C, and D.
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Parallel Input/Output (I/O)
77
$0000
Bit 7
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Read:
Write:
Reset:
Unaffected by reset
Technical Data
78
MC68HC705C8A Rev. 3
Parallel Input/Output (I/O)
MOTOROLA
$0004
Bit 7
Bit 0
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
Read:
Write:
Reset:
NOTE:
Avoid glitches on port A pins by writing to the port A data register before
changing DDRA bits from logic 0 to logic 1.
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Parallel Input/Output (I/O)
79
READ $0004
WRITE $0004
DATA DIRECTION
REGISTER A
BIT DDRAx
RESET
PORT A DATA
REGISTER
BIT PAx
WRITE $0000
PAx
READ $0000
Accesses to PORTA
Read
Write
Input, Hi-Z(1)
DDRA7DDRA0
Pin
PA7PA0(2)
Output
DDRA7DDRA0
PA7PA0
PA7PA0
NOTE:
To avoid excessive current draw, tie all unused input pins to VDD or VSS,
or change I/O pins to outputs by writing to DDRA in user code as early
as possible.
Technical Data
80
MC68HC705C8A Rev. 3
Parallel Input/Output (I/O)
MOTOROLA
7.4 Port B
Port B is an 8-bit, general-purpose, bidirectional I/O port. Port B pins can
also be configured to function as external interrupts. The port B pullup
devices are enabled in mask option register 1 (MOR1). See 9.5.2 Mask
Option Register 1 and 4.3.3 Port B Interrupts.
$0001
Bit 7
Bit 0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Read:
Write:
Reset:
Unaffected by reset
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Parallel Input/Output (I/O)
81
$0005
Bit 7
Bit 0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
Read:
Write:
Reset:
NOTE:
Avoid glitches on port B pins by writing to the port B data register before
changing DDRB bits from logic 0 to logic 1.
Technical Data
82
MC68HC705C8A Rev. 3
Parallel Input/Output (I/O)
MOTOROLA
PBPU7
FROM MOR1
READ $0005
WRITE $0005
RESET
WRITE $0001
DATA DIRECTION
REGISTER B
BIT DDRB7
PORT B DATA
REGISTER
BIT PB7
PB7
READ $0001
IRQ
FROM OPTION
REGISTER
VDD
D
FROM OTHER
PORT B PINS
EXTERNAL
INTERRUPT
REQUEST
IRQ
LATCH
C
Q
R
I BIT
FROM CCR
IRQ
RESET
EXTERNAL INTERRUPT VECTOR FETCH
Technical Data
Parallel Input/Output (I/O)
83
Accesses to PORTB
Read
Write
Input, Hi-Z(1)
DDRB7DDRB0
Pin
PB7PB0(2)
Output
DDRB7DDRB0
PB7PB0
PB7PB0
NOTE:
To avoid excessive current draw, tie all unused input pins to VDD or VSS,
or for I/O pins change to outputs by writing to DDRB in user code as early
as possible.
Technical Data
84
MC68HC705C8A Rev. 3
Parallel Input/Output (I/O)
MOTOROLA
7.5 Port C
Port C is an 8-bit, general-purpose, bidirectional I/O port. PC7 has a high
current sink and source capability.
$0002
Bit 7
Bit 0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Read:
Write:
Reset:
Unaffected by reset
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Parallel Input/Output (I/O)
85
$0006
Bit 7
Bit 0
DDRC7
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
Read:
Write:
Reset:
NOTE:
Avoid glitches on port C pins by writing to the port C data register before
changing DDRC bits from logic 0 to logic 1.
Technical Data
86
MC68HC705C8A Rev. 3
Parallel Input/Output (I/O)
MOTOROLA
READ $0006
WRITE $0006
DATA DIRECTION
REGISTER C
BIT DDRCx
RESET
PORT C DATA
REGISTER
BIT PCx
WRITE $0002
PCx
READ $0002
Accesses to PORTC
Read
Write
Input, Hi-Z(1)
DDRC7DDRC0
Pin
PC7PC0(2)
Output
DDRC7DDRC0
PC7PC0
PC7PC0
NOTE:
To avoid excessive current draw, tie all unused input pins to VDD or VSS
or change I/O pins to outputs by writing to DDRC in user code as early
as possible.
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Parallel Input/Output (I/O)
87
Address:
$0003
Bit 7
Read:
PD7
Bit 0
SS
SCK
MOSI
MISO
TDO
RDI
Write:
Reset:
Unaffected by reset
= Unimplemented
Technical Data
88
MC68HC705C8A Rev. 3
Parallel Input/Output (I/O)
MOTOROLA
8.1 Contents
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
8.3
Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
8.3.1
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
8.3.2
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
8.4
Timer I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
8.4.1
Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
8.4.2
Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8.4.3
Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
8.4.4
Alternate Timer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 98
8.4.5
Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 100
8.4.6
Output Compare Registers. . . . . . . . . . . . . . . . . . . . . . . . . 101
8.2 Introduction
This section describes the operation of the 16-bit capture/compare timer.
Figure 8-1 shows the structure of the timer module. Figure 8-2 is a
summary of the timer input/output (I/O) registers.
Technical Data
Capture/Compare Timer
89
Capture/Compare Timer
TCAP
EDGE
SELECT/
DETECT
LOGIC
ICRH ($0014)
ICRL ($0015)
TRH ($0018)
TRL ($0019)
16-BIT COUNTER
OVERFLOW
ATRH ($001A)
16-BIT COMPARATOR
OCRH ($0016)
ATRL ($001B)
TCMP
OCRL ($0017)
$0012
TOF
OCF
ICF
OLVL
IEDG
TOIE
OCIE
ICIE
TIMER
INTERRUPT
REQUEST
$0013
Technical Data
90
MC68HC705C8A Rev. 3
Capture/Compare Timer
MOTOROLA
Capture/Compare Timer
Timer Operation
Addr.
Register Name
$0012
Read:
Timer Control Register
(TCR) Write:
See page 94.
Reset:
$0014
$0015
$0017
Bit 0
ICIE
OCIE
TOIE
IEDG
OLVL
ICF
OCF
TOF
Read: Bit 15
Input Capture Register
High (ICRH) Write:
See page 100.
Reset:
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Read:
Input Capture Register
Low (ICRL) Write:
See page 100.
Reset:
Bit 6
Bit 2
Bit 1
Bit 0
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Read:
Timer Status Register
(TSR) Write:
See page 96.
Reset:
$0013
$0016
Bit 7
Bit 7
$0018
$0019
$001A
$001B
Bit 5
Bit 4
Bit 3
Unaffected by reset
Unaffected by reset
Bit 7
Bit 14
Bit 13
Bit 12
Bit 11
Unaffected by reset
Bit 6
Bit 5
Bit 4
Bit 3
Unaffected by reset
Read: Bit 15
Timer Register High
(TRH) Write:
See page 97.
Reset:
Bit 14
Read:
Timer Register Low
(TRL) Write:
See page 97.
Reset:
Bit 6
Bit 7
Bit 13
Bit 12
Bit 11
Bit 4
Bit 3
Read: Bit 15
Alternate Timer Register
High (ATRH) Write:
See page 99.
Reset:
Bit 14
Read:
Alternate Timer Register
Low (ATRL) Write:
See page 99.
Reset:
Bit 6
Bit 7
Bit 13
Bit 12
Bit 11
Bit 4
Bit 3
U = Unaffected
Technical Data
Capture/Compare Timer
91
Capture/Compare Timer
Because of the 16-bit timer architecture, the I/O registers for the input
capture and output compare functions are pairs of 8-bit registers.
Because the counter is 16 bits long and preceded by a fixed
divide-by-four prescaler, the counter rolls over every 262,144 internal
clock cycles. Timer resolution with a 4-MHz crystal is 2 s.
15
$0018
TCAP
EDGE
SELECT/DETECT
LOGIC
15
LATCH
$0019
$0014
$0015
TOF
OCF
ICF
OLVL
TOIE
OCIE
$0012
$0013
IEDG
ICIE
TIMER
INTERRUPT
REQUEST
MC68HC705C8A Rev. 3
Capture/Compare Timer
MOTOROLA
Capture/Compare Timer
Timer Operation
15
0
COUNTER LOW BYTE
PIN
CONTROL
LOGIC
16-BIT COMPARATOR
15
TCMP
$0016
$0017
TOF
OCF
ICF
TOIE
OCIE
ICIE
TIMER
INTERRUPT
REQUEST
$0012
$0013
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Capture/Compare Timer
93
Capture/Compare Timer
8.4 Timer I/O Registers
These registers control and monitor the timer operation:
Address:
$0012
Bit 7
Bit 0
ICIE
OCIE
TOIE
IEDG
OLVL
Read:
Write:
Reset:
U = Unaffected
Technical Data
94
MC68HC705C8A Rev. 3
Capture/Compare Timer
MOTOROLA
Capture/Compare Timer
Timer I/O Registers
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Capture/Compare Timer
95
Capture/Compare Timer
8.4.2 Timer Status Register
The timer status register (TSR) is a read-only register shown in
Figure 8-6 contains flags for these events:
Address:
Read:
$0013
Bit 7
Bit 0
ICF
OCF
TOF
Write:
Reset:
= Unimplemented
U = Unaffected
Technical Data
96
MC68HC705C8A Rev. 3
Capture/Compare Timer
MOTOROLA
Capture/Compare Timer
Timer I/O Registers
Bit 0
Bit 11
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Write:
Reset:
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Capture/Compare Timer
97
Capture/Compare Timer
Reading TRH returns the current value of the high byte of the counter
and causes the low byte to be latched into a buffer, as shown in
Figure 8-8. The buffer value remains fixed even if the high byte is read
more than once. Reading TRL reads the transparent low byte buffer and
completes the read sequence of the timer registers.
7
LATCH
15
$0018
8
TIMER REGISTER HIGH
0
LOW BYTE BUFFER
0
TIMER REGISTER LOW
$0019
READ TRH
NOTE:
Technical Data
98
MC68HC705C8A Rev. 3
Capture/Compare Timer
MOTOROLA
Capture/Compare Timer
Timer I/O Registers
Bit 7
Bit 0
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Write:
Reset:
7
LATCH
15
$001A
8
ALTERNATE TIMER REGISTER HIGH
0
LOW BYTE BUFFER
0
ALTERNATE TIMER REGISTER LOW
$001B
READ ATRH
NOTE:
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Capture/Compare Timer
99
Capture/Compare Timer
8.4.5 Input Capture Registers
When a selected edge occurs on the TCAP pin, the current high and low
bytes of the 16-bit counter are latched into the read-only input capture
registers (ICRH and ICRL) shown in Figure 8-11. Reading ICRH before
reading ICRL inhibits further captures until ICRL is read. Reading ICRL
after reading the timer status register clears the input capture flag (ICF).
Writing to the input capture registers has no effect.
Bit 7
Bit 0
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Write:
Reset:
Unaffected by reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Write:
Reset:
Unaffected by reset
= Unimplemented
NOTE:
Technical Data
100
MC68HC705C8A Rev. 3
Capture/Compare Timer
MOTOROLA
Capture/Compare Timer
Timer I/O Registers
Bit 0
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Bit 14
Bit 13
Bit 12
Bit 11
Write:
Reset:
Unaffected by reset
Bit 6
Bit 5
Bit 4
Bit 3
Write:
Reset:
Unaffected by reset
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Capture/Compare Timer
101
Capture/Compare Timer
Technical Data
102
MC68HC705C8A Rev. 3
Capture/Compare Timer
MOTOROLA
9.1 Contents
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
9.3
EPROM/OTPROM (PROM) Programming . . . . . . . . . . . . . . . 104
9.3.1
Program Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
9.3.2
Preprogramming Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
9.4
PROM Programming Routines . . . . . . . . . . . . . . . . . . . . . . . . 111
9.4.1
Program and Verify PROM. . . . . . . . . . . . . . . . . . . . . . . . . 111
9.4.2
Verify PROM Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
9.4.3
Secure PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
9.4.4
Secure PROM and Verify . . . . . . . . . . . . . . . . . . . . . . . . . . 113
9.4.5
Secure PROM and Dump. . . . . . . . . . . . . . . . . . . . . . . . . . 113
9.4.6
Load Program into RAM and Execute . . . . . . . . . . . . . . . . 114
9.4.7
Execute Program in RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 115
9.4.8
Dump PROM Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . .115
9.5
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
9.5.1
Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
9.5.2
Mask Option Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
9.5.3
Mask Option Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9.6
9.2 Introduction
This section describes erasable, programmable read-only
memory/one-time programmable read-only memory (EPROM/OTPROM
(PROM)) programming.
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
EPROM/OTPROM (PROM)
103
EPROM/OTPROM (PROM)
9.3 EPROM/OTPROM (PROM) Programming
The internal PROM can be programmed efficiently using the Motorola
MC68HC05PGMR-2 programmer board, which can be purchased from
a Motorola-authorized distributor. The user can program the
microcontroller unit (MCU) using this printed circuit board (PCB) in
conjunction with an EPROM device already programmed with user code.
Only standalone programming is discussed in this section. For more
information concerning the MC68HC05PGMR and its usages, contact a
local Motorola representative for a copy of the MC68HC05PGMR
Programmer Board Users Manual #2, Motorola document number
MC68HC05PGMR2/D1.
Refer to Figure 9-1 for an EPROM programming flowchart. Figure 9-2
provides a schematic of the MC68HC05PGMR PCB with the reference
designators defined in Table 9-1.
Device
Type
Ground
+5 V
+12 V
12 V
VPP
U1
2764
14, 20
1, 26, 27, 28
8 K x 8-bit EPROM
U2
MCU
20
40
U3
MCU
22
44
U4
MC145406
16
Driver/receiver
VR1
NMA0512S
2.5
DC-DC converter
Technical Data
104
Notes
MC68HC705C8A Rev. 3
EPROM/OTPROM (PROM)
MOTOROLA
EPROM/OTPROM (PROM)
EPROM/OTPROM (PROM) Programming
START
APPLY VPP
NTRYS = 0
START AT BEGINNING
OF MEMORY
LAT = 1
PGM = 1
WAIT 1 ms
PGM = 0
LAT = 0
YES
WRITE
ADDITIONAL
BYTE
NO
NTRYS = NTRYS + 1
NO
NTRYS = 2
YES
VPP OFF
END
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
EPROM/OTPROM (PROM)
105
EPROM/OTPROM (PROM)
VR1 NMA0512S
DC-DC CONVERTER
(OPTIONAL)
S1
OFF
A
+5 V
ON
P1
+5 V
+12 V
12 V
+V
6
OFF
1
VCC
5
0V
V
4
GND
2
GND
+ C1
100 F
40
VDD
+12 V
ON
VPP
R15
10 K
39
B
OSC1
12 V
3
D1
1N4001
38
C
OSC2
VPP
VPP
1
RESET
+5 V
16
RXD
IRQ
37
P3
3
D
2
14
TCAP
30
PD1
36
PD1
PD7
35
2
TXD
15
29
PD0
+12 V
U1
2764
A0
A1
+5 V
12 V
VPP
A3
NC
A4
27
PGM
A5
VCC
A6
28
CTS
5
C5
0.1 F
DSR
6
(A0)
PA0
PD5
11
(A1)
PA1
PD4
10
(A2)
PA2
PD3
PA2
(A3)
PA3
(A4)
PA4
(A5)
PA5
(A6)
PA6
(A7)
PA7
PD2
PA6
PC5
20
GND
1
(A8)
25
(A9)
24
(A10)
21
(A11)
23
(A12)
PB0
12
(D1)
PB1
D3
A9
A10
13
(D2)
PB2
14
15
(D3)
PB3
15
16
(D4)
PB4
16
17
(D5)
PB5
17
A12
D6
OE
D7
18
(D6)
PB6
18
PC1
PB2
PC2
19
(D7)
PB7
19
28
(A8)
27
(A9)
26
(A10)
25
(A11)
24
(A12)
PC3
PC4
PB5
PB6
GND
Notes:
1. The asterisk (*) denotes option T
command only.
2. Unless otherwise specified, resistors are in ohms,
5% 1/4 W; capacitors are in F; voltages are dc.
PB1
PB4
D5
22
PC0
PB3
D4
A11
PB0
13
D2
M
N
PC6
12
D1
A8
GND
7
(D0)
D0
CE
23
22
PA7
11
20
DTR
U2
PA4 40-PIN DIP
SOCKET
PA5
DCD
8
K
31
PA3
A7
J
32
PA1
8
I
33
PA0
A2
1
26
34
PD0
10
U4
MC145406
8
1
TCMP
14
21
PC7
PB7
VSS
20
P
Q
(ENABLE)
R
S
MC68HC705C8A Rev. 3
EPROM/OTPROM (PROM)
MOTOROLA
EPROM/OTPROM (PROM)
EPROM/OTPROM (PROM) Programming
R3 10 K
R2
J1
3 2 1
+5 V
NC
+12 V
NC
NC
NC
NC
2.7 K
C
R5
C2
1.0 F
+5 V
10 M
Y1
C4
22 pF
NC
10 K
R1
S2
3
38
39
40
OUT
RESET
R13
10 K
R4
10 K
+5 V
C3
22 pF
2.0 MHz
IRQ
+5 V
P2
2
E
F
S3
S4
S5
S6
H
PD5
34
PD4
33
PD3
K
+5 V
+5 V
R10*
470
1 2
VERF
R9
10 K
DS2*
31
36
R12
10 K
J2
TCAP
+5 V
TCMP
PB0
(VERF)
(PROG)
NC
PROG
DS1*
(A5)
(A4)
(A3)
(A2)
(A1)
(A0)
R11*
470
+5 V
14
15
16
17
PA5
PA4
PA3
PA2
PA1
PA0
PB0
PB1
PB2
PB3
PB4
PD7
TCMP
PD5
PD4
PD3
PD2
PD1
PD0
PC0
PC1
PC2
U3
44-LEAD PLCC
SOCKET
PB1
PB2
PB3
PB4
PB5
C6
0.1 F
39
38
37
36
35
34
33
32
31
30
29
PD5
PD4
PD3
PD2
PD1
PD0
(A8)
(A9)
(A10)
(D5)
(D6)
(D7)
18
19
20
21
22
23
24
(PROG) 25
(VERF) 26
(A12) 27
(A11) 28
NC
PB5
PB6
PB7
VSS
NC
PC7
PC6
PC5
(D0)
(D1)
(D2)
(D3)
(D4)
7
8
9
10
11
12
13
NC
PC4
PC3
R6
10 K
6 (A6)
PA6
5 (A7)
PA7
VPP 4
3
NC
2
IRQ
1
RESET
VDD 44
43
OSC1
42
OSC2
41
TCAP
40
NC
R7
10 K
R8
10 K
32
PD2
PD7
NC
NC
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PC0
PC1
PC2
PC3
PC4
PD1
PD0
PC5
Q
R
PC6
PC7
VSS
37
35
12
13
14
15
16
17
18
19
11
10
9
8
7
6
5
4
28
27
26
25
24
30
29
23
22
21
20
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
EPROM/OTPROM (PROM)
107
EPROM/OTPROM (PROM)
To program the PROM MCU, the MCU is installed in the PCB, along with
an EPROM device programmed with user code; the MCU is then
subjected to a series of routines. The routines necessary to program,
verify, and secure the PROM MCU are:
The user first configures the MCU for the bootstrap mode of operations
by installing a fabricated jumper across pins 1 and 2 of the boards mode
select header, J1. Next, the boards mode switches (S3, S4, S5, and S6)
are set to determine the routine to be executed after the next reset, as
shown in Table 9-2.
Table 9-2. PROM Programming Routines
Routine
S3
S4
S5
S6
Off
Off
Off
Off
Off
Off
On
Off
On
Off
On
Off
On
On
On
Off
Off
On
Off
Off
Off
Off
Off
On
Off
On
On
Off
Technical Data
108
MC68HC705C8A Rev. 3
EPROM/OTPROM (PROM)
MOTOROLA
EPROM/OTPROM (PROM)
EPROM/OTPROM (PROM) Programming
$001C
Bit 7
Bit 0
LAT
PGM
Read:
Write:
Reset:
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
EPROM/OTPROM (PROM)
109
EPROM/OTPROM (PROM)
9.3.2 Preprogramming Steps
Before programming the PROM using an MC68HC05PGMR PCB in
standalone mode, the user should ensure that:
NOTE:
If the VPP level at the MCU exceeds +16 Vdc, then the MC68HC705C8A
MCU device will suffer permanent damage.
Once those conditions are met, the user should take these steps before
beginning programming:
1. Remove the VPP power source.
2. Set switch 1 in the OFF position (removes VDD).
3. Place the programmed EPROM in socket U1.
4. Insert the erased PROM MCU device to be programmed in the
proper socket:
MC68HC705C8S or MC68HC705C8P in socket U2 (40-pin
dual in-line package (DIP)) or
MC68HC705C8FN in socket U3 (44-pin plastic leaded chip
carrier (PLCC)) with the device notch at the upper right corner
of the socket.
5. Set switch S2 in the RESET position.
NOTE:
Technical Data
110
MC68HC705C8A Rev. 3
EPROM/OTPROM (PROM)
MOTOROLA
EPROM/OTPROM (PROM)
PROM Programming Routines
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
EPROM/OTPROM (PROM)
111
EPROM/OTPROM (PROM)
9.4.2 Verify PROM Contents
The verify PROM contents routine is normally run automatically after the
PROM is programmed. Direct entry to this routine causes the PROM
contents of the MCU to be compared to the contents of the external
memory locations of the EPROM at the same addresses.
To invoke the verify PROM contents routine of the MCU, take these
steps:
1. Set switch 1 in the ON position (restores VDD).
2. Connect VPP to VDD.
3. Set switches S3, S4, and S6 in the OFF position.
4. Set S5 in the ON position.
5. Set switch 2 in the OUT position (routine is activated).
The red LED is not illuminated during this routine, since no
programming takes place. If verification fails, the routine halts with
the failing address in the external memory bus. When the green
LED is illuminated, verification is completed successfully and the
routine is finished.
6. Set switch 2 in the RESET position.
At this point, if another routine is to be performed on the MCU being
programmed, the user can set switches S3, S4, S5, and S6 to the
positions necessary to select the next routine and move switch S2 to the
OUT position to start the routine. If no other routine is to be performed,
remove VDD from the board and remove the MCU from the programming
socket.
Technical Data
112
MC68HC705C8A Rev. 3
EPROM/OTPROM (PROM)
MOTOROLA
EPROM/OTPROM (PROM)
PROM Programming Routines
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
EPROM/OTPROM (PROM)
113
EPROM/OTPROM (PROM)
No LED is illuminated during this routine. Further, the end of the routine
does not mean that the SEC bit was verified. To ensure that security is
properly enabled, attempt to perform another verify routine. If the green
LED does not light, the PROM has been secured properly.
Technical Data
114
MC68HC705C8A Rev. 3
EPROM/OTPROM (PROM)
MOTOROLA
EPROM/OTPROM (PROM)
PROM Programming Routines
NOTE:
Technical Data
EPROM/OTPROM (PROM)
115
EPROM/OTPROM (PROM)
9.5 Control Registers
This subsection describes the three registers that control memory
configuration, PROM security, and IRQ edge or level sensitivity; port B
pullups; and non-programmable COP enable/disable.
$1FDF
Bit 7
RAM0
RAM1
SEC*
Read:
Bit 0
IRQ
Write:
Reset:
U = Unaffected
Technical Data
116
MC68HC705C8A Rev. 3
EPROM/OTPROM (PROM)
MOTOROLA
EPROM/OTPROM (PROM)
Control Registers
$1FF0
Bit 7
Bit 0
PBPU7
PBPU6
PBPU5
PBPU4
PBPU3
PBPU2
PBPU1
PBPU0/
COPC
Read:
Write:
Reset:
Erased:
Unaffected by reset
0
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
EPROM/OTPROM (PROM)
117
EPROM/OTPROM (PROM)
NOTE:
$1FF1
Bit 7
Bit 0
Read:
NCOPE
Write:
Reset:
Erased:
Unaffected by reset
0
= Unimplemented
Technical Data
118
MC68HC705C8A Rev. 3
EPROM/OTPROM (PROM)
MOTOROLA
EPROM/OTPROM (PROM)
EPROM Erasing
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
EPROM/OTPROM (PROM)
119
EPROM/OTPROM (PROM)
Technical Data
120
MC68HC705C8A Rev. 3
EPROM/OTPROM (PROM)
MOTOROLA
10.1 Contents
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
10.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
10.4
10.2 Introduction
The serial communications interface (SCI) module allows high-speed
asynchronous communication with peripheral devices and other
microcontroller units (MCUs).
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Serial Communications Interface (SCI)
121
Full-duplex operation
Technical Data
122
MC68HC705C8A Rev. 3
Serial Communications Interface (SCI)
MOTOROLA
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
STOP
BIT
BIT 6
BIT 7
BIT 8
NEXT
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
STOP
BIT
NEXT
START
BIT
10.5.1 Transmitter
Figure 10-2 shows the structure of the SCI transmitter. Figure 10-3 is a
summary of the SCI transmitter input/output (I/O) registers.
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Serial Communications Interface (SCI)
123
SCDR ($0011)
1X
BAUD RATE
CLOCK
SCSR ($0010)
TDRE
TC
RDRF
IDLE
OR
NF
FE
M
WAKE
R8
T8
TRANSMITTER
CONTROL LOGIC
SCCR1 ($000E)
PD1/
TDO
SHIFT ENABLE
H 8 7 6 5 4 3 2 1 0 L
TDRE
TIE
TC
TCIE
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
SCI RECEIVE
REQUESTS
SCCR2 ($000F)
SCI INTERRUPT
REQUEST
Technical Data
124
MC68HC705C8A Rev. 3
Serial Communications Interface (SCI)
MOTOROLA
Addr.
$000D
$000E
$000F
$0010
$0011
Register Name
Bit 7
Read:
Baud Rate Register
(Baud) Write:
See page 136.
Reset:
Read:
SCI Control Register 1
(SCCR1) Write:
See page 130.
Reset:
Read:
SCI Control Register 2
(SCCR2) Write:
See page 131.
Reset:
SCP1
SCP0
Bit 0
SCR2
SCR1
SCR0
R8
T8
WAKE
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
TC
RDRF
IDLE
OR
NF
FE
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read: TDRE
SCI Status Register
(SCSR) Write:
See page 133.
Reset:
1
Read:
SCI Data Register
(SCDR) Write:
See page 129.
Reset:
Bit 7
Unaffected by reset
= Unimplemented
U = Unaffected
Technical Data
Serial Communications Interface (SCI)
125
Technical Data
126
MC68HC705C8A Rev. 3
Serial Communications Interface (SCI)
MOTOROLA
10.5.2 Receiver
16X
BAUD RATE
CLOCK
PD0/
RDI
PIN BUFFER
AND CONTROL
STOP
16
DATA
RECOVERY
8 7 6 5 4 3 2 1 0
DISABLE
DRIVER
SCCR1 ($000E)
IDLE
OR
NF
FE
TDRE
TC
RDRF
M
WAKE
T8
WAKEUP
LOGIC
R8
START
SCSR ($0010)
SCDR ($0011)
RDRF
IDLE
SCI TRANSMIT
REQUESTS
ILIE
OR
TCIE
RIE
ILIE
TE
RE
RWU
SBK
TIE
RIE
RIE
SCCR2 ($000F)
SCI INTERRUPT
REQUEST
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Serial Communications Interface (SCI)
127
Technical Data
128
MC68HC705C8A Rev. 3
Serial Communications Interface (SCI)
MOTOROLA
Framing Errors If the data recovery logic does not detect a logic
1 where the stop bit should be in an incoming character, it sets the
framing error (FE) bit in the SCSR. The FE bit is set at the same
time that the RDRF bit is set.
$0011
Bit 7
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Technical Data
Serial Communications Interface (SCI)
129
Stores ninth SCI data bit received and ninth SCI data bit
transmitted
Address:
$000E
Bit 7
R8
U
T8
WAKE
Bit 0
Read:
Write:
Reset:
= Unimplemented
U = Unaffected
Technical Data
130
MC68HC705C8A Rev. 3
Serial Communications Interface (SCI)
MOTOROLA
Address:
$000F
Bit 7
Bit 0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
Read:
Write:
Reset:
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Serial Communications Interface (SCI)
131
Technical Data
132
MC68HC705C8A Rev. 3
Serial Communications Interface (SCI)
MOTOROLA
idle input or an address mark brings the receiver out of the standby
state. Reset clears the RWU bit.
1 = Standby state
0 = Normal operation
SBK Send Break Bit
Setting this read/write bit continuously transmits break codes in the
form of 10-bit or 11-bit groups of logic 0s. Clearing the SBK bit stops
the break codes and transmits a logic 1 as a start bit. Reset clears the
SBK bit.
1 = Break codes being transmitted
0 = No break codes being transmitted
Transmission complete
Receiver overrun
Noisy data
Framing error
Address:
Read:
$0010
Bit 7
TDRE
TC
RDRF
IDLE
OR
NF
FE
Bit 0
Write:
Reset:
= Unimplemented
U = Unaffected
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Serial Communications Interface (SCI)
133
Technical Data
134
MC68HC705C8A Rev. 3
Serial Communications Interface (SCI)
MOTOROLA
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Serial Communications Interface (SCI)
135
$000D
Bit 7
SCP1
SCP0
Bit 0
SCR2
SCR1
SCR0
Read:
Write:
Reset:
= Unimplemented
U
U = Unaffected
00
Internal clock
01
Internal clock
10
Internal clock
11
Internal clock
13
Technical Data
136
MC68HC705C8A Rev. 3
Serial Communications Interface (SCI)
MOTOROLA
000
Prescaled clock 1
001
Prescaled clock 2
010
Prescaled clock 4
011
Prescaled clock 8
100
Prescaled clock 16
101
Prescaled clock 32
110
Prescaled clock 64
111
Prescaled clock
128
Table 10-3 shows all possible SCI baud rates derived from crystal
frequencies of 2 MHz, 4 MHz, and 4.194304 MHz.
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Serial Communications Interface (SCI)
137
SCR[2:1:0]
00
fOSC = 2 MHz
fOSC = 4 MHz
000
62.50 Kbaud
125 Kbaud
131.1 Kbaud
00
001
31.25 Kbaud
62.50 Kbaud
65.54 Kbaud
00
010
15.63 Kbaud
31.25 Kbaud
32.77 Kbaud
00
011
7813 baud
15.63 Kbaud
16.38 Kbaud
00
100
3906 baud
7813 baud
8192 baud
00
101
1953 baud
3906 baud
4096 baud
00
110
976.6 baud
1953 baud
2048 baud
00
111
488.3 baud
976.6 baud
1024 baud
01
000
20.83 Kbaud
41.67 Kbaud
43.69 Kbaud
01
001
10.42 Kbaud
20.83 Kbaud
21.85 Kbaud
01
010
5208 baud
10.42 Kbaud
10.92 Kbaud
01
011
2604 baud
5208 baud
5461 baud
01
100
1302 baud
2604 baud
2731 baud
01
101
651.0 baud
1302 baud
1365 baud
01
110
325.5 baud
651.0 baud
682.7 baud
01
111
162.8 baud
325.5 baud
341.3 baud
10
000
15.63 Kbaud
31.25 Kbaud
32.77 Kbaud
10
001
7813 baud
15.63 Kbaud
16.38 Kbaud
10
010
3906 baud
7813 baud
8192 baud
10
011
1953 baud
3906 baud
4906 baud
10
100
976.6 baud
1953 baud
2048 baud
10
101
488.3 baud
976.6 baud
1024 baud
10
110
244.1 baud
488.3 baud
512.0 baud
10
111
122.1 baud
244.1 baud
256.0 baud
11
000
4808 baud
9615 baud
10.08 Kbaud
11
001
2404 baud
4808 baud
5041 baud
11
010
1202 baud
2404 baud
2521 baud
11
011
601.0 baud
1202 baud
1260 baud
11
100
300.5 baud
601.0 baud
630.2 baud
11
101
150.2 baud
300.5 baud
315.1 baud
11
110
75.12 baud
150.2 baud
157.5 baud
11
111
37.56 baud
75.12 baud
78.77 baud
Technical Data
138
MC68HC705C8A Rev. 3
Serial Communications Interface (SCI)
MOTOROLA
11.1 Contents
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
11.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
11.6
11.2 Introduction
The serial peripheral interface (SPI) module allows full-duplex,
synchronous, serial communication with peripheral devices.
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Serial Peripheral Interface (SPI)
139
Full-duplex operation
Figure 11-1 shows the structure of the SPI module. Figure 11-2 is a
summary of the SPI input/output (I/O) registers.
Technical Data
140
MC68HC705C8A Rev. 3
Serial Peripheral Interface (SPI)
MOTOROLA
INTERNAL
CLOCK
(XTAL 2)
S
M
M
7 6 5 4 3 2 1 0
S
PIN CONTROL LOGIC
DIVIDER
2
32
SHIFT
CLOCK
SPDR ($000C)
SPI CLOCK (MASTER)
PD4/
SCK
PD5/
SS
SPR0
SPR1
CPOL
CPHA
MSTR
DWOM
SPIE
SPE
MSTR
SPE
DWOM
MODF
SPIF
WCOL
MSTR
SPE
SPIE
SPI CONTROL
PD3/
MOSI
CLOCK
LOGIC
SPR0
SPR1
SELECT
PD2/
MISO
SPCR ($000A)
SPSR ($000B)
SPI INTERRUPT
REQUEST
INTERNAL
DATA BUS
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Serial Peripheral Interface (SPI)
141
Addr.
$000A
$000B
$000C
Register Name
Read:
SPI Control Register
(SPCR) Write:
See page 149.
Reset:
Read:
SPI Status Register
(SPSR) Write:
See page 151.
Reset:
Read:
SPI Data Register
(SPDR) Write:
See page 149.
Reset:
Bit 7
SPIE
Bit 0
SPE
MSTR
CPOL
CPHA
SPR1
SPR0
SPIF
WCOL
MODF
Bit 7
Bit 6
Bit 3
BIt 2
Bit 1
Bit 0
Bit 5
Bit 4
Unaffected by reset
= Unimplemented
U = Unaffected
11.4 Operation
The master/slave SPI allows full-duplex, synchronous, serial
communication between the microcontroller unit (MCU) and peripheral
devices, including other MCUs. As the 8-bit shift register of a master SPI
transmits each byte to another device, a byte from the receiving device
enters the master SPI shift register. A clock signal from the master SPI
synchronizes data transmission.
Only a master SPI can initiate transmissions. Software begins the
transmission from a master SPI by writing to the SPI data register
(SPDR). The SPDR does not buffer data being transmitted from the SPI.
Data written to the SPDR goes directly into the shift register and begins
the transmission immediately under the control of the serial clock. The
transmission ends after eight cycles of the serial clock when the SPI flag
(SPIF) becomes set. At the same time that SPIF becomes set, the data
shifted into the master SPI from the receiving device transfers to the
SPDR. The SPDR buffers data being received by the SPI. Before the
master SPI sends the next byte, software must clear the SPIF bit by
reading the SPSR and then accessing the SPDR.
Technical Data
142
MC68HC705C8A Rev. 3
Serial Peripheral Interface (SPI)
MOTOROLA
In a slave SPI, data enters the shift register under the control of the serial
clock from the master SPI. After a byte enters the shift register of a slave
SPI, it transfers to the SPDR. To prevent an overrun condition, slave
software must then read the byte in the SPDR before another byte enters
the shift register and is ready to transfer to the SPDR.
Figure 11-3 shows how a master SPI exchanges data with a slave SPI.
PD3/MOSI
SPI SHIFT REGISTER
7 6 5 4 3 2 1 0
PD2/MISO
PD5/SS
SPDR ($000C)
SPDR ($000C)
PD4/SCK
MASTER MCU
SLAVE MCU
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Serial Peripheral Interface (SPI)
143
When CPHA = 0, the shift clock is the OR of SS with SCK. In this clock
phase mode, SS must go high between successive characters in an SPI
message. When CPHA = 1, SS may be left low for several SPI
characters. In cases with only one SPI slave MCU, the slave MCU SS
line can be tied to VSS as long as CPHA = 1 clock modes are used.
The WCOL flag bit can be improperly set when attempting the first
transmission after a reset if these conditions are present: MSTR = 0,
CPOL = 0, CPHA = 1, SS pin = 0, and SCK pin = 1. The reset states of
the CPOL and CPHA bits are 0 and 1, respectively. Under normal
operating conditions (CPOL = 0, CPHA = 1), the SCK input will be low.
The incorrect setting of the WCOL bit can be prevented in two ways:
1. Send a dummy transmission after reset, clear the WCOL flag, and
then proceed with the real transmission.
2. Use the MSTR bit in the SPCR (SPI control register). This is
accomplished by setting the MSTR bit at the same time the CPOL
and CPHA bits are programmed to the desired logic levels. Then,
the data register can be written to if desired. After this, the MSTR
bit should be set to a logic 0, the SPE (SPI enable bit) should be
set to a logic 1, and the CPOL, CPHA, SPR1, and SPR0 bits set
to the desired logic levels. If this procedure is followed after a reset
and before the first access to the SPDR, the WCOL flag will not be
set.
Technical Data
144
MC68HC705C8A Rev. 3
Serial Peripheral Interface (SPI)
MOTOROLA
Example:
LDA #$1C
STA SPCR
LDA #$4C
STA SPCR
;
;
;
;
;
;
VDD
SLAVE MCU 2
SLAVE MCU 1
PD2/MISO
PD3/MOSI
PD5/SS
PD4/SCK
PD2/MISO
PD3/MOSI
PD5/SS
PD4/SCK
PD2/MISO
PD3/MOSI
PD5/SS
PD4/SCK
I/O
PORT 1
0
SLAVE MCU 0
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Serial Peripheral Interface (SPI)
145
MASTER/SLAVE
MCU 2
PD2/MISO
PD2/MISO
PD3/MOSI
PD3/MOSI
PD4/SCK
PD4/SCK
PD5/SS
PD5/SS
SLAVE MCU 2
SLAVE MCU 1
I/O
PORT
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
I/O
PORT
SLAVE MCU 0
CPOL
SCK (A)
SCK (B)
SCK (C)
SCK (D)
SDO/SDI
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
CAPTURE STROBE
Technical Data
146
MC68HC705C8A Rev. 3
Serial Peripheral Interface (SPI)
MOTOROLA
Failing to read the SPDR before the next incoming byte sets the
SPIF bit (overrun error)
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Serial Peripheral Interface (SPI)
147
Technical Data
148
MC68HC705C8A Rev. 3
Serial Peripheral Interface (SPI)
MOTOROLA
$000C
Bit 7
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Address:
$000A
Bit 7
SPIE
0
Bit 0
SPE
MSTR
CPOL
CPHA
SPR1
SPR0
Read:
Write:
Reset:
= Unimplemented
U = Unaffected
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Serial Peripheral Interface (SPI)
149
00
Internal Clock
01
Internal Clock
10
Internal Clock
16
11
Internal Clock 32
Technical Data
150
MC68HC705C8A Rev. 3
Serial Peripheral Interface (SPI)
MOTOROLA
Write collision
Mode fault
Address:
Read:
$000B
Bit 7
SPIF
WCOL
MODF
Bit 0
Write:
Reset:
= Unimplemented
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Serial Peripheral Interface (SPI)
151
Technical Data
152
MC68HC705C8A Rev. 3
Serial Peripheral Interface (SPI)
MOTOROLA
12.1 Contents
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.6
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Instruction Set
153
Instruction Set
12.2 Introduction
The MCU instruction set has 62 instructions and uses eight addressing
modes. The instructions include all those of the M146805 CMOS Family
plus one more: the unsigned multiply (MUL) instruction. The MUL
instruction allows unsigned multiplication of the contents of the
accumulator (A) and the index register (X). The high-order product is
stored in the index register, and the low-order product is stored in the
accumulator.
Inherent
Immediate
Direct
Extended
Indexed, no offset
Relative
Technical Data
154
MC68HC705C8A Rev. 3
Instruction Set
MOTOROLA
Instruction Set
Addressing Modes
12.3.1 Inherent
Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.
12.3.2 Immediate
Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
12.3.3 Direct
Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.
12.3.4 Extended
Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.
When using the Motorola assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Instruction Set
155
Instruction Set
12.3.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000$00FF.
Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or I/O location.
MC68HC705C8A Rev. 3
Instruction Set
MOTOROLA
Instruction Set
Instruction Types
12.3.8 Relative
Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, twos complement byte that gives
a branching range of 128 to +127 bytes from the address of the next
location after the branch instruction.
When using the Motorola assembler, the programmer does not need to
calculate the offset, because the assembler determines the proper offset
and verifies that it is within the span of the branch.
Register/memory instructions
Read-modify-write instructions
Jump/branch instructions
Control instructions
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Instruction Set
157
Instruction Set
12.4.1 Register/Memory Instructions
These instructions operate on CPU registers and memory locations.
Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.
Table 12-1. Register/Memory Instructions
Instruction
Add memory byte and carry bit to accumulator
ADC
ADD
AND
BIT
Compare accumulator
CMP
CPX
EOR
LDA
LDX
Multiply
MUL
ORA
SBC
STA
STX
SUB
Technical Data
158
Mnemonic
MC68HC705C8A Rev. 3
Instruction Set
MOTOROLA
Instruction Set
Instruction Types
NOTE:
Mnemonic
ASL
ASR
Bit clear
BCLR(1)
Bit set
BSET(1)
Clear register
CLR
COM
Decrement
DEC
Increment
INC
LSL
LSR
NEG
ROL
ROR
TST(2)
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Instruction Set
159
Instruction Set
12.4.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.
The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from 128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.
Technical Data
160
MC68HC705C8A Rev. 3
Instruction Set
MOTOROLA
Instruction Set
Instruction Types
BCC
BCS
Branch if equal
BEQ
BHCC
BHCS
Branch if higher
BHI
BHS
BIH
BIL
Branch if lower
BLO
BLS
BMC
Branch if minus
BMI
BMS
BNE
Branch if plus
BPL
Branch always
BRA
BRCLR
BRN
BRSET
Branch to subroutine
BSR
Unconditional jump
JMP
Jump to subroutine
JSR
MC68HC705C8A Rev. 3
MOTOROLA
Mnemonic
Technical Data
Instruction Set
161
Instruction Set
12.4.4 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.
Table 12-4. Bit Manipulation Instructions
Instruction
Bit clear
BCLR
BRCLR
BRSET
Bit set
BSET
Technical Data
162
Mnemonic
MC68HC705C8A Rev. 3
Instruction Set
MOTOROLA
Instruction Set
Instruction Types
CLC
CLI
No operation
NOP
RSP
RTI
RTS
SEC
SEI
STOP
Software interrupt
SWI
TAX
TXA
WAIT
MC68HC705C8A Rev. 3
MOTOROLA
Mnemonic
Technical Data
Instruction Set
163
Instruction Set
12.5 Instruction Set Summary
#opr
opr
opr
opr,X
opr,X
,X
ADD
ADD
ADD
ADD
ADD
ADD
#opr
opr
opr
opr,X
opr,X
,X
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
IMM
DIR
EXT
IX2
IX1
IX
ii
A9
2
B9 dd 3
C9 hh ll 4
D9 ee ff 5
E9 ff
4
F9
3
IMM
DIR
EXT
IX2
IX1
IX
AB ii
2
BB dd 3
CB hh ll 4
DB ee ff 5
EB ff
4
FB
3
IMM
DIR
EXT
IX2
IX1
IX
ii
A4
2
B4 dd 3
C4 hh ll 4
D4 ee ff 5
E4 ff
4
F4
3
38
48
58
68
78
dd
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
REL
24
rr
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
Effect on
CCR
Description
H I N Z C
A (A) (M)
Logical AND
BCC rel
0
b7
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
A (A) + (M)
b0
C
b7
b0
PC (PC) + 2 + rel ? C = 0
Mn 0
ff
ff
Cycles
Opcode
ADC
ADC
ADC
ADC
ADC
ADC
Operation
Address
Mode
Source
Form
Operand
5
3
3
6
5
5
3
3
6
5
BCLR n opr
Clear Bit n
BCS rel
PC (PC) + 2 + rel ? C = 1
REL
25
rr
BEQ rel
Branch if Equal
PC (PC) + 2 + rel ? Z = 1
REL
27
rr
BHCC rel
PC (PC) + 2 + rel ? H = 0
REL
28
rr
BHCS rel
PC (PC) + 2 + rel ? H = 1
REL
29
rr
BHI rel
Branch if Higher
PC (PC) + 2 + rel ? C Z = 0
REL
22
rr
BHS rel
REL
24
rr
PC (PC) + 2 + rel ? C = 0
Technical Data
164
MC68HC705C8A Rev. 3
Instruction Set
MOTOROLA
Instruction Set
Instruction Set Summary
Address
Mode
Opcode
Operand
Cycles
BIH rel
REL
2F
rr
BIL rel
REL
2E
rr
IMM
DIR
EXT
IX2
IX1
IX
ii
A5
2
B5 dd 3
C5 hh ll 4
D5 ee ff 5
E5 ff
4
F5
3
REL
25
rr
PC (PC) + 2 + rel ? C Z = 1
REL
23
rr
Source
Form
Operation
Description
Effect on
CCR
H I N Z C
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BLO rel
BLS rel
BMC rel
PC (PC) + 2 + rel ? I = 0
REL
2C
rr
BMI rel
Branch if Minus
PC (PC) + 2 + rel ? N = 1
REL
2B
rr
BMS rel
PC (PC) + 2 + rel ? I = 1
REL
2D
rr
BNE rel
PC (PC) + 2 + rel ? Z = 0
REL
26
rr
BPL rel
Branch if Plus
PC (PC) + 2 + rel ? N = 0
REL
2A
rr
BRA rel
Branch Always
PC (PC) + 2 + rel ? 1 = 1
REL
20
rr
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
BRN rel
Branch Never
BSET n opr
(A) (M)
PC (PC) + 2 + rel ? C = 1
PC (PC) + 2 + rel ? Mn = 0
PC (PC) + 2 + rel ? 1 = 0
REL
21
rr
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
REL
AD
rr
PC (PC) + 2 + rel ? Mn = 1
Mn 1
Set Bit n
BSR rel
Branch to Subroutine
CLC
C0
INH
98
CLI
I0
INH
9A
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Instruction Set
165
Instruction Set
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
COM opr
COMA
COMX
COM opr,X
COM ,X
CPX
CPX
CPX
CPX
CPX
CPX
#opr
opr
opr
opr,X
opr,X
,X
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
EOR
EOR
EOR
EOR
EOR
EOR
#opr
opr
opr
opr,X
opr,X
,X
INC opr
INCA
INCX
INC opr,X
INC ,X
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
3F
4F
5F
6F
7F
dd
IMM
DIR
EXT
IX2
IX1
IX
ii
A1
2
B1 dd 3
C1 hh ll 4
D1 ee ff 5
E1 ff
4
F1
3
1
DIR
INH
INH
IX1
IX
33
43
53
63
73
IMM
DIR
EXT
IX2
IX1
IX
ii
A3
2
B3 dd 3
C3 hh ll 4
D3 ee ff 5
E3 ff
4
F3
3
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
IMM
DIR
EXT
IX2
IX1
IX
ii
A8
2
B8 dd 3
C8 hh ll 4
D8 ee ff 5
E8 ff
4
F8
3
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
DIR
EXT
IX2
IX1
IX
BC dd 2
CC hh ll 3
DC ee ff 4
EC ff
3
FC
2
H I N Z C
Clear Byte
Decrement Byte
Increment Byte
Unconditional Jump
M $00
A $00
X $00
M $00
M $00
(A) (M)
(X) (M)
M (M) 1
A (A) 1
X (X) 1
M (M) 1
M (M) 1
A (A) (M)
M (M) + 1
A (A) + 1
X (X) + 1
M (M) + 1
M (M) + 1
PC Jump Address
Technical Data
166
DIR
INH
INH
IX1
IX
Effect on
CCR
0 1
ff
dd
ff
dd
ff
dd
ff
Cycles
Description
Operand
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
Operation
Opcode
Source
Form
Address
Mode
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
MC68HC705C8A Rev. 3
Instruction Set
MOTOROLA
Instruction Set
Instruction Set Summary
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
Jump to Subroutine
A (M)
ii
A6
2
B6 dd 3
C6 hh ll 4
D6 ee ff 5
E6 ff
4
F6
3
IMM
DIR
EXT
IX2
IX1
IX
AE ii
2
BE dd 3
CE hh ll 4
DE ee ff 5
EE ff
4
FE
3
38
48
58
68
78
dd
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
0 0
INH
42
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
DIR
INH
INH
IX1
IX
30
40
50
60
70
NOP
No Operation
INH
9D
IMM
DIR
EXT
IX2
IX1
IX
AA ii
2
BA dd 3
CA hh ll 4
DA ee ff 5
EA ff
4
FA
3
DIR
INH
INH
IX1
IX
39
49
59
69
79
b0
X : A (X) (A)
M (M) = $00 (M)
A (A) = $00 (A)
X (X) = $00 (X)
M (M) = $00 (M)
M (M) = $00 (M)
A (A) (M)
b0
0
b7
b7
MC68HC705C8A Rev. 3
b0
ff
ff
Cycles
IMM
DIR
EXT
IX2
IX1
IX
C
b7
Unsigned Multiply
MOTOROLA
BD dd 5
CD hh ll 6
DD ee ff 7
ED ff
6
FD
5
X (M)
MUL
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
PC (PC) + n (n = 1, 2, or 3)
Push (PCL); SP (SP) 1
Push (PCH); SP (SP) 1
PC Effective Address
#opr
opr
opr
opr,X
opr,X
,X
DIR
EXT
IX2
IX1
IX
H I N Z C
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
ORA
ORA
ORA
ORA
ORA
ORA
Description
Opcode
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Operation
Effect on
CCR
Address
Mode
Source
Form
Operand
5
3
3
6
5
5
3
3
6
5
1
1
dd
ff
5
3
3
6
5
2
dd
ff
5
3
3
6
5
Technical Data
Instruction Set
167
Instruction Set
Opcode
Operand
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
INH
9C
INH
80
INH
81
IMM
DIR
EXT
IX2
IX1
IX
ii
A2
2
B2 dd 3
C2 hh ll 4
D2 ee ff 5
E2 ff
4
F2
3
Source
Form
Operation
Effect on
CCR
Description
H I N Z C
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
RSP
SP $00FF
RTI
RTS
C
b7
b0
ff
Cycles
Address
Mode
5
3
3
6
5
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SEC
C1
INH
99
SEI
I1
INH
9B
DIR
EXT
IX2
IX1
IX
B7 dd 4
C7 hh ll 5
D7 ee ff 6
E7 ff
5
F7
4
INH
8E
DIR
EXT
IX2
IX1
IX
BF dd 4
CF hh ll 5
DF ee ff 6
EF ff
5
FF
4
IMM
DIR
EXT
IX2
IX1
IX
ii
A0
2
B0 dd 3
C0 hh ll 4
D0 ee ff 5
E0 ff
4
F0
3
INH
83
1
0
INH
97
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
STOP
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
SUB
SUB
SUB
SUB
SUB
SUB
#opr
opr
opr
opr,X
opr,X
,X
SWI
Software Interrupt
TAX
M (A)
M (X)
A (A) (M)
X (A)
Technical Data
168
MC68HC705C8A Rev. 3
Instruction Set
MOTOROLA
Instruction Set
Opcode Map
TXA
WAIT
(M) $00
A (X)
Accumulator
Carry/borrow flag
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
opr
PC
PCH
PCL
REL
rel
rr
SP
X
Z
#
()
( )
?
:
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
dd
INH
9F
INH
8F
ff
Cycles
H I N Z C
TST opr
TSTA
TSTX
TST opr,X
TST ,X
A
C
CCR
dd
dd rr
DIR
ee ff
EXT
ff
H
hh ll
I
ii
IMM
INH
IX
IX1
IX2
M
N
n
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
4
3
3
5
4
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Instruction Set
169
Bit Manipulation
MSB
LSB
0
1
2
3
4
5
Instruction Set
6
7
8
9
A
B
C
MOTOROLA
MC68HC705C8A Rev. 3
D
E
F
Branch
Read-Modify-Write
Control
Register/Memory
DIR
DIR
REL
DIR
INH
INH
IX1
IX
INH
INH
IMM
DIR
EXT
IX2
IX1
IX
5
5
BSET0
BRSET0
DIR
3
DIR 2
5
5
BCLR0
BRCLR0
DIR
3
DIR 2
5
5
BSET1
BRSET1
DIR
3
DIR 2
5
5
BCLR1
BRCLR1
DIR
3
DIR 2
5
5
BSET2
BRSET2
DIR
3
DIR 2
5
5
BCLR2
BRCLR2
DIR
3
DIR 2
5
5
BSET3
BRSET3
DIR
3
DIR 2
5
5
BCLR3
BRCLR3
DIR
3
DIR 2
5
5
BSET4
BRSET4
DIR
3
DIR 2
5
5
BCLR4
BRCLR4
DIR
3
DIR 2
5
5
BSET5
BRSET5
DIR
3
DIR 2
5
5
BCLR5
BRCLR5
DIR
3
DIR 2
5
5
BSET6
BRSET6
DIR
3
DIR 2
5
5
BCLR6
BRCLR6
DIR
3
DIR 2
5
5
BSET7
BRSET7
DIR
3
DIR 2
5
5
BCLR7
BRCLR7
DIR
3
DIR 2
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
5
6
3
3
5
3
NEG
NEG
NEGX
NEGA
NEG
BRA
IX 1
IX1 1
INH 2
INH 1
DIR 1
REL 2
3
BRN
2
REL
1
3
11
BHI
MUL
2
REL
1
INH
5
6
3
3
5
3
COM
COM
COMX
COMA
COM
BLS
IX 1
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
5
6
3
3
5
3
LSR
LSR
LSRX
LSRA
LSR
BCC
IX
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
3
BCS/BLO
2
REL
5
6
3
3
5
3
ROR
ROR
RORX
RORA
ROR
BNE
IX
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
5
6
3
3
5
3
ASR
ASR
ASRX
ASRA
ASR
BEQ
IX
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
5
6
3
3
5
3
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL
BHCC
IX
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
5
6
3
3
5
3
ROL
ROL
ROLX
ROLA
ROL
BHCS
IX
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
5
6
3
3
5
3
DEC
DEC
DECX
DECA
DEC
BPL
IX
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
3
BMI
2
REL
5
6
3
3
5
3
INC
INC
INCX
INCA
INC
BMC
IX
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
4
5
3
3
4
3
TST
TST
TSTX
TSTA
TST
BMS
IX
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
3
BIL
2
REL
1
5
6
3
3
5
3
CLR
CLR
CLRX
CLRA
CLR
BIH
IX 1
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
2
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
9
RTI
INH
6
RTS
INH
2
2
2
10
SWI
INH
2
2
2
2
1
1
1
1
1
1
1
2
TAX
INH
2
CLC
INH
2
SEC
INH
2
CLI
INH
2
SEI
INH
2
RSP
INH
2
NOP
INH
2
STOP
INH
2
2
TXA
WAIT
INH
INH 1
2
SUB
IMM
2
CMP
IMM
2
SBC
IMM
2
CPX
IMM
2
AND
IMM
2
BIT
IMM
2
LDA
IMM
2
2
2
2
2
2
2
2
EOR
IMM
2
ADC
2
IMM
2
ORA
2
IMM
2
ADD
2
IMM
2
2
2
2
2
2
6
BSR
2
REL 2
2
LDX
2
IMM 2
2
MSB
LSB
3
SUB
DIR
3
CMP
DIR
3
SBC
DIR
3
CPX
DIR
3
AND
DIR
3
BIT
DIR
3
LDA
DIR
4
STA
DIR
3
EOR
DIR
3
ADC
DIR
3
ORA
DIR
3
ADD
DIR
2
JMP
DIR
5
JSR
DIR
3
LDX
DIR
4
STX
DIR
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
SUB
EXT
4
CMP
EXT
4
SBC
EXT
4
CPX
EXT
4
AND
EXT
4
BIT
EXT
4
LDA
EXT
5
STA
EXT
4
EOR
EXT
4
ADC
EXT
4
ORA
EXT
4
ADD
EXT
3
JMP
EXT
6
JSR
EXT
4
LDX
EXT
5
STX
EXT
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
5
SUB
IX2
5
CMP
IX2
5
SBC
IX2
5
CPX
IX2
5
AND
IX2
5
BIT
IX2
5
LDA
IX2
6
STA
IX2
5
EOR
IX2
5
ADC
IX2
5
ORA
IX2
5
ADD
IX2
4
JMP
IX2
7
JSR
IX2
5
LDX
IX2
6
STX
IX2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
SUB
IX1 1
4
CMP
IX1 1
4
SBC
IX1 1
4
CPX
IX1 1
4
AND
IX1 1
4
BIT
IX1 1
4
LDA
IX1 1
5
STA
IX1 1
4
EOR
IX1 1
4
ADC
IX1 1
4
ORA
IX1 1
4
ADD
IX1 1
3
JMP
IX1 1
6
JSR
IX1 1
4
LDX
IX1 1
5
STX
IX1 1
5 Number of Cycles
BRSET0 Opcode Mnemonic
3
DIR Number of Bytes/Addressing Mode
MSB
LSB
3
SUB
IX
3
CMP
IX
3
SBC
IX
3
CPX
IX
3
AND
IX
3
BIT
IX
3
LDA
IX
4
STA
IX
3
EOR
IX
3
ADC
IX
3
ORA
IX
3
ADD
IX
2
JMP
IX
5
JSR
IX
3
LDX
IX
4
STX
IX
Instruction Set
Technical Data
170
Section 13.
Electrical Specifications
13.1 Contents
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
13.3
13.4
13.5
13.6
13.7
13.8
13.9
13.2 Introduction
This section contains electrical and timing specifications.
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Electrical Specifications
171
Electrical Specifications
13.3 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table here. Keep VIn and VOut within the range
VSS (VIn or VOut) VDD. Connect unused inputs to the appropriate
voltage level, either VSS or VDD.
Rating(1)
Symbol
Value
Unit
Supply voltage
VDD
0.3 to +7.0
Input voltage
VIn
VSS 0.3
to VDD +0.3
Programming voltage
VPP
VDD 0.3 to
16.0
VIn
VSS 0.3
to 2 x VDD + 0.3
25
mA
TSTG
65 to +150
NOTE:
Technical Data
172
MC68HC705C8A Rev. 3
Electrical Specifications
MOTOROLA
Electrical Specifications
Operating Temperature Range
Symbol
Value
Unit
TA
TL to TH
40 to + 85
Symbol
Value
Unit
60
50
70
95
60
JA
C/W
VDD = 4.5 V
VDD
Pins
R2
(SEE TABLE)
TEST
POINT
C
(SEE TABLE)
R1
(SEE TABLE)
PA7PA0
PB7PB0
PC7PC0
PD4PD1
R1
R2
3.26 k
2.38 k
50 pF
R1
R2
10.91 k
6.32 k
50 pF
6 k
6 k
200 pF
VDD = 3.0 V
Pins
PA7PA0
PB7PB0
PC7PC0
PD4PD1
PD7, PD5, PD0
Technical Data
Electrical Specifications
173
Electrical Specifications
13.6 Power Considerations
The average chip junction temperature, TJ, in C can be obtained from:
TJ = TA + (PD x JA)
(1)
Where:
TA = ambient temperature in C
JA = package thermal resistance, junction to ambient in C/W
PD = PINT + PI/O
PINT = ICC VCC = chip internal power dissipation
PI/O = power dissipation on input and output pins (user-determined)
For most applications, PI/O < PINT and can be neglected.
Ignoring PI/O, the relationship between PD and TJ is approximately:
K
PD =
(2)
TJ + 273C
Solving equations (1) and (2) for K gives:
= PD x (TA + 273C) + JA x (PD)2
(3)
Technical Data
174
MC68HC705C8A Rev. 3
Electrical Specifications
MOTOROLA
Electrical Specifications
5.0-Volt DC Electrical Characteristics
Symbol
Min
Typ(2)
Max
Unit
VOL
VOH
VDD 0.1
0.1
VOH
VDD 0.8
VOL
0.4
0.4
VIH
0.7 x VDD
VDD
VIL
VSS
0.2 x VDD
VPP
14.5
14.75
15.0
IPP
10
mA
IPP
10
mA
VRM
2.0
5.0
1.95
7.0
3.0
mA
mA
5.0
5.0
50
50
A
A
IIL
10
IIn
COut
CIn
12
8
pF
(3)
Supply current
Run(4)
Wait(5)
Stop(6)
25C
40C to +85C
I/O ports hi-z leakage current
PA7PA0, PB7PB0, PC7PC0, PD4PD1, PD7, RESET
Input current, IRQ, TCAP, OSC1, PD0, PD5
Capacitance
Ports (as input or output)
RESET, IRQ, TCAP, PD0PD5, PD7
IDD
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Electrical Specifications
175
Electrical Specifications
13.8 3.3-Volt DC Electrical Characteristics
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
VOL
VOH
VDD 0.1
0.1
VOH
VDD 0.3
VOL
0.3
0.3
VIH
0.7 x VDD
VDD
VIL
VSS
0.2 x VDD
VRM
2.0
Supply current(3)
Run(4)
Wait(5)
Stop(6)
IDD
1.53
0.711
2.0
3.0
1.0
20
mA
mA
A
IIL
10
Input current
IRQ, TCAP, OSC1, PD5, PD0
IIn
Technical Data
176
MC68HC705C8A Rev. 3
Electrical Specifications
MOTOROLA
Electrical Specifications
3.3-Volt DC Electrical Characteristics
5.0
4.0
V DD
=5
.0 V
IOH (mA)
3.0
2.0
V DD
= 3.
0V
SEE NOTE 1
1.0
0.8
SEE NOTE 2
0.2
0
0
0.2
0.4
0.6
0.8
8.0
6.0
IOH (mA)
V
.0
=5
V DD
4.0
2.0
1.6
V DD
.0
=3
SEE NOTE 1
SEE NOTE 2
0.4
0
0
0.2
0.4
0.6
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Electrical Specifications
177
Electrical Specifications
6.0
5.0
4.0
IOL (MA)
V DD
=5
.0
3.0
V DD
2.0
.0
=3
SEE NOTE 1
1.6
1.0
SEE NOTE 2
0.4
0
0
0.1
0.2
0.3
0.4
VOL (VOLTS)
Notes:
1. At VDD = 5.0 V, devices are specified and tested for
VOL 400 mV @ IOL = 1.6 mA.
2. At VDD = 3.3 V, devices are specified and tested for
VOL 300 mV @ IOL = 0.4 mA.
Technical Data
178
MC68HC705C8A Rev. 3
Electrical Specifications
MOTOROLA
Electrical Specifications
3.3-Volt DC Electrical Characteristics
2.0
1.8
1.6
=5
.0
1.4
DD
IDD (mA)
1.2
1.0
0.8
0.6
=3
0.4
.3
V DD
0.2
0.0
0.0
0.5
1.0
1.5
INTERNAL FREQUENCY 1 tCYC (MHz)
2.0
=5
.0
4.0
DD
3.5
IDD (mA)
3.0
2.5
2.0
1.5
1.0
V DD
=3
V
.3
0.5
0.0
0.0
0.5
1.0
1.5
INTERNAL FREQUENCY 1 tCYC (MHz)
2.0
Technical Data
Electrical Specifications
179
Electrical Specifications
3.0 mA
T = 40C to 85C
VDD = 3.3 V 10%
2.5 mA
2.0 mA
N
RU
1.5 mA
G
TIN
RA
E
P
(O
)ID
1.0 mA
WAIT
I DD
500 mA
(20 A)
STOP IDD
0
0
250 kHz
500 kHz
750 kHz
1 MHz
7.0 mA
T = 40C to 85C
VDD = 5.0 V 10%
6.0 mA
5.0 mA
4.0 mA
N
RU
(O
PE
G
TIN
A
R
)ID
3.0 mA
WA
2.0 mA
IT I DD
1.0 mA
STOP IDD
(50 A)
0
0
500 kHz
1 MHz
1.5 MHz
2 MHz
Technical Data
180
MC68HC705C8A Rev. 3
Electrical Specifications
MOTOROLA
Electrical Specifications
5.0-Volt Control Timing
Symbol
Min
Max
Unit
Frequency of operation
Crystal option
External clock option
fOSC
dc
4.2
4.2
MHz
fOP
dc
2.1
2.1
MHz
tCYC
480
ns
tOXOV
100
ms
tILCH
100
ms
tRL
tCYC
Timer
Resolution(2)
Input capture pulse width (see Figure 13-5)
Input capture pulse period (see Figure 13-5)
tRESL
tTH, tTL
tTLTL
4.0
125
(3)
tCYC
ns
tCYC
tILIH
125
ns
tILIL
(4)
tCYC
tOH, tOL
90
ns
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Electrical Specifications
181
Electrical Specifications
13.10 3.3-Volt Control Timing
Characteristic(1)
Symbol
Min
Max
Unit
Frequency of operation
Crystal option
External clock option
fOSC
dc
2.0
2.0
MHz
fOP
dc
1.0
1.0
MHz
tCYC
1000
ns
tOXOV
100
ms
tILCH
100
ms
tRL
tCYC
Timer
Resolution(2)
Input capture pulse width (see Figure 13-5)
Input capture pulse period (see Figure 13-5)
tRESL
tTH, tTL
tTLTL
4.0
250
(3)
tCYC
ns
tCYC
tILIH
250
ns
tILIL
(4)
tCYC
tOH, tOL
200
ns
tTLTL*
tTH*
tTL*
EXTERNAL SIGNAL
(TCAP PIN 37)
*
MC68HC705C8A Rev. 3
Electrical Specifications
MOTOROLA
Electrical Specifications
3.3-Volt Control Timing
(1)
OSC1
RESET
IRQ(2)
IRQ
(3)
tRL
tILIH
tILCH
4064 tCYC
INTERNAL
CLOCK
INTERNAL
ADDRESS
BUS
1FFE
1FFE
1FFE
1FFE
1FFF(4)
RESET OR INTERRUPT
VECTOR FETCH
Notes:
1. Represents the internal gating of the OSC1 pin
2. IRQ pin edge-sensitive option
3. IRQ pin level and edge-sensitive option
4. RESET vector address shown for timing example
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Electrical Specifications
183
Electrical Specifications
Technical Data
184
tVDDR
VDD
OSC1*
tOXOV
tCYC
Electrical Specifications
INTERNAL
PROCESSOR
CLOCK
INTERNAL
ADDRESS
BUS **
1FFE
1FFF
NEW PC
INTERNAL
DATA
BUS ***
NEW
PCH
NEW
PCL
OP
CODE
1FFE
1FFE
1FFE
1FFE
1FFF
NEW PC
PCH
PCL
OP
CODE
tRL
RESET
* * *
MOTOROLA
MC68HC705C8A Rev. 3
* OSC1 line is not meant to represent frequency. It is only used to represent time.
** Internal timing signal and bus information are not available externally.
*** The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.
Figure 13-7. Power-On Reset and External Reset Timing Diagram
Electrical Specifications
5.0-Volt Serial Peripheral Interface (SPI) Timing
Characteristic(2)
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
fOP(M)
fOP(S)
dc
dc
0.5
2.1
fOP
MHz
Cycle time
Master
Slave
tCYC(M)
tCYC(S)
2.0
480
tCYC
ns
tLead(M)
tLead(S)
(3)
ns
240
tLag(M)
tLag(S)
ns
720
(2)
tW(SCKH)M
tW(SCKH)S
340
190
ns
tW(SCKL)M
tW(SCKL)S
340
190
ns
tSU(M)
tSU(S)
100
100
ns
tH(M)
tH(S)
100
100
ns
Access time(4)
Slave
tA
120
ns
Disable time(5)
Slave
tDIS
240
ns
10
tV(M)
tV(S)
0.25
240
tCYC(M)
ns
Continued
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Electrical Specifications
185
Electrical Specifications
Number(1)
Characteristic(2)
Symbol
Min
Max
Unit
tHO(M)
tHO(S)
0.25
0
tCYC(M)
ns
11
12
Rise time(7)
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, MISO, SS)
tR(M)
tR(S)
100
2.0
ns
s
13
Fall time(8)
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, MISO, SS)
tF(M)
tF(S)
100
2.0
ns
s
Technical Data
186
MC68HC705C8A Rev. 3
Electrical Specifications
MOTOROLA
Electrical Specifications
3.3-Volt Serial Peripheral Interface (SPI) Timing
Characteristic(2)
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
fOP(M)
fOP(S)
dc
0.5
2.1
fOP
MHz
Cycle time
Master
Slave
tCYC(M)
tCYC(S)
2.0
1
tCYC
ns
tLead(M)
tLead(S)
(3)
ns
500
tLag(M)
tLag(S)
ns
1500
(2)
tW(SCKH)M
tW(SCKH)S
720
400
ns
tW(SCKL)M
tW(SCKL)S
720
400
ns
tSU(M)
tSU(S)
200
200
ns
tH(M)
tH(S)
200
200
ns
Access time(4)
Slave
tA
250
ns
Disable time(5)
Slave
tDIS
500
ns
10
tV(M)
tV(S)
0.25
500
tCYC(M)
ns
Continued
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Electrical Specifications
187
Electrical Specifications
Number(1)
Characteristic(2)
Symbol
Min
Max
Unit
tHO(M)
tHO(S)
0.25
0
tCYC(M)
ns
11
12
Rise time(7)
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, MISO, SS)
tR(M)
tR(S)
200
2.0
ns
s
13
Fall time(8)
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, MISO, SS)
tF(M)
tF(S)
200
2.0
ns
s
Technical Data
188
MC68HC705C8A Rev. 3
Electrical Specifications
MOTOROLA
Electrical Specifications
3.3-Volt Serial Peripheral Interface (SPI) Timing
SS
INPUT
1
SCK (CPOL = 0)
OUTPUT
13
12
NOTE
4
12
SCK (CPOL = 1)
OUTPUT
13
NOTE
4
6
MISO
INPUT
MSB IN
BITS 61
10
11
MOSI
OUTPUT
7
LSB IN
10
11
BITS 61
13
12
Note: This first clock edge is generated internally, but is not seen at the SCK pin.
SS
INPUT
SCK (CPOL = 0)
OUTPUT
13
12
NOTE
4
12
SCK (CPOL = 1)
OUTPUT
13
NOTE
4
6
MISO
INPUT
MSB IN
10
BITS 61
11
MOSI
OUTPUT
7
LSB IN
10
BITS 61
13
11
MASTER LSB OUT
12
Note: This last clock edge is generated internally, but is not seen at the SCK pin.
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Electrical Specifications
189
Electrical Specifications
SS
INPUT
1
SCK (CPOL = 0)
(INPUT
13
12
12
13
11
5
4
2
SCK (CPOL = 1)
INPUT
5
4
8
MISO
INPUT
SLAVE
MSB OUT
6
MOSI
OUTPUT
BITS 61
NOTE
11
10
MSB IN
BITS 61
LSB IN
SS
INPUT
13
1
SCK (CPOL = 0)
INPUT
12
5
4
2
SCK (CPOL = 1)
INPUT
8
MISO
OUTPUT
MOSI
INPUT
5
4
10
NOTE
12
SLAVE
MSB OUT
13
BITS 61
10
MSB IN
9
SLAVE LSB OUT
11
BITS 61
LSB IN
Technical Data
190
MC68HC705C8A Rev. 3
Electrical Specifications
MOTOROLA
14.1 Contents
14.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
14.3
14.4
14.5
14.6
14.7
14.8
14.2 Introduction
Package dimensions available at the time of this publication for the
MC68HC705C8A are provided in this section. The packages are:
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Mechanical Specifications
191
Mechanical Specifications
14.3 40-Pin Plastic Dual In-Line Package (PDIP)
40
21
B
1
20
A
C
N
J
H
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
51.69
52.45
13.72
14.22
3.94
5.08
0.36
0.56
1.02
1.52
2.54 BSC
1.65
2.16
0.20
0.38
2.92
3.43
15.24 BSC
0
1
0.51
1.02
INCHES
MIN
MAX
2.035
2.065
0.540
0.560
0.155
0.200
0.014
0.022
0.040
0.060
0.100 BSC
0.065
0.085
0.008
0.015
0.115
0.135
0.600 BSC
0
1
0.020
0.040
SEATING
PLANE
NOTES:
1.POSITION TOLERANCE OF LEADS (D), SHALL
BEWITHIN 0.25 (0.010) AT MAXIMUM MATERIAL
CONDITIONS, IN RELATION TO SEATING PLANE
AND EACH OTHER.
2.DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3.DIMENSION B DOES NOT INCLUDE MOLD FLASH.
Technical Data
192
MC68HC705C8A Rev. 3
Mechanical Specifications
MOTOROLA
Mechanical Specifications
40-Pin Ceramic Dual In-Line Package (Cerdip)
40
21
B
1
20
N
C
SEATING
PLANE
DATUM
PLANE
DIM
J
M
F
D 40 PL
0.25(0.010) M T A M
A
B
C
D
F
G
J
K
L
M
N
INCHES
MILLIMETERS
MIN
MAX
MIN MAX
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Mechanical Specifications
193
Mechanical Specifications
14.5 44-Lead Plastic-Leaded Chip Carrier (PLCC)
-N-
Y BRK
0.007(0.180) M T
L-M S
0.007(0.180) M T
N S
L-M
N S
Z
-M-
-L-
V
44
G1
0.010 (0.25) S T
VIEW D-D
0.007(0.180) M T
L-M
N S
0.007(0.180) M T
L-M
N S
0.007(0.180) M T
L-M S
L-M S
N S
N S
Z
J
K1
E
0.004 (0.10)
-TG1
0.010 (0.25) S T
L-M S
N S
SEATING
PLANE
VIEW S
0.007(0.180) M T
L-M S
N S
VIEW S
NOTES:
1. DATUMS -L-, -M-, AND -N- ARE DETERMINED
WHERE TOP OF LEAD SHOLDERS EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSION R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010
(0.25) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE DETERMINED
AT THE OUTERMOST EXTREMES OF THE
PLASTIC BODY EXCLUSIVE OF THE MOLD
FLASH, TIE BAR BURRS, GATE BURRS AND
INTERLEAD FLASH, BUT INCLUDING ANY
MISMATCH BETWEEN THE TOP AND BOTTOM
OF THE PLASTIC BODY.
7. DIMINSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTUSION(S) SHALL NOT CAUSE THE H
DIMINSION TO BE GREATER THAN 0.037
(0.940198). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMINISION TO SMALLER
THAN 0.025 (0.635).
INCHES
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
MIN
MAX
0.685
0.695
0.685
0.695
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
0.025
0.650
0.656
0.650
0.656
0.042
0.048
0.042
0.048
0.042
0.056
0.020
2
10
0.610
0.630
0.040
MILLIMETERS
MIN
MAX
17.40
17.65
17.40
17.65
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
0.64
16.51
16.66
16.51
16.66
1.07
1.21
1.07
1.21
1.07
1.42
0.50
2
10
15.50
16.00
1.02
MC68HC705C8A Rev. 3
Mechanical Specifications
MOTOROLA
Mechanical Specifications
44-Lead Ceramic-Leaded Chip Carrier (CLCC)
0.18 (0.007) M T N S -P S
B
-N-
Y BRK
L S
0.18 (0.007) M T N S -P S
L S
-L-
44
DETAIL D-D
-P-
G1
0.25 (0.010) M T N S -P S
L S
0.20 (0.008) M T L M N M -P M
V
0.18 (0.007) M T L S N S -P S
0.18 (0.007) M T L S N S -P S
NOTES:
1. DATUMS -L-, -N-, AND -P- DETERMINED
WHERE TOP OF LEAD SHOULDER EXIT
BODY.
2. DIMINSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING
PLANE.
3. DIMINSIONS R AND U DO NOT INCLUDE
GLASS MENISCUS. ALLOWABLE GLASS
RUNOUT IS 0.25 (0.010) PER SIDE.
4. DIMINSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
E
0.10 (0.004)
-T-
DETAIL S
G1
SEATING
PLANE
0.25 (0.010) S T L S N S -P S
0.18 (0.007) M T L S N S -P S
H
0.18 (0.007) M T N S -P S L S
K1
DIM
A
B
C
E
F
G
H
J
K
R
S
U
V
W
Y
G1
K1
MILLIMETERS
MIN
MAX
17.40 17.65
17.40 17.65
4.20
4.57
2.79
2.29
0.33
0.48
1.27 BSC
0.66
0.81
0.51
--0.64
--16.51 16.66
6.94
7.26
16.51 16.66
1.07
1.21
1.07
1.21
--0.50
14.99 16.00
1.02
---
INCHES
MIN
MAX
0.685
0.695
0.685
0.695
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
--0.025
--0.650
0.656
0.273
0.286
0.650
0.656
0.042
0.048
0.042
0.048
--0.020
0.590
0.630
0.040
---
K
F
0.18 (0.007) M T L S N S -P S
0.18 (0.007) M T N S -P S L S
DETAIL S
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Mechanical Specifications
195
Mechanical Specifications
14.7 44-Pin Quad Flat Pack (QFP)
B
L
33
23
44
D
S
0.20
(0.008) M
H A-B
S
S
DETAIL A
-B-
B
0.20 (0.008) M C A-B
-A-
22
34
11
DETAIL C
C E
-H-
-CSEATING
PLANE
DATUM
PLANE
0.01 (0.004)
H
M
T
DATUM
PLANE -H-
K
W
X
DETAIL C
F
BASE METAL
SECTION B-B
-DA
0.20 (0.008) M C A-B
DETAIL A
D
0.20 (0.008) M C A-B
12
1
MILLIMETERS
DIM MIN
MAX
A
9.90 10.10
B
9.90 10.10
C
2.10
2.45
D
0.30
0.45
E
2.00
2.10
F
0.30
0.40
G
0.80 BSC
H
--0.25
J 0.013
0.23
K
0.65
0.95
L
8.00 REF
M
5
10
N
0.13
0.17
Q
0
7
R
0.13
0.30
S 12.95 13.45
T
0.13
--U
0
--V 12.95 13.45
W
0.40
--X
1.6 REF
NOTES:
1. 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. 2. CONTROLLING DIMENSION: MILLIMETER.
3. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD WHERE
THE LEAD EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT
DATUM PLANE -H-.
5. 5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE -C-.
6. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE -H-.
7. 7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION. DAMBAR CANNOT BE
LOCATED ON THE LOWER RADIUS OR THE FOOT.
INCHES
MIN MAX
0.390 0.398
0.390 0.398
0.083 0.096
0.012 0.018
0.079 0.083
0.012 0.016
0.031 BSC
--- 0.010
0.005 0.009
0.026 0.037
0.315 REF
5
10
0.005 0.007
0
7
0.005 0.012
0.510 0.530
0.005
--0
--0.510 0.530
0.016
--0.063 REF
MC68HC705C8A Rev. 3
Mechanical Specifications
MOTOROLA
Mechanical Specifications
42-Pin Shrink Dual In-Line Package (SDIP)
NOTES:
1. DIMENSIONS AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH. MAXIMUM MOLD FLASH 0.25 (0.010).
22
-B1
21
DIM
A
B
C
D
F
G
H
J
K
L
M
N
-TSEATING
PLANE
0.25 (0.010)
F
D 42 PL
K
M
T A
M
J 42 PL
0.25 (0.010)
T B
INCHES
MIN
MAX
1.435 1.465
0.540 0.560
0.155 0.200
0.014 0.022
0.032 0.046
0.070 BSC
0.300 BSC
0.008 0.015
0.115 0.135
0.600 BSC
0
15
0.020 0.040
MILLIMETERS
MIN
MAX
36.45 37.21
13.72 14.22
3.94
5.08
0.36
0.56
0.81
1.17
1.778 BSC
7.62 BSC
0.20
0.38
2.92
3.43
15.24 BSC
0
15
0.51
1.02
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Mechanical Specifications
197
Mechanical Specifications
Technical Data
198
MC68HC705C8A Rev. 3
Mechanical Specifications
MOTOROLA
15.1 Contents
15.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
15.3
15.2 Introduction
This section contains ordering information for the available package
types.
Temperature Range
Order Number
40C to +85C
MC68HC705C8AC (1)P(2)
40C to +85C
MC68HC705C8ACFN(3)
40C to +85C
MC68HC705C8ACFS(4)
40C to +85C
MC68HC705C8ACS(5)
40C to +85C
MC68HC705C8ACFB(6)
40C to +85C
MC68HC705C8ACB(7)
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Ordering Information
199
Ordering Information
Technical Data
200
MC68HC705C8A Rev. 3
Ordering Information
MOTOROLA
Appendix A. MC68HSC705C8A
A.1 Contents
A.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
A.3
A.4
A.5
A.6
A.7
A.8
A.9
A.2 Introduction
The MC68HSC705C8A is an enhanced, high-speed version of the
MC68HC705C8A, featuring a 4-MHz bus speed.
The data in this document, MC68HC705C8A Technical Data Rev. 3,
applies to the MC68HSC705C8A with the exceptions given in this
appendix.
The computer operating properly (COP) mode bits (CM1 and CM0 in the
COP control register) select the timeout period of the programmable
COP watchdog, as shown in Table A-1. See Figure 5-3.
Programmable COP Control Register (COPCR).
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
MC68HSC705C8A
201
MC68HSC705C8A
Table A-1. Programmable COP Timeout Period Selection
CM1:CM0
COP
Timeout
Rate
00
fOP 215
8.192 ms
16.38 ms
18.31 ms
32.77 ms
01
fOP 217
32.77 ms
65.54 ms
73.24 ms
131.07 ms
10
fOP 219
131.07 ms
262.14 ms
292.95 ms
524.29 ms
11
fOP 221
524.29 ms
1.048 s
1.172 s
2.097 s
Typ(2)
Max
0.4
0.4
5.92
2.27
14
7.0
mA
mA
5
2.0
50
50
A
A
Symbol
Min
VOH
VDD 0.8
VOL
Supply current(3)
Run(4)
Wait(5)
Stop(6)
25C
40C to +85C
IDD
Unit
Technical Data
202
MC68HC705C8A Rev. 3
MC68HSC705C8A
MOTOROLA
MC68HSC705C8A
Typ(2)
Max
0.3
0.3
1.91
0.915
2.0
6.0
2.0
20
Symbol
Min
VOH
VDD 0.3
VOL
Supply current(3)
Run(4)
Wait(5)
Stop(6)
IDD
Unit
mA
mA
A
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
MC68HSC705C8A
203
MC68HSC705C8A
A.5 5.0-Volt High-Speed Control Timing
Characteristic(1)
Symbol
Min
Max
Unit
Oscillator frequency
Crystal oscillator
External clock
fOSC
dc
8.0
8.0
MHz
fOP
dc
4.0
4.0
MHz
Cycle time
tCYC
250
ns
tTH, tTL
65
ns
tILIH
65
ns
tOH, tOL
45
ns
Symbol
Min
Max
Unit
Oscillator frequency
Crystal oscillator
External clock
fOSC
dc
4.0
4.0
MHz
fOP
dc
2.0
2.0
MHz
Cycle time
tCYC
476
ns
tTH, tTL
125
ns
tILIH
125
ns
tOH, tOL
90
ns
Technical Data
204
MC68HC705C8A Rev. 3
MC68HSC705C8A
MOTOROLA
MC68HSC705C8A
Characteristic(2)
Operating frequency
Master
Slave
Symbol
Min
Max
Unit
fOP(S)
fOP(S)
dc
dc
0.5
4.0
fOP
MHz
Cycle time
Master
Slave
tCYC(M)
tCYC(S)
2.0
250
tCYC
ns
tLead(M)
tLead(S)
Note (3)
125
ns
tLag(M)
tLag(S)
Note(2)
375
ns
tW(SCKH)M
tW(SCKH)S
170
95
ns
tW(SCKL)M
tW(SCKL)S
170
95
ns
tSU(M)
tSU(S)
50
50
ns
tH(M)
tH(S)
50
50
ns
Access time(4)
Slave
tA
60
ns
Disable time(5)
Slave
tDIS
120
ns
tV(M)
tV(S)
0.25
120
tCYC(M)
ns
10
Continued
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
MC68HSC705C8A
205
MC68HSC705C8A
Diagram
Number(1)
Characteristic(2)
Symbol
Min
Max
Unit
tHO(M)
tHO(S)
0.25
0
tCYC(M)
ns
11
12
Rise time(7)
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, MISO, SS)
tRM
tRS
50
2.0
ns
s
13
Fall time(8)
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, MISO, SS)
tFM
tFS
50
2.0
ns
s
1. Diagram numbers refer to dimensions in Figure 13-8. SPI Master Timing and Figure 13-9. SPI Slave Timing.
2. VDD = 5 V 10%; VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
3. Signal production depends on software.
4. Time to data active from high-impedance state
5. Hold time to high-impedance state
6. With 200 pF on all SPI pins.
7. 20% of VDD to 70% of VDD; CL = 200 pF
8. 70% of VDD to 20% of VDD; CL = 200 pF
Technical Data
206
MC68HC705C8A Rev. 3
MC68HSC705C8A
MOTOROLA
MC68HSC705C8A
Characteristic(2)
Operating frequency
Master
Slave
Symbol
Min
Max
Unit
fOP(S)
fOP(S)
dc
dc
0.5
2.1
fOP
MHz
Cycle time
Master
Slave
tCYC(M)
tCYC(S)
2.0
480
tCYC
ns
tLead(M)
tLead(S)
Note (3)
240
ns
tLag(M)
tLag(S)
Note(2)
720
ns
tW(SCKH)M
tW(SCKH)S
340
190
ns
tW(SCKL)M
tW(SCKL)S
340
190
ns
tSU(M)
tSU(S)
100
100
ns
tH(M)
tH(S)
100
100
ns
Access time(4)
Slave
tA
120
Disable time(5)
Slave
tDIS
240
10
tV(M)
tV(S)
0.25
240
ns
ns
tCYC(M)
ns
Continued
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
MC68HSC705C8A
207
MC68HSC705C8A
Diagram
Number(1)
Characteristic(2)
Symbol
Min
Max
Unit
tHO(M)
tHO(S)
0.25
0
tCYC(M)
ns
11
12
Rise time(7)
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, MISO, SS)
tRM
tRS
100
2.0
ns
s
13
Fall time(8)
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, MISO, SS)
tFM
tFS
100
2.0
ns
s
1. Diagram numbers refer to dimensions in Figure 13-8. SPI Master Timing and Figure 13-9. SPI Slave Timing.
2. VDD = 3.3 V 10%; VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
3. Signal production depends on software.
4. Time to data active from high-impedance state
5. Hold time to high-impedance state
6. With 200 pF on all SPI pins
7. 20% of VDD to 70% of VDD; CL = 200 pF
8. 70% of VDD to 20% of VDD; CL = 200 pF
Technical Data
208
MC68HC705C8A Rev. 3
MC68HSC705C8A
MOTOROLA
MC68HSC705C8A
Temperature Range
Order Number
40C to +85C
MC68HSC705C8AC(1)P(2)
40C to +85C
MC68HSC705C8ACFN (3)
40C to +85C
MC68HSC705C8ACFS (4)
40C to +85C
MC68HSC705C8ACS(5)
40C to +85C
MC68HSC705C8ACFB (6)
40C to +85C
MC68HSC705C8ACB(7)
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
MC68HSC705C8A
209
MC68HSC705C8A
Technical Data
210
MC68HC705C8A Rev. 3
MC68HSC705C8A
MOTOROLA
Index
A
accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45, 154, 155, 158
addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
arithmetic/logic unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
B
block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
bootloader ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
C
C bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
condition code register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 47, 160
COP watchdog (non-programmable)
diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
in stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
timeout period formula . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
when clock monitor enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
73
73
66
66
73
64
64
63
71
71
63
66
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Index
211
Index
CPU
instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155, 158, 163
accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154, 155, 158
condition code register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 160
index register (X) . . . . . . . . . . . . . . . . . . . . . . . . 154, 155, 156, 158
program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157, 160
D
data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
E
electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .
power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
171
181
176
174
204
202
209
205
Technical Data
212
MC68HC705C8A Rev. 3
Index
MOTOROLA
Index
MC68HC705C8A Rev. 3
MOTOROLA
153
154
164
157
170
Technical Data
Index
213
Index
interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
reset/interrupt vector addresses. . . . . . . . . . . . . . . . . . . . . . . . . .
stacking order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
59
57
58
interrupts
external interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
internal function diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .
timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
port B interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
port B I/O logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
timer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51
52
52
50
50
53
53
54
55
50
49
56
55
IRQ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
J
junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
L
low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stop mode
non-programmable COP in stop mode flowchart . . . . . . . . . .
non-programmable COP watchdog in stop mode. . . . . . . . . .
programmable COP in stop mode flowchart. . . . . . . . . . . . . .
programmable COP watchdog in stop mode . . . . . . . . . . . . .
SCI during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stop/wait mode function flowchart. . . . . . . . . . . . . . . . . . . . . .
wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
non-programmable COP watchdog in wait mode . . . . . . . . . .
programmable COP watchdog in wait mode . . . . . . . . . . . . .
Technical Data
214
69
75
74
73
72
71
71
71
70
73
75
75
MC68HC705C8A Rev. 3
Index
MOTOROLA
Index
M
mask option registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23, 117, 118
MC68HSC705C8A (high-speed part) . . . . . . . . . . . . . . . . . . . . . . .
control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .
ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
programmable COP timeout period selection . . . . . . . . . . . . . .
SPI timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
201
204
202
209
202
205
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Index
215
Index
P
pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33, 78
data direction register A (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . 79
port A data register (PORT A) . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
port A I/O logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
port A pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33, 81
data direction register B (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . 82
port B data register (PORTB). . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
port B I/O logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
port B pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
port C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33, 85
data direction register C (DDRC) . . . . . . . . . . . . . . . . . . . . . . . . . 86
port C data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
port C I/O logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
port C pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33, 88
power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46, 157, 160
programmable options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
programming model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
PROM (EPROM/OTPROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
R
RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
registers
I/O register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
reset and interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . 59
RESET pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
clock monitor reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65, 67
with STOP instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Technical Data
216
MC68HC705C8A Rev. 3
Index
MOTOROLA
Index
62
66
67
63
63
65
62
62
61
ROM (bootloader) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
S
serial communications interface (SCI). . . . . . . . . . . . . . . . . . . . . . . 121
baud rate generator clock prescaling . . . . . . . . . . . . . . . . . . . . . 136
baud rate register (baud) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
baud rate selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
baud rate selection examples . . . . . . . . . . . . . . . . . . . . . . . . . . 138
during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
SCI control register 1 (SCCR1) . . . . . . . . . . . . . . . . . . . . . . . . . 130
SCI control register 2 (SCCR2) . . . . . . . . . . . . . . . . . . . . . . . . . 131
SCI data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
SCI data register (SCDR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
SCI I/O registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
SCI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
SCI operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
SCI receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
SCI status register (SCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
SCI transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
serial peripheral interface (SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
master/slave connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
multiple-SPI systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
pin functions in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
pin functions in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
serial clock polarity and phase . . . . . . . . . . . . . . . . . . . . . . . . . . 146
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Index
217
Index
SPI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI clock/data timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI control register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI data register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI I/O register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI I/O registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI status register (SPSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . .
141
146
149
149
147
142
148
148
142
151
73
74
71
72
71
71
69
70
T
TCAP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
TCMP pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
alternate timer registers (ATRH and ATRL) . . . . . . . . . . . . . . . . . 99
I/O registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
input capture registers (ICRH and ICRL) . . . . . . . . . . . . . . . . . . 100
output compare registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
timer control register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
timer I/O register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
timer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
timer registers (TRH and TRL). . . . . . . . . . . . . . . . . . . . . . . . . . . 97
timer status register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Technical Data
218
MC68HC705C8A Rev. 3
Index
MOTOROLA
Index
V
VDD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
VSS pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
W
wait mode
non-programmable COP watchdog in wait mode . . . . . . . . . . . . 75
programmable COP watchdog in wait mode . . . . . . . . . . . . . . . . 75
stop/wait mode function flowchart . . . . . . . . . . . . . . . . . . . . . . . . 70
MC68HC705C8A Rev. 3
MOTOROLA
Technical Data
Index
219
Index
Technical Data
220
MC68HC705C8A Rev. 3
Index
MOTOROLA
HOME PAGE:
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disclaims any and all liability, including without limitation consequential or incidental
damages. Typical parameters which may be provided in Motorola data sheets
and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including Typicals
must be validated for each customer application by customers technical experts.
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others. Motorola products are not designed, intended, or authorized for use as
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MC68HC705C8A/D