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Introductory CADENCE Information for ESE 555

Dr. Emre Salman

Electrical and Computer Engineering Department
Stony Brook University

1. If you have the recommended course textbook by Erik Brunvand, Chapters 2, 3, 5, and 7
contain sufficient information for our course regarding CADENCE design tools. Please
read these chapters.
2. We will use NCSU Cadence design kit (CDK) and process design kit (PDK) to design our
integrated circuits. These kits are already installed to the server in the CAD lab.
Familiarize yourself with this design kit and understand why we need CDK /PDK to
design and fabricate integrated circuits:
3. There are a few steps you need to follow before you can start Cadence. Go to CAD lab in
the first floor at Light Engineering Building. Login one of the workstations using your
ece username and password assigned to you by the department.
As the first step download file from the documents link on Blackboard. Put this
file in your home directory. If you previously had any cshrc files for Cadence (such as
.cshrc.cadence), delete them. Open a new terminal and follow the steps below
> pwd
(to make sure that you are in your home directory)
> ls -la
(to make sure that the file exists in your home directory)
> source (this step will automatically create a new directory named ese555,
setup Cadence for your account and start it)
4. Note that next time you need to start Cadence, you only need to run the following
> cd ~
> source .cshrc.cadence
> cd ese555
> virtuoso &
5. At this point, you need to read tutorials about how to use Cadence. As mentioned in
step 1, if you have the recommended textbook, read Chapters 2, 3, 5, and 7. The
following website from Tufts University has a useful manual. You should read and
understand Steps 2 to 9.
Another good tutorial is available at the University of Virginia website
Feel free to search for many other tutorials online. Cadence is a major toolset used by IC design
and VLSI engineers throughout the worlds, both in companies and academu.

6. We will use a 0.6 um CMOS technology. When you generate a new library in Cadence,
you need to attach it to this technology: HP 0.60u AMOS14TB. This technology is a 0.60micron, 3.3V CMOS n-well process containing 3 metal layers and 1 poly layer. Download
the design rules (MOSIS Scalable CMOS) for this technology (which you will use for the
layout) from the documents in Blackboard.
7. To perform simulation with active devices (such as MOS transistors), you need to add
the model files to the simulation environment (ADE SPECTRE). From the ADE window,
choose SETUP Model Libraries. The model files exist in the following path:
Under this path, you should choose the correct model files for both NMOS and PMOS
transistors of our technology: hp14tbN.m and hp14tbP.m
8. To perform DRC, LVS, and extraction during layout, you need to specify the correct path
for the rule files.
For DRC, rule file is /usr/local/cds/ncsu/techfile/divaDRC.rul
For LVS, rule file is /usr/local/cds/ncsu/techfile/divaLVS.rul
For extraction, rule file is /usr/local/cds/ncsu/techfile/divaEXT.rul
When you run extraction, it is important to make sure you set switches. On the
extraction window, hit the "Set Switches" button and select the options
"Extract_parasitic_caps" and "Keep_labels_in_extracted_view" using the CTRL key adn
the left mouse button. These should now appear in the Switch Names box. Click OK to
start the extraction and observe its progress in the icfb main window.
9. If you carefully follow the tutorials mentioned above, you should be all set to perform
your CAD assignments.