LAB MANUAL

ANALOG
ELECTRONICS

BY
AJAL.A.J
ASSISTANT PROFESSOR
ECE DEPARTMENT
MOB:8907305642
MAIL:professorajal@gmail.com

EXPERIMENT NO:1

FAMILIARIZATION OF CRO
AIM
To familiarize with the cathode ray oscilloscope and to measure voltage,current,frequency
and phase shift.
COMPONENTS AND EQUIPMENTS REQUIRED
CRO,function generator,capacitors and resistors
THEORY

The main use of a CRO is to obtain the visual display of an electrical voltage signal. If
the signal to be displayed is not in the voltage form, it is first converted to this form. The
signal voltage is then transmitted to the oscilloscope along a cable (usually a coaxial cable)
and enters the oscilloscope where the cable is connected to the scope input terminals. Often
the signal at this point is too small in amplitude to activate the scope display system (the
Cathode Ray Tube or CRT). Therefore, it needs to be amplified. The function of the vertical
deflection system is to perform such amplification. After suitable amplification, the input
signal is applied to the vertical deflection plates of the scope CRT. Within the CRT, an
electron beam is created by an electron gun. The electron beam is focused and directed to
strike the fluorescent screen, creating a spot of light, where impact is made with the screen.
The beam is deflected vertically in proportion to the amplitude of the voltage applied to the
CRT vertical deflection plates. The amplified input signal is also monitored by the horizontal
deflection system. This subsystem has the task of sweeping the electron beam horizontally
across the screen at a uniform rate. A sawtooth type signal (a triangular/ramp signal with long
time duration for the rising part of the ramp and very small time duration for the falling part)
is internally generated in a CRO as a time-base signal (sweep signal). This signal is amplified
and applied to the horizontal deflection plates of the CRO. Again, the beam is deflected
horizontally in proportion to the amplitude of the voltage applied to the CRT horizontal
deflection plates. The simultaneous deflection of the electron beam in the vertical direction
(by the vertical deflection system and the vertical deflection plates) and in the horizontal
direction (by the time-base circuitry and the horizontal deflection plates) causes the spot of
light produced by the electron beam to trace a path across the CRT screen.

Fig1. Internal components

The main part of the C.R.O. is a highly evacuated glass tube housing parts which generates a
beam of electrons, accelerates them, shapes them into a narrow beam, and provides external
connections to the sets of plates for changing the direction of the beam.
The main elements of the C.R.O. tube are shown in Figure 1.
1. K, an indirectly heated cathode which provides a source of electrons for the beam by
boiling them out of the cathode.
2. P, the anode (or plate) which is circular with a small central hole. The potential of P
creates an electric field which accelerates the electrons, some of which emerge from
the hole as a fine beam. This beam lies along the central axis of the tube.
3. G, the grid. Controlling the potential of the grid controls the number of electrons for
the beam, and hence the intensity of the spot on the screen where the beam hits.
4. F, the focusing cylinder. This aids in concentrating the electron beam into a thin
straight line much as a lens operates in optics.
5. X, Y, deflection plate pairs. The X plates are used for deflecting the beam left to right
(the x direction) by means of the ramp voltage. The Y plates are used for deflection
of the beam in the vertical direction. Voltages on the X and Y sets of plates determine
where the beam will strike the screen and cause a spot of light.
6. S, the screen. This is coated on the inside with a material which fluoresces with green
light (usually) where the electrons are striking.
As well as this tube, there are several electronic circuits required to operate the
tube, all within the C.R.O. along with the tube:
1. A power supply:This supply provides all the voltages required for the different
circuits within the C.R.O. for operation of the tube.
2. A sawtooth, or ramp signal generator which makes the spot move left to right on
the screen. External controls for this circuit allow variation of the sweep width, and
the frequency of the sweep signal. Because of the persistence of our vision, this sweep
is often fast enough that what we see on the screen is a continuous horizontal line.
3. Amplifiers for the internally generated ramp signal, and for the unknown signal
which we hook up to the C.R.O. for the purpose of displaying it.

4. Shift devices which allow us to control the mean position of the beam; up or down, or
left to right.
5. The synchroniser circuit. This circuit allows us to synchronise the unknown signal
with the ramp signal such that the resulting display is a nice clear signal like a
snapshot of the unknown voltage vs. time.

Fig2.front panel

Typical front-panel controls are,

1. Onoff switch.
2. INTENS. This is the intensity control connected to the grid G to control the beam
intensity and hence the brightness of the screen spot.
3. FOCUS allows you to obtain a clearly defined line on the screen .
4. POSITION allows you to adjust the vertical position of the waveform on the
screen.(There is one of these for each channel).
5. AMPL/DIV. is a control of the Y (ie. vertical) amplitude of the signal on the
screen.(There is one of these for each channel).
6. AC/DC switch. This should be left in the DC position unless you cannot get a signal
on-screen otherwise. (There is one of these for each channel).
7. A&B/ADD switch. This allows you to display both input channels separately or to
combine them into one.
8. +/- switch. This allows you to invert the B channel on the display.
9. Channel A input
10. Channel B input
11. X POSITION These allow you to adjust the horizontal position of the signals on the
screen.
12. LEVEL This allows you to determine the trigger level; ie. the point of the waveform
at which the ramp voltage will begin in timebase mode.

13. ms/s This defines the multiplication factor for the horizontal scale in timebase mode.
14. MAGN The horizontal scale units are to be multiplied by this setting in both timebase
and xy modes. To avoid confusion, leave it at x1 unless you really need to change it.
15. Time/Div This selector controls the frequency at which the beam sweeps horizontally
across the screen in timebase mode, as well as whether the oscilloscope is in timebase
mode or xy (x VIA A) mode. This switch has the following positions:
a) X VIA A In this position, an external signal connected to input A is used in place of
the internally generated ramp. (This is also known as xy mode.)
b) .5, 1, 2, 5, etc. Here the internally generated ramp voltage will repeat such that each
large (cm) horizontal division corresponds to .5, 1, 2, 5, etc. ms. or s depending on
the multiplier and magnitude settings.
16. The following controls are for triggering of the scope, and only have an effect in
timebase mode.
17. A/B selector. This allows you to choose which signal to use for triggering.
18. -/+ will force the ramp signal to synchronise its starting time to either the decreasing
or increasing part of the unknown signal you are studying.
19. INT/EXT This will determine whether the the ramp will be synchronised to the signal
chosen by the A/B switch or by whatever signal is applied to the EXT. SYNC. input.
(See 21 below.)
20. External trigger input.

MEASUREMENTS USING CRO

MEASUREMENT OF AMPLITUDE

1. Switch on the CRO. Obtain a sharply defined trace of a horizontal line on the screen
by adjusting INTENS and FOCUS knobs.
2. Adjust the Y position knob so as to make coincide with the centre line on the screen
by keeping the AC-DC switch in the ground position
3. Connect the function generator output to CRO using a test probe. Switch on the
function generator.
4. Count the number of divisions spanned by the signal from peak to peak. Multiply this
by the scale indicated by the VOLT/DIV knob. This gives the peak to peak amplitude
of the signal. Half of this will give the maximum value of the voltage
5. Repeat the above steps for various settings of VOLT/DIV knob
MEASUREMENT OF FREQUENCY
1. Obtain a sharply defined trace of horizontal line on the screen by adjusting the
INTENS and FOCUS knobs. Feed the signal whose frequency is to be measured, to
either of the channels using a probe and observe the signal on CRO
2. Adjust the TIME/DIV knob so as to see two or three cycles of the waveform. Count
the number of divisions in one cycle of the waveform. Multiply this by the time base
setting. This gives the period of the signal.
3. Reciprocal of the period will give the frequency of the signal
4. Repeat the above steps for various settings of TIME/DIV

RESULT
Familiarized with various functions of CRO and measured voltage,current ,frequency
and phase difference

EXPERIMENT NO:2

RECTIFIERS WITH AND WITHOUT SHUNT CAPACITORS

AIM
To study the performance of following rectifiers with and without capacitor filters and to
measure, Ripple factor, Rectification efficiency, and % regulation.
1. Half wave rectifier
2. Full wave rectifier
3. Bridge rectifier
COMPONENTS AND EQUIPMENTS REQUIRED:
Diodes,resistors,stepdown transformer,voltmeter,ammeter,bread board and CRO
PROCEDURE

1.
2.
3.
4.

Test all the components required.

Set up the circuit as shown in figure.
Observe the i/p & o/p wave forms.
Set up circuit in figure. By adjusting rheostat calculate percentage of regulation. Plot
the regulation characteristics.
5. Set up circuit in fig. Observe the o/p and calculate the ripple factor.

DESIGN
HALFWAVE RECTIFIER

DESIGN OF LOAD RESISTOR RL

RL=

where vs is the voltage across the secondary of the transformer and vDis the

voltage drop across the diode and ID is the current through the diode.
Take ID=10mA
Peak value of the voltage across the secondary of the transformer=Vrms
Voltagr drop across the diode vD=0.6v

Then RL=

= 789

Select RL=1k
Vrms=
Vdc=

Ripple factor r=

2
Vrms
Vdc2

Vdc

DESIGN OF CAPACITOR C
Let the allowed ripple factor of the capacitor input filter be 3%
We know the ripple factor r =
Power supply frequency f

1
2 3 fR L C

= 50Hz

We get C=234.6

Select C=220

,25V

FULL WAVE RECTIFIER

DESIGN OF LOAD RESISTOR RL
RL=

where vs is the voltage across the secondary of the transformer and vD is the

voltage drop across the diode and ID is the current through the diode.
Take ID=10mA
Peak value of the voltage across the secondary of the transformer=Vrms
Voltagr drop across the diode vD = 0.6v
Then RL=

Select RL=1k

= 789

DESIGN OF CAPACITOR C

Let the allowed ripple factor of the capacitor input filter be 3%

We know the ripple factor r =
Power supply frequency f

1
4 3 fR L C

= 50Hz

We get C=100

Select C=100

,25V

DESIGN OF BRIDGE RECTIFIER

DESIGN OF LOAD RESISTOR RL

RL=

where vs is the voltage across the secondary of the transformer and vD is the

voltage drop across the diode and ID is the current through the diode.
Take ID=10mA
Peak value of the voltage across the secondary of the transformer=Vrms
Voltagr drop across the diode vD = 0.6v
Then RL=

= 789

Select RL=1k
DESIGN OF CAPACITOR C

Let the allowed ripple factor of the capacitor input filter be 3%

We know the ripple factor r =
Power supply frequency f
We get C=100

1
4 3 fR L C

= 50Hz

Select C=100

,25V

CIRCUIT

0-6V

1N 4001

230V
AC
Mains

1K

a) Halfwave rectifier

IN4001
+

230V,50Hz AC

V0
100F
_
b)Halfwave rectifier with capacitor filter_-

1N4001
6-0-6V

230V.AC
1K
1N4001

c)Full wave rectifier

IN4001
+
1K

230V,50Hz AC

100F
V0
_
_-

IN4001

d)Full wave rectifier with capacitor filter

6-0-6V

41N4001

230v ac

1K

e)bridge rectifier

waveforms for halfwave rectifier

Input wave

Rectified wave

Ripple

waveforms for fullwave rectifier

Input wave
t

Output wave

V
Ripple
t

RESULT:
1.

The FWR and

HWR was designed and rectified wave forms were observed.
2.
Ripple factor
,%regulation and rectification efficiency was measured

EXPERIMENT NO:3

CLIPPING AND CLAMPING CIRCUITS USING DIODES

AIM
To design and set up different types of clippers and clampers

COMPONENTS AND EQUIPMENTS REQUIRED:

COMPONENTS
Diode
Resistors
Voltage source
Signal source
PROCEDURE:

SPECIFICATION
1N 4001
1K

1.

Test various components and wire up

the circuit.

2.

Observe the output on CRO screen.

CIRCUITS:
a) Negative clipper

1N4001

18vpp,100hz
1k

b) Positive clipper

1N4001

18vpp,100hz
1k

c) Parallel ve clipper

1N4001

18vpp,100hz
1k

d) Parallel +ve clipper

1N4001

18vpp,100hz
1k

e) Biased clipper

1N4001

3v
18vpp,100hz
1k

f) Biased negative clipper

1N4001

18vpp,100hz
1k

3v

1N4001

3v
18vpp,100hz
1k

h) Biased positive clipper

1N4001

18vpp,100hz
1k

3v

CLAMPING CIRCUITS

5V

a) Positive clamper

input wave

1N4001
V0

10V

b) Negative clamper

1N4001
V0

-10V

c) positive clamper at -3V

1N4001
V0
3V

7V

0V
-3V

d) Negative clamper clamping at +3V

1N4001
V0

3V

3V
0V
t
-7V

RESULT:
Designed various clippers clampers and observed the output

EXPERIMENT NO:4

RC COUPLED AMPLIFIER
AIM
To design an RC coupled amplifier for a gain of 50, to plot frequency
response and to find the band width.
COMPONENTS AND EQUIPMENTS REQUIRED:

COMPONENTS
Transistor
Resistors
Capacitors
DC voltage source
AC voltage source

SPECIFICATION
BC 107
820,220,6.8k,47k
10,2
10V

PROCEDURE:
1.

Test all the components

using multimeter.

2.

Set up the circuit as

shown in the fig.

3.

Apply the input signal

and adjust the port to get a gain of 50

4.

Observe the output

wave form on the CRO screen. Measure output amplitude for various
values of input frequencies.
5.
Plot the frequency
response and calculate the bandwidth.

OBSERVATION:
F (HZ)

VO

Log f

VO/VIN

G DB

CIRCUIT:

10V

RC=820

R1=47K

C2 2
C1

2
BC107
4.7K

R2=6.8K

RE=220
CE=10

DESIGN:

Assume that 10% of VCC drops across RE.

Assuming a bleeder current of 5IB,

Current through R2

From this equation, we get R1

Substituting in equation for Rin,

Taking f=1 kHz, we get C1

Taking f=1 kHz, we get CE

GRAPH:

Gain in
dB

3dB

7F

Log fL

log fH

RESULT
Designed RC coupled amplifier for a gain of 50. Plotted the frequency response
and calculated the band width. BW=...............

EXPERIMENT NO:5
OPAMP CIRCUITS DESIGN AND SET UP OF INVERTER, SCALE
CHANGER, ADDER, NON-INVERTING AMPLIFIER,COMPARATOR
AIM
To design and setup the following opamp circuits. Inverting amplifier, non inverting amplifier,scale
changer, adder, comparator

COMPONENTS AND EQUIPMENTS REQUIRED

IC 741, resistors, signal generator, CRO etc
1. INVERTING AMPLIFIER
The inverting amplifier configuration is formed by grounding the VP terminal and feeding the
signal into R. The resistor Rf which connects to the Vout to VN terminal providers negative feedback
connection. Suppose the opamp begins in the rest with Vin and Vout both equal to zero. If a +ve
voltage is applied to Vin , the VN terminal will rise in voltage, forcing Vout to become ve. The ve
value of Vout will act to return VN to zero. In equilibrium, Voutwill be just large enough vely to
balance the applied Vin, thereby establishing a virtual short condition at the opamp input terminals
with VN=VP=0. We have

2.NONINVERTING AMPLIFIER
Here the input voltage is applied directly to the VP terminal of the opamp. Negative feedback
is formed by the voltage divider of R1 and R2 which applies a fixed portion of the output to the VN
terminal. This negative feedback is responsible for circuits amplification properties. Suppose the
amplifier begins in an initial condition with Vinand Vout both equal to zero. If a positive voltage is
applied to Vin, the opamp will react to the rise in(VP-VN) by increase in Voutin the positive direction. At
the same time a fraction of the positively increasing Vout will be fed back to the VN terminal, thus
counteracting the increase in (VP-VN). Eventually an equilibrium condition will be reached in which
Vout forces (VP-VN) to a very small value that is just large enough to sustain the resulting value of Vout.

The fraction of Vout appearing at the VN terminal is

Since VN = VP

3.COMPARATOR
The open loop comparator circuits are also known as polarity indicators (circuits; figs 1&2).In the
circuit 1, the input voltage is connected directly across the Vf terminal with v terminal grounded.
Without feedback the range of Vin over which the operation is linear is negligibly small. The slightest
positive input when amplified by the opamps open loop gain forces Vout to its positive saturation limit.
Similarly, the slightest negative input forces Vout to its negative saturation limit. The circuit thus detects
the polarity of the input voltage and shifts Vout to either Vpos or Vneg accordingly. We can modify the
above zero crossing detectors to a voltage detector VR such that VR determines the point at which +
Vsat changes to Vsat and viceversa.

4.ZERO CROSSING DETECTOR:

It is a comparator that switches output between +Vsat and Vsat when the output
crosses zero reference voltage. For an inverting zero crossing detector ,the output is driven to Vsat
when the input signal passes through 0 to positive direction. Conversely, when the input signal passes
through zero to negative direction, the output switches to +Vsat. This circuit can be used to check
whether the opamp is in good condition.
5.INTEGRATOR
The circuit diagram of this simple integrator circuit need only the components resistance R
and capacitance C. With these components we get

ie,
It means that, the output voltage is the integral of the input. In order to limit the behavior of the
circuit to a particular region, we connect a resistance Rf in parallel with the capacitor Cf. Then the
resulting integrator circuit is called Lassy integrator.
6.DIFFERENTIATOR

The circuit diagram for the simple differentiator circuit consists of resistance Rf and capacitance C1.
With only these two components we get

This simple circuit has a tendency to oscillate. To avoid this we use a resistor Ri and capacitor Cf as
shown in the circuit diagram
CIRCUIT DIAGRAM
a)inverting amplifier

b)noninverting amplifier

c)comparator

Zero crossing detector:

Fig1 : Inverting

Threshold Detectors

Fig 2 : Non Inverting

Fig : Inverting

Fig : Non Inverting

EXPERIMENT NO:6

INTEGRATOR AND DIFFERENTIATOR

AIM:
To design and implement an integrator and differentiator using IC 741 and to plot the frequency
response.

COMPONENTS AND EQUIPMENTS REQUIRED:

IC 741, resistors, capacitors, breadboard, CRO, function generator etc

THEORY
The circuit diagram of this simple integrator circuit need only the components resistance R
and capacitance C. With these components we get

ie,

It means that, the output voltage is the integral of the input. In order to limit the behavior of the
circuit to a particular region, we connect a resistance Rf in parallel with the capacitor Cf. Then the
resulting integrator circuit is called Lassy integrator.

CIRCUIT DIAGRAM

Fig: An Integrator

DESIGN
fa=1Khz, fb=10fa=10Khz,
Let Cf=0.01uF
fa=1/(2*3.14*RF*CF); RF=1/(2*3.14*1K*.01uF)=15.9K
select 15K std.

fb=1/(2*3.14*R1*CF)
R1=1/(2*3.14*10k*0.01uF)=1.59K
Select 1.5K std.
PROCEDURE

1. Setup the circuit neatly on the breadboard.

2. Set the amplitude of the input signal to a suitable value.
3. Vary the input signal frequency and take the corresponding output values

Fig: Frequency Response of Integrator

Differentiator
The circuit diagram for the simple differentiator circuit consists of resistance Rf and capacitance C1.
With only these two components we get

This simple circuit has a tendency to oscillate. To avoid this we use a resistor Ri and capacitor Cf as
shown in the circuit diagram.

DESIGN
Transfer function
fH=

and fL =

fH=20khz and fL=1kHz

For C1= 0.01uF Rf = 15k
Cf =470pF
CfRf=R1C1
R1=820

PROCEDURE

1. Setup the circuit neatly on the breadboard.

2. Set the amplitude of the input signal to a suitable value.
3. Vary the input signal frequency and take the corresponding output values

Fig: Frequency response of differentiator

Input and Output waveforms

RESULT
Designed and setup a differentiator and integrator circuit and obtained the output waveforms

7.WIEN-BRIDGE OSCILLATOR

AIM
To design and set up a Wien-bridge oscillator with amplitude stabilization for a frequency of 1
kHz.

COMPONENTS REQUIRED
741IC, resistors, capacitor, diode, dc source

CIRCUIT DIAGRAM

DESIGN

The frequency needed is 1 kHz.

f0 = 1/2RC = 1 kHz

let C = 0.01uf, then

R= 15.91 kHz. ; R=15k

For sustained oscillations, 1+ ( Rf/ R1 ) = 3
Select R1 = 10 k and two 10 k resistors in series for Rf
For the amplitude stabilization circuit, 1+ (Rf+R2)/R1 = 3.3 => R2 = 3 k
R2=3.3 k
THEORY

The Wien bridge oscillator is a circuit for generating low frequency in the range of 10Hz to
about 1MHz. It is widely used in commercial generators. The basic network forms a bridge in the
feedback circuit. That is why it is called as Wien bridge oscillator. The Wien bridge consists of a
series RC circuit and parallel RC circuit as shown in figure
The circuit shown here uses both negative and positive feedback. Circuit behavior is strongly
affected by whether positive or negative feedback prevails. Here the feedback factor is found to be
of the form =1/*3+j(f/fo fo/f)];which is of band pass nature ,which has a maximum value of 1/3 at
f= fo =1/(2RC).At this point the loop phase is 0o .Hence by barkhausen criteria, oscillation will start if
A >1,i.e if the gain of the amplifier is greater than 3.Hence for the oscillation to start, initially gain
should be greater than 3 slightly and finally it should settle down at a gain of 3,where the amplitude
of oscillation stabilizes. For this we use an amplitude stabilization circuitry consisting of resistors and
diodes.
The frequency of oscillation can be varied by varying the capacitors simultaneously. These
capacitors are variable air-gang capacitors. We can change the frequency range of the oscillator by
connecting different values of resistors. The Wien bridge oscillator is therefore suitable for audio
frequency generators.

PROCEDURE

Check the op-amp. Setup the circuit on the breadboard as shown in figure. Ensure that opamp is operating as an amplifier of required gain. Observe the output on the CRO. Adjust the
potentiometer to get the sine wave without any distortion or clipping. The amplitude is almost equal
to Vsat.

Output
RESULT
Frequency of Oscillation =
Amplitude of Oscillation=

EXPERIMENT NO:8
SECOND ORDER LP AND BP/NOTCH FILTERS USING SINGLE OPAMP

AIM
To design and setup a second order lowpass and bandpass filters using single opamp
COMPONENTS REQUIRED
IC 741, Resistors, Capacitors, Function Generator, CRO etc.

THEORY
Since an R-C stage provides a first-order low-pass response, cascading two such stages
ought to provide a second-order response, and without using any inductances. Indeed, at low
frequencies the capacitors act as open circuits, thus letting the input signal pass through with H
1V/V. At high frequencies, the incoming signal will be shunted to ground first by C1 and then by C2,
thus providing a two-step attenuation; hence the designation second-order. Since at high
frequencies a single R-C stage gives
H

, the cascade combination of two stages gives

, 0 = (12)1/2 indicating an asymptotic slope of -40dB/dec. But if they are

implemented using passive components alone, it does not offer sufficient flexibility for controlling
the magnitude profile in the vicinity of =0. In fact, all passive filters yield Q<0.5. In order to
increase Q above 0.5, we go for active filters.

The circuit diagram for the second order filter is Sallen-key LPF is shown. Here, a positive
feedback is affected in the vicinity of =0 only, through a capacitor C1. At low frequencies, the
value of C1 is fairly large, to feedback a signal. And at high frequencies, the value of VP itself is very
small to have some signal at v0 to feedback. Thus we see that, the feedback is affected only near to
=0. Interchanging the capacitances and resistances, we get second order active high pass filter.
When Q=0.707 , the filters is said to have an almost ideal response. Such filters are known as
Butterworth Filters

A band pass filter passes a particular band of frequencies with zero attenuation and attenuates all
other frequencies. It is widely used as filters in analog and digital communication systems.

Delyiannis-friend band pass filter uses multiple feedback and hence it is a narrow band pass filter.
The classification of narrow band and wide band are made generally that Quality factor Q<0.5 for
wide band filter and Q>0.5 for narrow band filter. Maximum Q attainable by the band pass basic
circuit is limited by the maximum manufacturable ratio of resistance test(R2/R1).The maximum pole
Q is **R2/R1.Thus in the negative feedback topology, high pole Qs could be increased by
subtracting a term from the denominator. This subtraction can also be achieved in the negative
feedback topology in an analogous manner, by providing some positive feedback via a potential
divider

Transfer function H(s)

Where fp

DESIGN

For Sallen Key LPF

fp=1Khz, Qp=5;
fp=1/(2*3.14*RC)
For f = 1kHz
Use C = 0.01uF and R = 15k
Qp=1/(3-K);
For Qp=5
K= 2.8 = 1+R2/R1
Select R2=18K and R1=10K

For Butterworth LPF

and Qp =

Q P=
K= 1.586 = 1+ R2/R1
Use R2= 5.6k and R1 = 10k

DESIGN OF BPF

K=1+ R4/R3
For K=32; select R4=33k, R3=1k;
Qp=(R2/R1)/(2-(1/K-1)*R2/R1)
For Qp=10; then (R2/R1)=6.496;
Or R2=43.198*R1; fp=1/(2*3.14*C1*R1*R2)
For fp=1Khz, Let C1=0.1uf;
R1*R2 =1.592k, R1*R2=2534000, R1=2534000/R2;
R2=10k, R1=220

SALLEN KEY LPF FOR Q=5

BUTTERWORTH LPF

PROCEDURE

1.
2.
3.
4.

Set up the circuit for LPF neatly on a breadboard for Q=1/2

Vary the input signal frequency and note the corresponding output voltage values.
Repeat the above steps for Q=5 also.
Repeat the above four steps for second order HPF also.

Fig: LPF response

CIRCUIT FOR BPF

PROCEDURE

1.
2.
3.
4.

Setup the circuit after checking all components and op-amp.

Apply a 20mV input signal and observe the outout waveform.
Vary the input frequencies and note down the output voltage.
Load the frequency response.

Frequency Response:

9.SQUARE, TRIANGULAR & SAWTOOTH WAVE GENERATORS

AIM:
To design and set up a square with amplitude Vsat and triangular wave with amplitude
2.5V for a frequency of 1 KHz
To design and set up a triangular wave generator with amplitude +2.5 V and a frequency of 2
KHz
To design and set up a saw tooth wave generator with amplitude 2.5 V & for a risetime t1 =
2ms and fall time t2 = 0.2 ms
To design and setup a saw tooth wave generator with amplitude + 2.5 ms and for a rise time
t1 = 1ms and fall time of t2 = 0.1 ms

COMPONENTS AND EQUIPMENT REQUIRED:

IC 741 (2), resistors (5.6-(2), 15K, 1K, 56K), capacitors (0.1F), diode 1N4001(3), DC source (15 V),
bread board and CRO

THEORY:
The square wave triangular wave generator uses two operational amplifiers. One (A1)
functions as a comparator and other (A2) as an integrator. Comparator compares the voltage at
point P continuously with the inverting input that is at 0V. When the coltage at P goes slightly above
or below 0V, the output of A1 is at negative or positive saturation level respectively. At the output
of the comparator we get a square wave with amplitude Vsat. Suppose the output of A1 is at
positive saturation + Vsat. Since this voltage is the input of the integrator, the output of A2 will be a
negative going ramp. At time t = t1, when the negative going ramp attains values of Vramp, the
effective voltage at point P is slightly less than zero. This switches the output of A1 from positive
saturation to negative saturation. During the time when output of A1 is Vsat, the output of A1
increases in positive direction till it reaches +Vramp. At this point P is slightly above 0V, therefore the
output of A1 is switched back to positive saturation level +Vsat. The cycle repeats and generates a
triangular waveform. The frequency of triangular waveform is given by
peak amplitude is

. Peak to

In the triangular wave generator with amplitude +Vramp, a diode is connected in the
feedback path. The circuit has 2 op-amps. One A1 functions as a comparator and the other A2
functions as an integrator. Suppose output of A1 is at negative saturation Vsat. Since this voltage is

the input of integrator, its output will be a positive going ramp. Thus one end of the voltage divider
is at Vsat and the other end at positive going ramp. When the positive going ramp attains a value
Vramp the output of A1 switches from negative saturation too positive saturation. Since the output of
A1 is at positive saturation, then the diode is reverse biased. Output of A2 is a negative going ramp
and when the output of A1 reaches zero, the output of A1 switches from +Vsat to Vsat, and the cycle
repeats.
In a sawtooth wave generator, the rise time is higher than fall time or vice versa.
A triangular waveform generator can be converted to a sawtooth by a diode resistor network shown
in the circuit. During positive saturation at output of A1, upper diode D1 conducts and R3 will be
effective. The current for charging the capacitor will be high if R3 is effective because R3< R3. Hence
the output of A2 which is a negative going ramp with steeper slope and hence the fall time of a
sawtooth wave decreases. Similarly during negative saturation at output of A1, upper diode D1 is
everse biased and lower diode D2 conducts and R3 will be effective. The current through the
capacitor will be less because R3> R3. Hence the output o A2 is a positive going ramp with less
steeper slope. Hence the rise time of the sawtooth wave increases.
In a sawtooth wave form generator with amplitude +Vramp , a diode is connected in the
feedback path. It consists of 2 op-amps. One (A1) functions as a comparator and the other (A2)
functions as an integrator. Consider the instant at which the output of A1 is at negative saturation
Vsat; then the lower diode D2 conducts and R3 will be effective. The output of A2 will be a positive
going ramp. When the output of A2 goes reaches of +Vramp the effective voltage at P is slightly less
than zero. This switches the output of A1 from negative to positive saturation. When output of A1 is
+Vsat , the diode in the feedback path is reverse biased and upper diode D1 conducts. Therefore the
output of A2 is a negative going ramp and when the ramp reaches zero, the output of A2 switches
from +Vsat to Vsat and the cycle repeats.

CIRCUIT
DIAGRAM

DESIGN
Vramp =Vsat R2/R3
Let Vramp= 6V ,

Vsat= 13V

Then for R2= 1K , R3=

= 2.6K

Select 2.7K std .

Also time period T =

For T = 0.1 ms
Let C = 0.01 F, then R1 =

= 6.75 K Select 6.8K std

PROCEDURE:

Set up the circuit of square cum triangular wave generator on the breadboard after
checking all components and op-amps. Observe the square wave output of the first op-amp. Note
down the amplitude and frequency of the square wave Observe the output of the second op-amp
which is a triangular wave Note down the amplitude and frequency of the waveform Set up the

triangular wave generator for amplitude +Vramp , after checking all components and op-amps Observe
the triangular wave form at the output of the second op-amp Note down the amplitude and
frequency of the triangular waveform generator Set up the circuit of the saw tooth generator on the
breadboard after checking all the components and op-amp Observe the sawtooth waveform at the
output of the second op-amp. Note down the amplitude, time period of rise time & time period of
fall time Set up the circuit of sawtooth wave generator with amplitude +Vramp, after checking all the
components and op-amp. Observe the output waveform at the output of the 2nd op-amp Note down
the amplitude and time periods of rise and fall times

Vsawtooth

RESULT:
A square wave generator cum triangular waveform generator was designed and setup for square
wave amplitude = Vsat, Triangular wave amplitude = 2.5V, Frequency =2 KHz
Observed amplitude of the square wave =
Observed amplitude of the triangular wave

Observed frequency

A triangular wave generator is designed and setup for an amplitude +2.5 V and a frequency of 2 KHz

Observed amplitude of triangular wave =

Observed frequency

A saw tooth wave generator was designed and setup for an amplitude of 2.5 V, rise time of 2ms and
fall time 0.2 ms
Observed sawtooth amplitude

Observed rise time

Observed fall time

A sawtooth wave form generator was designed and setup for an amplitude of 2.5V, rise time t1 =1
ms and fall time t2 = 0.1 ms
Observed sawtooth amplitude

Observed rise time

Observed fall time

10. MONOSTABLE MULTIVIBRATOR USING IC 555

AIM
To design and setup a monostable multivibrator using 555 timer for a pulse-width of 1ms

COMPONENTS REQUIRED
555 IC, resistors, capacitors, dc source

CIRCUIT DIAGRAM

DESIGN

Take VCC=10 V
Pulse width T = 1.1 RC = 1ms
Let C = 0.1 uf, then R = 9.09 k, select standard value of 10 k
Trigger RiCi=0.016 Tt Take Tt =3ms
For Ri=5.6K, then Ci=0.01 uF

THEORY
The circuit diagram is shown in fig. Here the resistor R and the capacitor C are external to
the chip and their values determine the output pulse-width. The three equal resistance R
inside the chip establish the reference voltages 2Vcc/3 and Vcc/3 for comparators C 1 and C2
respectively.
Before the application of the trigger pulse Vt, the voltage at the trigger input is high which
is equal to Vcc.With this high trigger input , the output of the comparator C 2 will be low
causing the FF output to be high. Now the discharge transistor Q1 will be saturated and the
voltage across the timing capacitor C will be essentially zero.

At t=0, application of trigger V t, less than Vcc/3 causes the output of the comparator C2 to
be high. This will set the FF with now low. The discharge transistor will be turned off.
Now the timing capacitor charges up towards Vcc via resistor R, with a time constant =RC
.When this charging voltages reach the threshold level of 2Vcc/3,comparator C1 will switch
states and its output voltage will now be high. This causes the FF to reset so that will go
high. The high value of turns on the discharge transistor Q1.The time duration of quasistable state is given by the equation, T=1.1RC seconds
PROCEDURE
1. Set up the circuit after verifying the condition of the IC using analog IC tester.
2. Use positive pulses of amplitude Vcc and frequency 300Hz as the trigger.
3 .Observe the waveforms at pin numbers 3 and 6 of the chip.
4. If pulse generator isnt available, use square wave generator along with a differentiator circuit

Output waveforms:
Trigger pulses

Output waveform:

RESULT

Designed and set up a monostable multivibrator and observed it output waveforms

11. PHASE LOCKED LOOPS

AIM:

1. To determine the lock range and capture range of a given PLL using NE 565
2. To design and setup a frequency multiplier using PLL chip to multiply by a factor of 2

COMPONENTS AND EQUIPMENTS REQUIRED:

IC 565, IC 7490, Resistors(4.7K and 47k), capacitors (0.001F), diode OA79, transistor BC 107, DC
sources (
signal generator, breadboard and CRO.

THEORY

PLL mainly consists of a phase detector, a low pass filter and a voltage controlled
oscillator. Phase detector provides a dc voltage proportional to the phase difference between the
input frequencies. Low pass filter removes high frequency noise. The dc voltage controls the VCO
frequency. VCO frequency is fed back and compared with input frequency and automatically gets
itself equal to the input frequency. Free running frequency of the VCO is
Refrring to the graph,

Lock range

Capture range

fL1

fC1

fo

fC2

fL2

When input frequency is less than fL1, PLL is neither in lock mode or capture range. It will be
in the free running range. When input frequency reaches fC1, VCO frequency becomes equal to the
input frequency. In other words VCO captures the input frequency. If input increases in frequency
VCO follows the input up to the limit of fL2. There after the VCO remains in its free running state. If
input frequency is reduced, VCO frequency becomes equal to input frequency only at fC2. If input is
further reduced VCO frequency follows input frequency only up to the limit of fL1. Lock range fL2 to fL1
can be defined as the range of frequencies in which PLL maintains lock with input frequency. Capture
range fC2 to fC1 is defined as the range of frequencies in which PLL acquires a lock with input
frequency. 7490 is a decade counter designed as a divide by 2 network. Since the output of the
counter is lock with the input frequency, the VCO output frequency is twice the input frequency.

CIRCUIT DIAGRAM

DESIGN
fo= 1.2/4R1C1
For fo=60kHz, C1=0.001F gives R1=4.7k

VCO Free running Waveform:

PROCEDURE:

1. Set up the circuit of the phase lock loop and observe the free running frequency of the
PLL by disconnecting the connection between 4th an 5th pins.
2. Connect the 4th and 5th pins. Apply an input signal and calculate the lock and capture
range.
3. Set up a divide by 2 network using a 7490 counter IC
4. Observe the input and VCO output waveforms.
RESULT :
Lock range of the PLL is determined.
Center frequency

= _______________ hz

Lock range

=__________ to ___________ =_________kHz

Capture range

=__________ to ___________ =_________kHz

Frequency multiplier is designed and set up using a PLL

12. APPLICATION OF PLL

AIM
To design and set up a frequency multiplier using PLL chip to multiply the input frequency
by a factor of two
COMPONENTS REQUIRED
IC 565, 7490, Resistors, Capacitors, Diode, Transistor, DC source, Signal generators

THEORY
Frequency synthesis is one of the application of PLL. A frequency divider divides the
frequency by a factor of N. Since the divided frequency is in lock with the input frequency, VCO is
running at the multiple of input frequency.

CIRCUIT DIAGRAM

DESIGN
fo= 1.2/4R1C1
For fo=60kHz, C1=0.001F gives R1=4.7k
Transistor selection
For BC107, IC=1mA
R2=(VCC-VCEsat)/(IC+I)=(5-0.3)/1mA=4.7k
R3=(VB-VBEsat)/IB=(5-0.7)/1mA/100=47k

PROCEDURE

1. Set up the circuit of PLL and observe the free running frequency of PLL by
disconnecting the connection between pins 4 and 5
2. Connect 4 and 5 pin
3. Set up the divide by two counter using 7490 IC
4. Observe the VCO output and input

RESULT
A frequency multiplier was designed and set up using PLL chip to get the input frequency multiplied
by two