DESIGN OF NANO ELECTRON BASED MEMORY
K. Loganathan, Mr. K. Rathnakannan,
PG Student, Lecturer
CEG, Guindy, Anna University.
Email: loguest@gmail.com
Abstract
The need for fast switching and
low power consumption is the main goal
of semiconductor technology. According
to Moor’s law, the number of transistors
on a chip roughly doubles every eighteen
months. Advances in integrated circuit
technology have been based mostly on
CMOS (Complementary Metal Oxide
Semiconductor) technology operating on
the basis of binary logic. Major
problems in present-day LSI
Technology, such as increased power
consumption, interconnects delay,
limited integration density and device
scaling limits cannot be addressed
simply by improving the conventional
CMOS technology. Nano electron
device technology has promising
capabilities to replace CMOS transistors
in semiconductor applications, in
computing system the memory is the
primary requirement for hardware
design. Single-electron Transistor
memory cells usually have extremely
poor driving capabilities so that direct
application to practical circuits is almost
yet impossible. One possible solution to
overcome this problem is to build hybrid
circuits consisting of single electron
transistors and CMOS interfaces. Using
hybrid circuits, design static random
access memory (SRAM) cell and
implement a multi-valued logic.
Key terms- complementary
metal oxide semiconductor, large scale
integration, single electron transistor,
multiple valued logic, static random
access memory.
1. INTRODUCTION
Emerging nano electron device
especially have a possibility of achieving
high functional density and extremely
low power operation in principle.
Whenever designing the memory, it
should be smaller in size and easy to
access data. The memory technology
which is in use today consumes more
power for storing small amount of data.
So it is essential to design a memory
which is smaller in size, having fast
access time and consumes less power. A
Nano electron device addresses these
issues and which can operate at room
temperature. Using hybrid circuits,
design static random access memory cell
and implement a multi-valued logic
.Using multi-valued logic to achieve
higher functionality with lower
hardware.
2. SET /Hybrid CMOS-SET
A SET can be defined as “a
system of three electrodes (drain, source
and gate) in which the source and drain
are connected via two tunnel junctions
and a single electron island between
them. Voltage to gate changes electro
static potential of island and hence, the
rate of electron transport between source
and drain” symbol of SET is shown in
bellow [1].
Fig.1 SET symbol
The voltage biased, voltage
controlled SET transistor circuit consists
of two SET junctions TJ1 and TJ2 with a
capacitor Cg connected to island [2].
Two external sources are applied to the
circuit. One source forms the voltage
source SET junction loop, consisting of
us, TJ1 and TJ2. The other source
controls charge distribution among the
junctions via the capacitor Cg and is able
to control the electron flow through the
voltage source SET junction loop. This
device is able to amplify signals in the
voltage domain and was therefore called
a SET transistor.R1, R2, and R3 is
expressed with a cosine function to
describe the Coulomb oscillation and
D2, D3, and Vp is expressed to describe
the Coulomb staircase. Symmetric
features of the drain-source current-
voltage (Ids-Vds) characteristics are
incorporated with two branches
consisting of the combination of
resistors, diodes, and voltage sources.
They are denoted by R2/D2/V2 and
R3/D3/V3, respectively. The directions
of D2 and V2 are opposite to those of
D3 and V3 to have the current flow in
both positive and negative drain-source
bias. The charging energy, periodically
changing as a function of the gate bias,
is included in R1, R2 and R3 where the
cosine of the gate bias is used. They are
expressed as follows;
R1 (Vg) = CR1+ CR2 cos (CF1. Vg)
R2 (Vg) = R3 (Vg) = CVp/CI2-
2CVp/R1 (Vg)
The parameters, CF1, CVp, CI2,
CR1, and CR2 are used to fit the current-
voltage Characteristics at various gate
biases. The simulated I-V characteristics
of an SET at various gate biases shown
in.
Fig.2 SET output at various
temperature
The parameter values, C1=1E-
18, C C2=1E-18, R1=1E5, R2=1E5,
CG1=1E-18, CG2=1E-18
Single-electron transistors
(SETs) have recently attracted much
attention because of their nano feature
size, ultra low power dissipation, unique
Coulomb blockade oscillation behavior,
and CMOS compatible fabrication
process. However, a complete
replacement of CMOS by SET is quite
unlikely in near future due to some of its
intrinsic limitations e.g., very low
current drive, higher sensitivity to
temperature variation because of the
operation of MOS transistors in the deep
sub threshold region and high off-state
thermal leakage current due to the low
island capacitance charging energy in
present technology. It also appears that
CMOS and SETs are rather
complementary [4]. For example, SET
provides low-power consumption and
unique Coulomb Blockade oscillations,
while CMOS has advantages such as
high-speed driving and voltage gain,
which can compensate for the SET’s
intrinsic drawbacks.
Fig.3 SET/ CMOS Hybrid circuit
3. Multiple valued logic
The SET based memory is
suffers from two major limitations: 1)
low current drive (nA) due to the series
connection of SET and MOSFET and 2)
higher sensitivity to temperature
variation because of the operation of
MOS transistors in the deep sub
threshold region. In this paper,
combining the virtues of both SET and
CMOS devices, we propose to use our
new hybrid elementary circuit cell,
called SETMOS, which exhibits similar
Coulomb blockade oscillations as a
traditional SET but offers much higher
current driving ability, to build the
fundamental modules of quaternary logic
(e.g., literal gate). We have found that
the proposed SETMOS architectures
could be much faster and less
temperature-sensitive than the
previously architecture. This paper
mainly demonstrates the fact that the
SETMOS device Characteristics could
be extremely useful for implementing
MV logic in memory systems. The
SETMOS logic gate family is useful for
realizing the literal functions with
periodic transfer characteristics. MV
logic functions of a single variable can
be realized by adding the out put of
literal functions .As MV logic uses
higher radix , it can provide more
information for each line and thus can
help to reduce the number global
interconnects and pin outs drastically.
MV memory cell can reduce the number
of transistors and interconnections.
Figure.4 shows a schematic of a periodic
literal circuit, which consists of a SET, a
MOSFET. The MOSFET with a fixed
gate bias of Vgg is used to keep the SET
drain voltage almost constant at Vgg-
Vth, where Vth is the MOSFET
threshold voltage. The Vgg- Vth is set
low enough to sustain the Coulomb
blockade condition. In addition, the
MOSFET works as a cascade device and
keeps the output resistance of the circuit
high. When the increasing drain current
crosses the load line of, the output
voltage Vout switches very sharply from
high to low. On the other hand, when the
decreasing drain current crosses the load
line, the output voltage switches from
low to high. The output Vout becomes
logical “1” when the SET is off and
Vout becomes “0” when the SET is on.
The periodic waveform of the output is
shifted by control gate potential.
Fig. 4 SET periodic literal
 Fig. 5 SET periodic literal output
Fig.6 SET parallel gate
Fig.7 SET parallel gate output
Fig.7 SET literal output
4. Multi-valued static random access
memory Cell
A new multi-valued static
random access memory (MVSRAM) cell
with a hybrid circuit consisting of a
single-electron transistor (SET) and
MOSFETs is proposed [5]. Cell structure
consisting of one SET, three MOSFET.
Compared with the conventional SRAM,
this cell has the advantages of a multi-
valued capability; allow less number of
elements in the cell, and a high write
speed to very small storage node (SN).
The other cell structure with the fast
read-out scheme has been proposed to
improve the slow read-out Operation of
the original MVSRAM cell due to a
relatively large bit line (BL) capacitance,
in which voltages at the SN are
converted to current levels. However,
this cell structure has the disadvantage of
increasing the memory area because it
needs four lines: two column lines (BL
and SL) and two row lines (WL and
SWL). To decrease memory area, it is
necessary to reduce the number of lines
in the cell. We propose a new
MVSETMOS-SRAM cell with an
SETMOS hybrid circuit, which has a
much smaller. Owing to the reduced
number of lines. Proposed
MVSETMOS-SRAM cell structure with
an SETMOS hybrid circuit is shown in.
Fig.8 MVSRAM cell
Fig.9 MVSRAM cell array
The basic concept for write, read
operations of the proposed cell is first
converting voltage levels in SN to
current levels by using M4, but only one
data line (one BL without the SL) is
needed for read, write operations. The
memory area of the proposed cell is
much smaller than that of the SRAM cell
with the fast readout scheme in owing to
the reduced number of lines (three lines:
one BL, one WL, and one SWL). The
area of the proposed cell may be much
larger than that of the SRAM cell with
the fast read-out scheme in because one
extra MOSFET M6 is needed to control
the source voltage, VS, of M4, but the
penalty area of M6 is very small, as the
source of M4 in each cell of the array
block is connected with the drain of M4
outside the array block. During the write
operation, SC has to be ‘low’ to turn off
both M4 and M6. Both WL and SWL
are switched to ‘high’ to turn on bothM3
and M5. A multi-valued logic data
applied to BL. The logic data is stored in
SN through the pass transistors M3
andM5. There is no current path through
M4 and no extra power consumption
since the source control transistor M6 is
turned off at this time. After the logic
data in SN is completely written, both
WL and SWL are switched to ‘low’, and
then the logic data stored in SN is
maintained at the stability point since
M5 is turned off.BL is pre charged to
ground at then the write operation is
finished. During the read operation, WL
has to stay ‘low’ to turn off M5. At t4
timing, both SWL and SC node voltage
of theM6 transistor are switched to
‘high’ to turn onM3, M4, and
M6.Voltage levels in SN are converted
to currents through M4 because M3, M4,
and M6 are all turned on, and then the
currents are transferred to BL through
M3, M4, and M6. The currents are then
sensed by the peripheral circuits. At
particular time all signals are switched to
‘low,’ and then the read operation is
finished.
5. CONCLUSION
This paper demonstrates the
possibility of the exploitation of unique
Coulomb blockade oscillation of SETs
for implementing some basic building
blocks of MV logic in memory. By
combining the properties of SETs and
traditional CMOS devices, we have References:
developed a CMOS-SET hybrid
architecture named MVSETMOS that [1] A.K. Abul El-Seoud, M. El-banna,
offers Coulomb blockade oscillations and M.A. Hakim,”A simple model for
and much higher current levels than the single-electron transistors” proc .IEEE
traditional SETs. The Coulomb blockade 0-7803-8294-3/04/$20.00 2004
oscillation characteristics are exploited
to realize the MV literal gate. The [2] Yun seop Yu,” Macro modeling of
periodic NDR effect is used to design an single-electron transistors for efficient
MV hysteresis loop architecture, which circuit simulation”IEEE Trans. 0018-
works as MVSETMOS SRAM. The 9383/99$10.00 1999
functionalities of the proposed
MVSETMOS SRAM logic and memory [3] Katsuhiko Degawa and Takafumi
cells are fully verified by SET model Aoki, Tatsuo higuchi, “A single-
SPICE simulations systems. The Electron-transintor logic gate family and
previously reported CMOS-SE based its application”proc.IEEE 0195-623x/04
SRAM cell circuit needs two data lines, $20.00 2004
one BL for write operations and one SL
for read operations, to improve the speed [4] Y. S. Yu, Y. I. Jung and J. H.
of the read-write operation, but the Park,”Simulation of Single-
proposed cell has only one data line for electron/CMOS Hybrid Circuits Using
read, write operations, resulting in a SPICE Macro-modeling” School of
memory area that is much smaller than Electrical Engineering, Korea
that of the previous cell, without any University, Seoul 136-701 Dec 1999
reduction of read-out speed.
MVSETMOS architectures are found to [5] Y. S. Yu, Y. I. Jung and J. H. Park,
be much faster and less temperature- “A Two-Bit-per-Cell Content-
sensitive than previously hybrid CMOS- addressable Memory Using Single-
SE based circuits. Electron Transistors” School of
Electrical Engineering, Korea
University, Seoul 136-701 proc IEEE
0195-623X/05 $ 20.00