Journal of Information, Control and Management Systems, Vol. 5, (2007), No.

225

EMBEDDED COMMUNICATION SYSTEM

IMPLEMENTED IN FPGA
Oldich KOV, Juraj MIEK
University of ilina, Faculty of Management Science and Informatics,
Slovak Republic
e-mail: kovar@frtk.fri.uniza.sk, micek@frtk.fri.uniza.sk
Abstract
The design, implementation and verification of the communication system are
presented in this article. The communication system manages data transfer
between PC computer and Digital Imaging System (DIS) special periphery. As
a control unit of the communication system the 8-bit soft-core PicoBlaze
microcontroller was selected. The customize Serial converter (Scon) and
Parallel converter (Pcon) peripheral cores of the communication system was
designed with the aim of the optimum utilization of the Xilinx XC3S200 FPGA
architecture components.
Keywords: Communication system, Pico-Blaze microcontroller, Customize
peripheral cores, Scon periphery, Pcon periphery DIS periphery, Application
System Integrated Circuit (ASIC), Macro Module system.
1

INTRODUCTION
The special analog / digital ASIC Digital Imaging System (DIS) periphery was
developed for the X-ray intensity to digital information conversion. Periphery was
developed for the diagnostic purposes (clinical-mammography, angiography; material
science-diffractometry). The simplified structure of ASIC is depicted in the figure 1.
DIS periphery has 64 analog input channels. X-ray intensity of the individual
input channels is converted into digital form. Digital information is accessible through
interface that is indicated on the right side of the figure1. The interface will be
described in more detail in next part of this article. Eight DIS peripherals are grouped
into Macro Module to gain considerable more image date. Macro Module architecture
is depicted in the figure 2.
Macro Module contains eight DIS peripheries. Each of them is individually
addressed. Data from DIS peripherals can be read individually. Data are transmitted
simultaneously on the 8 output serial channels and they are synchronized by Strobe
signal.

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DIGITAL IMAGING SYSTEM

(X-RAYS PHOTON COUNTING )
ANALOG
PART

DIGITAL
PART

8 OUTPUT INDVIDUAL
SERIAL DATA
CHANNELS

IN 0

64 READOUT
CHANNELS
X-RAY INTESITY

IN 1

STROBE
I/O
BLOCK
CHARGE
AMPLIFIERS

COMMAND

COUNTERS
RESET

IN 63

CLK

Figure 1 Simplified structure of ASIC DIS periphery

8 SERIAL
DATA
CNANNELS
CLK
COMMAND
RESET

1
1
1

CLK
COMMAND
RESET

8 DATA
DIS 0
000

CLK
COMMAND
RESET

8 DATA
DIS 1
001

CLK
COMMAND
RESET

DIS 2

INPUT
SIGNALS

RESET

1 STROBE
8 DATA

DIS 6
110

CLK
COMMAND

1 STROBE
8 DATA

DIS 5
101

CLK
COMMAND
RESET

1 STROBE
8 DATA

DIS 4
100

CLK
COMMAND
RESET

1 STROBE
8 DATA

DIS 3
011

CLK
COMMAND
RESET

1 STROBE
8 DATA

010

CLK
COMMAND
RESET

1 STROBE
1 STROBE

1 STROBE
8 DATA

DIS 7
111

1 STROBE

MACRO MODULE

Figure 2 Macro module architecture

OUTPUT
SIGNALS

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227

1.1 Short survey of DIS peripheral digital interface

Each DIS periphery ASIC chip is controlled using commands send to it via serial
link. The length of the command code is constant 22 bits. The structure of the
command is depicted in the figure 3.
header-4bits

address -4bits

command code-3bits

data -11bits

Figure 3 Format of the command

Since the transmission of the commands is synchronous, command signals needs
to be synchronized with clock. Rise edge of the clock signal is an active edge. Example
of command and clock sequence is illustrated in the figure 4.
Clock
Data

Figure 4 Command transmission timing

Appropriate DIS periphery transmits data chain as a response to the command on
the eight independents serial data lines. Format of this data on the series line is shown
in the figure 5.
header-7bits

channel 7-44bits

channel 6-44bits

channel 0-44bits

Figure 5 DIS periphery transmitted data format

Transmitted data stream from DIS periphery is synchronized with strobe signal,
which has exactly 359 periods. Transmitted data are stable on the falling edge of the
strobe signal. Example of transmitted data sequence is shown in the figure 6.
Strobe
Transmitted data

Figure 6 Data transmission timing

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Embedded Control Communication System Implemented in FPGA

THE REQUIREMENTS ON CONTROL COMMUNICATION SYSTEM

DIS peripherals have to be connected to the PC for the following digital image
processing of the scanned picture data. For reason of the interfaces incompability
between DIS periphery and PC, the interface transformation is necessary. The control
communication system had to be designed to accomplish connection between DIS
peripherals and PC. Following conditions on the control communication system were
defined:
- Connection to the PC through serial interface (RS 232),
- 10Mbps bit rate of the serial communication between DIS peripherals and
control communication system.
The design of the control communication system was our task.
3

OVERALL ARCHITECTURE OF THE COMMUNICATION SYSTEM

Architecture of the control communication system is depicted in the figure 7.
Controller of the communications is implemented into FPGA and consists of three
subsystems:
- Customized Pico-Blaze processor,
- Transmitting periphery Scon,

- Receiving periphery Pcon.

4

SCON PERIPHERY ARCHITECTURE

Scon periphery converts parallel 8 bits data from the processor into 22 bits serial
data stream compatible with DIS periphery command code format. Conversion has
three cycles of the transmission of 3 bytes from the output port of the processor into
registers R0, R1, R2 22 bit data stream is formed into shift register ShR and
immediate is send into the appropriate DIS periphery. Blocks indicate as CM3 and
CM4 are control elements that insure correct function of Scon periphery. Architecture
of the Scon periphery is depicted in the figure 8.
The way of synchronization is mentioned in right part of the figure 8. Signal
LOAD starts sending of the 22 bits control word into DIS periphery.

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Journal of Information, Control and Management Systems, Vol. 5, (2007), No. 2

48MHz
CLK

FPGA XC3S200

CUSTOM PERIPHERALS

DCM
CLK
COMMAND
RESET

Scon

DIS 0

70MHz
CLK

PicoBlaze
Processor

Din
0-7
1
SERIAL
DATA
LINES

DIS 1

Pcon

STROBE

I/O PORTS,
CONTROL SIGNALS

DIS 7
MACRO MODUL
USB
CONFIG

JTAG
CONFIG.

UART

PC

Figure 7 Overall architecture of the communications system

LOAD SYNCHRONIZATION

RESET
CM3

WR

CLK

CE0CE1CE2

8 D(7:0)

WSA

CE0
CLK

CE2 WR

CE1
R0

CM24

CE2
R1
8

LOAD
0

ShR

LOAD

R2

WSA
D

CE2
WR

8
Command data
serial out

CLK

Figure 8 Architecture of the Scon periphery

CE
CLK
R

LOAD
D

Q
CLK

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Embedded Control Communication System Implemented in FPGA

4.1 Scon periphery post route simulation result

The correct function of Scon periphery was verified by post route simulation. In
the figure 9 are depicted waveforms of individual signals. Data bytes A0, F0, 0F are
written in three write cycles (wr signal). The position of the cursor labels start of data
bytes transmission in serial form (output so). Data are transmitted in the order 0F, F0,
A0.

Figure 9 Post route simulation result

5

PCON PERIPHERY ARCHITECTURE

Architecture Pcon periphery is depicted in the figure 10. Pcon periphery consists
of eight 359 bits shift registers that receive simultaneously serial data streams from
selected DIS periphery Di0-Di7 channels. Single bits of data streams are written into
shift registers on the falling edge of the STROBE signal. Signal MEM FULL is
generated when 359 bits are received. At this moment microcontroller Pico Blaze starts
to read subsequently content of shift registers through S-P REG.
CE0
CE1

CLK
Di0
pB PREP

CLK

pB CLK

SHIFT REGISTER 359 Bitov

Q1

CE1
MUX

RES CNT

S-P REG
D(7:0)

CLK
Di7
MEM FULL

pB Data_out

CE7

Di1

CNT 359

WR
D(7:0)
REG

CE0

BUFG
MUX

STROBE

SHIFT REGISTER 359 Bitov

Q0

3
SHIFT REGISTER 359 Bitov

CE7

Q7

pB Data_in
pB ADDRESS

Figure 10 Architecture of the Pcon periphery

pB CLK

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231

Block indicates as REG generates enable signals CE0 - CE7. Shift registers are
built from SRL16E FPGA components. The utilization of SRL16E components is
highly effective with respect to the FPGA resources saving.
6

CONCLUSIONS
Communication system was implemented into the FPGA training board with
XC3S200 circuit. All components of the communication system was designed with
VHDL utilization.
The PicoBlaze microcontroller core is totally embedded within the target FPGA
and requires no external resources. The PicoBlaze microcontroller is extremely
flexible. The basic functionality is easily extended and enhanced by connecting
additional FPGA logic to the microcontrollers input and output ports. The PicoBlaze
peripheral set can be customized to meet the specific features, function, and cost
requirements of the target application.
Scon and Pcon peripherals are original digital systems that meet interface
requirements towards the DIS periphery and PC.
Implemented communication system was successfully tested in T&N System firm
in real conditions.
REFERENCES
[1]
[2]
[3]

T&N System firm publication

http://www.xilinx.com/support/techxclusives/SRL16-echxclusive.htm
(18.3.2001)
evk, P.: Implementation design of pulse coded neural network neuron into
field programmable gate array device, Applied Electronics 2006 Plze, 2006

Acknowledgement
This work has been supported by the grant VEGA 1/4064/07.

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