1371022526

DO NOT OPEN THIS TEST BOOKLET UNTIL YOU ARE ASKED TO DO SO
Test Booklet Series

TEST BOOKLET
Electronics & Communication Paper
Topic Test Digital & Microprocessor
Time Allowed: One Hour
Maximum Marks: 100
INSTRUCTIONS
1.
IMMEDIATELY AFTER THE COMMENCEMENT OF THE EXAMINATION YOU SHOULD
CHECK THAT THIS TEST BOOKLET DOES NOT HAVE ANY UNPRINTED OR TORN OR
MISSING PAGES OR ITEMS ETC. IF SO, GET IT REPLACED BY A COMPLETE TEST
BOOKLET.
2.
ENCODE CLEARLY THE TEST BOOKLET SERIES A, B, C, OR D AS THE CASE MAY BE IN
THE APPROPRIATE PLACE IN THE ANSWER SHEET.
3.
You have to enter your Roll Number on the
Test Booklet in the Box provided alongside.
DO NOT write anything else on the Test Booklet.
4.
This Test Booklet contains 60 items (questions). Each item comprises four responses (answers). You
will select the response which you want to mark on the Answer Sheet. In case you feel that there is
more than one correct response, mark the response which you consider the best. In any case, choose
ONLY ONE response for each item.
5.
You have to mark all you responses ONLY on the separate Answer Sheet provided. See directions in
the Answer Sheet.
6.
All items carry equal marks.
7.
Before you proceed to mark in the Answer Sheet the response to various items in the Test Booklet,
you have to fill in some particulars in the Answer Sheet as per instructions sent to you with your
Admission Certificate.
8.
After you have completed filling in all your responses on the Answer Sheet and the examination has
concluded, you should hand over to the Invigilator only the Answer Sheet. You are permitted to take
away with you the Test Booklet.
9.
Sheets for rough work are appended in the Test Booklet at the end.
10.
Penalty for wrong answers:
THERE WILL BE PENALTY FOR WRONG ANSWERS MARKED BY A CANDIDATE IN THE
OBJECTIVE TYPE QUESTION PAPERS.
(i)
There are four alternatives for the answer to every question. For each question for which a
wrong answer has been given by the candidate, one-third (0.33) of the marks assigned to that
question will be deducted as penalty.
(ii)
If a candidate gives more than one answer, it will be treated as a wrong answer even if one
of the given answers happens to be correct and there will be same penalty as above to that
question.
(iii) If a question is left blank, i.e., no answer is given by the candidate, there will be no penalty
for that question
DO NOT OPEN THIS TEST BOOKLET UNTIL YOU ARE ASKED TO DO SO
28A/11, Ground Floor- Jia Sarai New Delhi 16 Ph.: 09811382221, 011-32662945 www.panaceainstitute.org.in
Q.1.
How many 0s are present in binary representation of the expression

4 4096 9 257 7 17 4 9 1
(A) 7
(B) 8
(C) 9
(D) 10
Q.2.
Consider X (54)b where b is the base of the number system. If
Q.3.
Q.4.
X 7 then value of base b is?
(A) 7
(B) 8
(C) 9
(D) Cant be calculated
Which of the following statement is not correct?
(A) XS-64 represents numbers from -64 to +63& XS-32 represents numbers from -32 to +31
(B) XS-64 represents numbers from -64 to +64& XS-32 represents numbers from -32 to +32
(C) XS-64 representation uses 7 bits while XS-32 representation uses 6 bits
(D) XS-3 code is self complementary and unweighted code
In the logic equation A(A BC C) B(C A BC)(A BC AC) 1 If C A then which of the
following is true?
Q.5.
Q.6.
Q.7.
(A) A B 1
(B) A B 1
(C) A B 1
(D) A=1
Which of the following statements are correct??
1. The sum of all min terms of a boolen function of n-variables is 1
2. The sum of all min terms of boolean functions of n-variables is 0
3. The product of all max-terms of a boolean functions of n-variables is 0
4. The product of all max-terms of a boolean functions of n-variables is 1
(A) 1, 3
(B) 1, 4
(C) 2, 3
(D) 2, 4
(A) Dual and Complement of EX-OR are EX-NOR&EX-NOR respectively
(B) f(A,B,C)=AB+BC+CA is a self dual expression
(C) Dual and Complement of EX-OR are EX-NOR&EX-OR respectively
(D) Max terms and Min terms are complement to each other
Consider the logic function in Min terms form as f (A, B,C, D) (1,3,5,8,9,11,15) d(2,13) what
are the numbers of complemented literals in the expression of SOP form for f (A, B,C,D)?
(A) 3
(B) 4
(C) 5
(D) 6
Q.8.
Q.9.
For a Boolean function Y AB AC the POS form will be:

(A) (0, 2, 4)
(B) (1, 2,5,7)
(C) (2,3,5,7)
(D) (0, 2, 4,5)
What is the value of f (A, B,C) (f1.f 2 ) f3 if Min-terms of expressions are given as follows?
f1 (A, B, C) (0, 2,3, 4)
f 2 (A, B, C) (1, 2,3)
f3 (A, B, C) (4,5, 6)
(A) (0, 2,3, 4)
(B) (2,3, 4,5,6)
(C) (0,1, 2,3, 4,5,6)
(D) (2,3)
Q.10. In a 8 variable K-Map if 32 number of 1s are forming a group then number of literals in that group
after minimization will be?
(A) 3
(B) 4
(C) 5
(D) 6
Q.11. Which of the following identity is not correct:

(A) A B C A (B C) (A B) C
(C) A B AB A
AB A B
(B) A
CA
(B C) (A
(D) A
CA
(B
C) (A
B) C
B)
Q.12. How many essential prime implicates are available in expression of f (A, B,C) (0, 2,3, 4,5,7)
(A) 0
(B) 3
(C) 5
(D) 6
Q.13. A 1 bit full adder takes 5 ns to generate carry out bit and 10 ns for the sum bit. What is the maximum
rate of addition per second when four 1-bit full adders are cascaded?
Q.14.
Q.15.
Q.16.
Q.17.
(A) 107
(B) 6.25 106
(C) 4 107
(D) 6.25 107
Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean
function of n-variables. What is the Minimum size of Multiplexer needed??
(A) 2n-2 line to 1 line (B) 2n line to 1 line (C) 2n+1 line to 1 line (D) 2n-1 line to 1 line
(A) Half adder can be implemented by use of five two input NAND gate & five two input NOR gate
(B) Full adder can be implemented by use of nine two input NAND gate & nine two input NOR gate
(C) Half subtractor can be implemented by use of five two input NAND gate & five two input NOR
gate
(D) Half adder can be implemented by use of two 2:1 MUX (inverter is not available)
Consider the following statements. A 4 16 decoder can be constructed with enable inputs by
1. Using 4, 2 4 decoders (each with enable input)
4. Using 2, 3 8 decoders (each with enable i/p & inverter)
Which statements are correct?
(A) Only 1 & 4
(B) Only 2 & 4
(C) Only 1 & 3
(D) Only 2 & 3
Which of the following statement/s is/are correct?
1. The digital circuit using two inverters shown in figure will acts as Flip-flop
2. The digital circuit using five inverters shown in figure will acts as Ring counter.
v0
(A) Only 1
(B) Only 2
(C) Both 1 & 2
(D) None
Q.18. A 5 bit serial adder is implemented using two 5 bit shift registers, a full adder and a D Flip-flop. The
two binary words to be added are 11011 and 11011.The sum of the two numbers is stored in one of
the shift registers and the carry in the D Flip-flop. Assuming that D Flip-flop is set initially the
contents of the sum shift register and D Flip-flop respectively are:
(A) 10111 and 0
(B) 11011 and 1
(C) 11101 and 0
(D) 10111 and 1
Q.19. In circuit shown in figure, when inputs A = B = 0, Then possible logic states of C & D are
A
C
D
B
(A) C = 0, D = 1 or C = 1, D = 0
(B) C = 1, D = 1 or C = 0, D = 0
(C) C = 1, D = 0
(D) C = 0, D = 1
Q.20. In the modulo-6 ripple counter shown in figure the output of the 2-input gate is used to clear the J-K
flip-flops.
1
C
J
Clock
input
2-input
gate
The 2-input gate is:

(A) NAND gate
(B) NOR gate
Q.21. In the circuit shown below initially
D0
Q0
(C) OR gate
D1
(D) AND gate
Q1
Q0
Q1
CLK
Q0 = Q1 = 0 Then what are the values of Q0 and Q1 after 335th clock pulse.
(A) 00
(B) 01
(C) 10
(D) 11
Q.22. An X Y Flip-flop, whose characteristic table given below is to be implemented by use of a JK FlipFlop. This can be done by using
X
0
0
1
1
( A) J X K Y
( B) J X K Y
Y
0
1
0
1
Qn+1
1
Qn
Qn
0
(C ) J Y K X
( D) J Y K X
Q.23. Figure shows a ripple counter using positive edge triggered flip-flops. If the present state of the
counter is Q2 Q1 Q0 = 100 then its next state (Q2 Q1 Q0) will be:
1
1
CLK
T0
Q0
1
Q1
T1
Q0
Q2
T2
Q1
Q2
(A) 011
(B) 100
(C) 111
(D) 101
Q.24. Which of the following statement is not correct?
(A) 4-bit ring counter requires 4 Flip-flops
(B)MOD-4 Johnson counter requires 4 Flip-flops
(C) MOD-4 Ring counter requires 4 Flip flops
(D) Both Ring and Jhonson counter are basically shift registers
Q.25. An R 2R ladder type DAC is shown in Figure, if a switch status is 0 then 0 volt is applied and if a
switch status is 1 then 5 volt is applied to the corresponding terminal of DAC.
R
R
v0
2R
2R
S0
2R
S1
2R
What is the step size of DAC?

(A) 0.125 V
(B) 0.525 V
(C) 0.625 V
(D) 0.75 V
Q.26. Which of the following statement is not correct about ADC conversion time?
(A) Flash type ADC is the fastest ADC but conversion time depends upon no. of bits
(B) Counter type ADC has conversion time equal to 2N Tc where Tc is period of clock
(C) Successive approximation type ADC has conversion time equal to N Tc where Tc is period of
clock
(D) Dual slope ADC is the slowest ADC and has the highest accuracy
Q.27. A combinational circuit accepts a 2 bit binary number and output is square in binary. To design this
circuit using a ROM the minimum size of ROM required is:
(A) 2 2
(B) 4 2
(C) 4 4
(D) 8 4
Q.28. For a given logic family if followings are the available data:
1.IOH (max) 4mA
2.I IH (max) 0.02mA

3.IOL (max) 8mA
4.I IL (max) 0.4mA
What is the value of Fan-out of given logic family:
(A) 10
(B) 20
(C) 200
(D) 400
Q.29. If A and B are input as shown in figure and y is output then what is the value of y ??
V
CC
(A) AB
(B) ( AB)
(D) ( A B)
(C) (A + B)
+5v
Q.30.
A
B
o/p
In the I.C. logic gate shown in figure. If threshold voltage VBE is o.75 volt and VCE (sat) = 0.2 V
calculate value of output voltage. If VA = VB = 4.5 volt
(A) 0.75 V
(B) 0.55 V
(C) 5 V
(D) 0.2 V
Q.31. Which of the following statement is not correct about 8085 Micro processor?
(A) It has 8bits data line and 16 bits address line
(B) Both address and data buses are multiplexed in this microprocessor
(C) Out of 16 address lines only lower order buses (A0-A7) are used as both data bus and address bus
(D) Both address bus and data bus of a micro processor are always bi-directional
Q.32. Which of the followings is not correct about various signal in 8085 Micro processor?
(A) ALE is positive going pulse and is used to latch lower order bus from multiplexed bus
(B) RD Indicates that selected I/O or memory device is to be read and data are available on data bus
(C) WR Indicates that data on data bus are to be written into a selected memory or I/O location
(D) S1 and S0 are status signals and deals with interrupt in 8085 microprocessor
Q.33. Which of the following statements are true about interrupt in 8085 microprocessor:
1. There are five interrupts in 8085 microprocessor
2. TRAP has the highest priority followed by RST 7.5, RST 6.5, RST 5.5 and INTR
3. All three RST and TRAP dont require any external hardware i.e. they are automatically
transferred to specific locations without any hardware.
(A) 1 & 2
(B) 2 & 3
(C) 1 & 3
(D) 1, 2 & 3
Q.34. Which of the following statement is not correct about interrupt in 8085 Microprocessor
(A) TRAP is edge as well as level triggered interrupt
(B) RST 7.5 is positive edge triggered interrupt
(C) RST 6.5&RST 5.5 are level triggered interrupts
(D) RST 6.5&RST 5.5 are negative edge triggered interrupts
Q.35. Which of the following is not true about DMA transfer in microprocessor?
(A) It is direct transfer of data between memory and I/O devices without the use of microprocessor
(B) It is faster scheme for transfer of data from mass storage device & is also used for high speed
printers
(C) In burst mode DMA transfer I/O device withdraws request only after data bytes have been
transferred
(D) Cycle stealing scheme is same as burst mode transfer in DMA controller
Q.36. Which of the following statements are correct?
1. READY signal in 8085 is useful when the CPU communicates with a slow peripheral device
2. In a microprocessor wait states are used for interface of slow peripherals to the processor
3. READY signal is used to delay the microprocessor read or write cycles
4. READY pin is an output pin
(A) 1, 2 & 3
(B) 2, 3 & 4
(C) 1, 3 & 4
(D) 1, 2, 3 & 4
Q.37. Which of the followings are correct about INR and DCR instructions in 8085?
1. It affects contents of specified registers
2. It affects all flags except CY flag
3. Both INR and DCR are 2 byte instructions
(A) 1 & 2 only
(B) 2 & 3 only
(C) 1 & 3 only
(D) 1, 2 & 3 only
Q.38. Which of the following is not true about registers in 8085 Microprocessor?
(A) Both SP and PC are 16 bit registers used in 8085 Microprocessor
(B) PC always holds address of the next instruction to be fetched
(C) SP always holds the address of the top of the stack
(D) Accumulator is also 16 bit register in 8085 Microprocessor which is used to perform arithmetic
and logical operations.
Q.39. A small code of 8085 as given below, is executed
MVI A, 7FH
ORA A
CPI A2H
The contents of the accumulator and flags after execution are
(A) A DD, S = 1, Z = 0, CY = 0
(B) A 7F, S = 1, Z = 0, CY = 1
(C) A DD, S = 0, Z = 1, CY = 0
(D) A 7F, S = 0, Z = 1, CY = 1
Q.40. Which of the following statement is not correct about status of flag register in 8085 Microprocessor?
(A) The value of MSB of result following the execution of any arithmetic or Boolean instruction is
stored in the sign status flag
(B) In execution of XRA A instruction zero flag is set
(C) In execution of instruction SUB B sign flag must not be affected
(D) In execution of instruction SUB B zero flag may be affected
Q.41. Which of the following pair is not correctly matched with regard to addressing mode?
(A) STA 2400H--------------- Direct addressing mode
(B) LXI H, 2500H------------Immediate addressing mode
(C) MVI A, 05-----------------Immediate addressing mode
(D) MOV A, B----------------- Register addressing mode
Q.42. The following sequences of instructions are executed by an 8085 microprocessor:
1000
LXI
SP, 27 FF
1003
CALL
1006
1006
POP H
The contents of the stack pointer (SP) and the HL, register pair on completion of execution of these
Instructions are:
(A) SP = 27 FF, HL = 1003
(B) SP = 27 FD, HL = 1003
(C) SP = 27 FF, HL = 1006
(D) SP = 27 FD, HL = 1006
Q.43. Consider the sequence of 8085 instruction given below:
LXI H, 9258
MOV A, M
CMA
MOV M, A
Which one of the following is performed by this sequence?
(A) Contents of location 9258 are moved to the accumulator
(B) Contents of location 9258 are compared with the contents of the accumulator
(C) Contents of location 9258 are complemented and stored in location 9258
(D) Contents of location 5892 are complemented and stored in location 5892
Q.44. In the following 8085 program how many times (decimal) is the DCRC executed?
MVIC, 78 H
LOOP DCRC
JNZ LOOP
HLT
(A) 119
(B) 120
(C) 78
(D) 77
Q.45. Match List-I with List-II and select the correct answer using the code given below the Lists:
List-I
List-II
A. 8255A
1. Programmable Peripheral Interface
B. 8279
2. Programmable Interval Timer
C. 8254/8253
3. DMA Controller
D. 8237/8257
4. Programmable Keyboard/Display Interface
Code: A
B
C
D
A
B
C
D
(A)
2
4
1
3
(B)
1
3
2
4
(C)
2
3
1
4
(D)
1
4
2
3
Q.46. Which one of the following is used as the interface chip for data transmission between 8086 and a
16-bit ADC?
(A) 8259
(B) 8255
(C) 8253
(D) 8251
Q.47. Match List-I with List-II and select the correct answer using the code given below the Lists :
List I
List II
(Program Required in
(Definition)
System Software)
A. Linker
1. It is a program which combines smaller programs to
form a single program; and also links subroutines with the
main program
B. Loader
2. It is a program which loads machine codes of a program into
the system memory?
C. Interpreter
3. It is a program which translates a high-level program into
machine code executes it and reads one statement at a time,
executes and then goes to the next statements of the program
D. Compiler
4. It is a program which translates a high-level program into a
machine language, Reads the entire program and then
executes it
Code: A
B
C
D
A
B
C
D
(A)
1
2
3
4
(B)
3
4
1
2
(C)
1
4
3
2
(D)
3
2
1
4
Q.48. Which of the following statements are correct about 8086 Microprocessor?
1. It is 16 bit microprocessor and is 40 pin package
2. There are 14 general purpose registers
3. There are 9 flag registers
4. It is capable of addressing 2 M bytes of memory
(A) 1 & 2
(B) 1, 2 & 3
(C) 1, 3 & 4
(D) 1, 2, 3 & 4
Q.49. In a 8085 microprocessor, the following sequence of instructions is executed.
STC
CMC
MOV A, B
RAL
MOV B, A
After the last instruction the output will
(A) Rotate the contents of the accumulator and store it in B
(B) Get the contents of B register into accumulator and rotate it to left by one bit
(C) Double contents of B register
(D) manipulate carry in A and B
Q.50. If
(BX) = 0158
(DI) = 10A5
Displacement = 1B57
(DS) = 2100
(Where DS is used as a segment register) then the effective and physical addresses produced using
RELATIVE BASE INDEXED INDIRECT ADDRESSING will be respectively
(A) 2D54 and 23D54
(B) 23D54 and 2D54
(C) 1B57 and 1CAF (D) 1CAF and 1B57
Q.51. Which of the following statement is not correct about Cache memory?
(A) Cache memory is based upon concept of locality of reference
(B) Performance of cache memory is measured in terms of hit ratio
(C) Cache memory is fast but costly memory
(D) Size of cache memory is very large
Q.52. Which of the following statements are correct about various registers?
1. The register which contains the instruction to be executed is called as Index register
2. The register which keeps track of execution of a program and which contains the memory
address of instruction currently being executed is called as Program counter
3. The register which hold address of location to or from which data are to be transferred is known
as Memory Address Register (MAR)
4. The register which contains the data to be written into or readout of location is known as
Memory Buffer Register (MBR)
(A) 1, 2 & 3
(B) 2, 3 & 4
(C) 1, 3 & 4
(D) 1, 2, 3 & 4
Q.53. What is the depth of a complete binary tree with n nodes?
(A) log2(n + 1) 1
(B) log2(n 1) + 1
(C) log2(n) + 1
(D) log2(n) 1
Q.54. Given that main memory access time is 1200 ns and cache access time is 100 ns if the average
memory access time is not to exceed 120 ns. The hit ratio for the Cache must be at least:
(A) 90%
(B) 98%
(C) 80%
(D) 75%
Q.55. Which of the following are included in the architecture of computer?
1. Addressing modes, design of CPU
2. Instruction set, data formats
3. Secondary memory, operating system
Select the correct answer using the codes given below:
Codes: (A) 1 and 2
(B) 2 and 3
(C) 1 and 3
(D) 1, 2 and 3
Q.56. How many distinct binary trees can be constructed with three nodes?
(A) 1
(B) 2
(C) 3
(D) 5
Q.57. A sub routine can return:
(A) Only one value (B) only two values (C) Only three values
(D) any no of values
Q.58. Match List-I (Type of Data Structure) with List-II (Used in Application) and select the correct
answer using the codes given below the lists:
List-I
List-II
(Type of data Structure)
(Used in Application)
A. Stack
1. Solving linear simultaneous equations
B. Tree
2. Subroutine linkage
C. Record
3. File processing
D. Array
4. Sorting
Codes: A
B
C
D
A
B
C
D
(A)
3
4
2
1
(B)
2
1
3
4
(C)
2
4
3
1
(D)
3
1
2
4
10
Q.59. The default parameter passing mechanism in C programming language is:

(A) Call by reference
(B) Call as random
(C) Call by values
(D) Call by value result
Q.60. IC is the Instruction Count, CPI is average number of system clock periods to execute per instruction
and T is the duration of a clock period then which one of the following expresses execution time?
IC CPI
(A) IC CPI T
(B)
T
IC T
T CPI
(C)
(D)
CPI
IC
11
Engineering Service Examination -2013

SI No.
Electronics & Telecommunication Engineering
PAPER Digital Electronics & Microprocessor
(Conventional)
Time allotted: 90 Minute
Maximum marks: 100
INSTRUCTIONS
Candidates should attempt Question No. 1 which is compulsory and remaining FOUR from questions taking
two each from section-A and Section-B. The number of marks carried by each question is indicated at the
end of the question. Answers must be written only in English. Assume suitable data if found necessary and
indicate the same clearly. Values of the following constants may be used wherever necessary:
Electronic charge = 1.6 109 Coulomb
Free space permeability = 4 107 Henry /m.
1
9
Free space permittivity =
10 Farad/m.
36
Velocity of light in free space = 3 108 m/ sec.

Boltzmann constant = 1.38 1023 joule /K.
Planck constant = 6.626 1034 joule-sec.
Important: Candidates are to note that all parts and sub parts of a question are to be attempted
continuously in answer book. That is all parts and sub parts of a question being attempted must be
completed before attempting the next question.
Any page left blank in answer book must be clearly struck out. Answers that follow pages left blank
may not be given credit.
12
Q.1.
(a) The 4 1 MUX is shown in figure what is the value of output f(x, y, z) (5)
(b) Draw the circuit of a 3-bit parallel comparator analog to digital converter. Compare the speed and
hardware requirement of flash ADC, successive approximation ADC, counter type ADC and dual
slope ADC
(5)
(c) For the given synchronous counter what is the MOD of given counter? (5)
(d) Determine the dont care combinations in the following Boolean expression: BE BDE , which
is a simplified version of expression : ABE BCDE BCDE ABDE BCDE. (5)
(e) What are the function of the following pins of 8085 microprocessor (5)
(i) READY
(ii) ALE
(iii) HOLD (iv) TRAP
(v) HLDA
(f) Distinguish between (5)
(i) High Level Language and Low Level Language
(ii) Macro Programming and Micro-Programming
(iii) Machine Cycle and Instruction Cycle
(iv) Hardware Interrupts and Software Interrupts
(v) Memory mapped I/O and I/O mapped I/O.
(g) A memory system contains a cache, a main memory and a virtual memory. The access time of
the cache is 5 ns and it has an 80 percent hit rate. The access time of the main memory is 100 ns
and it has a 995 percent hit rate. The access time of the virtual memory is 10 ms. what is the
average access time of the hierarchy? (5)
(h) An 8085 assembly language program is given below. (5)
Line 1: MVI A, B5H
2: MVI B, 0EH
3: XRI 69 H
4: ADD B
5: ANI 9BH
6: CPI 9FH
7: STA 3010H
8: HLT
(i) The contents of the accumulator just after execution of the ADD instruction in line 4 will be:
(ii) After execution of line 7 of the program, the status of the CY and Z flags will be:
13
Q.2.
Q.3.
Q.4.
(a)
(b)
(c)
(a)
(b)
(a)
(b)
SECTION-A
Design Mod-6 Ripple Down counter by use of FFS and NAND gates (5)
Design Mod-8 Synchronous up counter by use of FFS and gates (5)
Convert D FF into T FF by K-Map method (5)
Draw NAND gate and NOR gate by use of CMOS (10)
Design Positive logic OR and Negative OR gate by use of diodes (5)
Construct a 4-input multiplexer using four 3-input AND gates, an OR-gate and three inverters.
Show the input, output and select lines and write a table showing the outputs for various select
inputs. (10)
For the circuit shown in figure below, two 4-bit parallel in serial-out shift registers loaded with
the data shown are used to feed the data to a full adder. Initially all the flip-flops are in clear
state. After applying two clock pulses, the outputs of the full adder should be (5)
1
MSB
A
S
FULL
ADDER
LSB
CK
Shift Registers
0
C0
CK
Ci
Q
CK
Clock
14
Q.5.
SECTION-B
(a) Write an 8085 ALP to find smallest number in an Array.
(10)
(b) What memory address range is represented by chip #1& chip #2 in figure? A0 to A15 in this
figure are the address lines and CS means Chip Select. (5)
A0A7
256 bytes
Chip # 1
A8
A9
A9
A8
A0A7
256 bytes
Chip # 2
A10A16
not used
Q.6.
The contents of some memory locations of an 8085 microprocessor system are show below. What
will be the contents of H-L Pair after the execution of the program given below. (15)
LHLD
3000H
MOV
E, M
INX
H
MOV
D, M
LDAX
D
MOV
L, A
INX
D
LDAX
D
MOV
H, A
Memory address
Memory contents
(Hex)
(Hex)
3000
02
3001
30
3002
00
3003
30
Q.7.
(a) Give the number of bytes, Machine cycles and T state for the following opcodes used in 8085
Micro Processor. (5)
(i) LDA
(ii) JMP
15
(iii) POP
(iv) STA
(v) STAX
(b) What are execution unit and bus interface unit in case of 8086 Microprocessor explain with
proper diagram. what is the difference between 8086 and 8088 microprocessor?
(10)
16

1371022526

Hochgeladen von

Dokumentinformationen

Copyright

Verfügbare Formate

Dieses Dokument teilen

Dokument teilen oder einbetten

Freigabeoptionen

Stufen Sie dieses Dokument als nützlich ein?

Sind diese Inhalte unangemessen?

Copyright:

Verfügbare Formate

1371022526

Hochgeladen von

Copyright:

Verfügbare Formate

DO NOT OPEN THIS TEST BOOKLET UNTIL YOU ARE ASKED TO DO SO

Test Booklet Series

How many 0s are present in binary representation of the expression

Consider X (54)b where b is the base of the number system. If

X 7 then value of base b is?

For a Boolean function Y AB AC the POS form will be:

(D) (0, 2, 4,5)

(A) (0, 2,3, 4)

(B) (2,3, 4,5,6)

(C) (0,1, 2,3, 4,5,6)

Q.11. Which of the following identity is not correct:

The 2-input gate is:

(D) AND gate

What is the step size of DAC?

2.I IH (max) 0.02mA

Q.59. The default parameter passing mechanism in C programming language is:

Engineering Service Examination -2013

Maximum marks: 100

Velocity of light in free space = 3 108 m/ sec.

Das könnte Ihnen auch gefallen