Course Code: CAP211

Course Name: COMPUTER ORGANIZATION AND ARCHITECTURE

HOME WORK -2 COURSE CODE-CAP211

COURSE INSTRUCTOR – Miss Kuljeet COURSE TUTOR – Miss Kuljeet

DATE OF ALLOTMENT – 25-09-09 DOS: 13/09/09

STUDENT ROLL.NO-RD3803B52 SECTION NO. D3803

DECELERATION: - I declare that this assignment is my individual work. I have not copied from
other students work or from any other source except where due acknowledgement is made explicitly in
the text, not has any part being written for me by another person.

Jivtesh Singh Ahuja

Evaluator comments…………….
 PART-A

Q1 Design a four bit combinational circuit incrementer and decrementer using full
adders.

4-bit combinational circuit using full adder: As increment means adding 1 bit to the
least significant bit of the input.. For getting its increment we have to add one carry to each
of the full hadder.
Full adder increment=A+1

4 bit combinational circuit decremented: We have to perm the operation A-1

A-1=A+2’s complement of 1(i.e. 1111)
Q2. Register A holds the 8 bit binary 11011001. Determine the B operand and the logic
microoperation to be performed in order to change the value in A to (a) 01101101 (b)
11111101

Using 01101101
A 11011001
B 10110100
------------------------
A A B 01101101

Using 1111101
A 11011001
B 11111101
------------------------
AAV B 11111101

Q3. Starting from initial value of R=11011101, determine the sequence of binary values
in R after a logic shift left followed by circular shift right, followed by a logical shift
right and a circular shift
ANS:
Initial value of R= 11011101
Logical Shift left= 10111010
Circular shift right= 01011101
Logical shift right= 00101110
Circular right shift= 01011100
 PART-B

Q4. Determine the micro operation that will be executed in the processor when
following 14 bit control words are applies
00101001100101
00000000000000
ANSWER:
(a) 00101001100101:

selA selb seld opr

r1 r2 r3 sub

microoperaition= r3 r1— r2

(b) 00000000000000:

selA selb seld opr

input input none tsfa

microoperation:

output  input

Q5.Convert the following arithmetic expressions from infix to RPN

A*B+C*D+E*F
A*B+C*D+EF*
A*B+C*DEF*+
A*B+CD*EF*+
AB*CD*EF*++

A*B+A*(B*D+C*E)

A*B+A*(BD*CE*+)
A*B+A(BD*CE*+)*
AB*A(BD*CE*+)*+
AB*ABD*ACE*+*+

A + B* [ C * D + E * ( F + G )]
A +B *[C * D + E * F G + ]
A + B * [ C D * + E * F G +]
FG+E*CD*+B*A+

A*[B+C*(D+E)]
F*(G+H))
A*[B+C*(D+ E)]FGH+*/
 A*[B+ CD E+*]FGH+*/
ABCDE +*+*FGH+*/

Q6. Convert the following from RPN to infix

ABCDE+*-/
ABCD+E *-/
ABC*D+E-/
A B – C * ( D + E) /
A/B–C*(D+E)

ABC*/D -EF/+
AB*C/D–EF/+
A/B*CD–EF/+
A / (B * C – D) E F / +
A / (B * C – D) E / F +
A / (B * C) – D + E / F