I.

VHDL
A. What is VHDL?
VHDL (VHSIC Hardware Description Language) is a hardware
description language used in electronic design automation to
describe digital and mixed-signal systems such as field-programmable
gate arrays and integrated circuits. VHDL can also be used as a general
purpose parallel programming language.
VHDL is a programming language that has been designed and
optimized for describing the behavior of digital systems. VHDL has many
features appropriate for describing the behavior of electronic
components ranging from simple logic gates to complete
microprocessors and custom chips. Features of VHDL allow electrical
aspects of circuit behavior (such as rise and fall times of signals, delays
through gates, and functional operation) to be precisely described. The
resulting VHDL simulation models can then be used as building blocks in
larger circuits (using schematics, block diagrams or system-level VHDL
descriptions) for the purpose of simulation. VHDL is also a generalpurpose programming language: just as high-level programming
languages allow complex design concepts to be expressed as computer
programs, VHDL allows the behavior of complex electronic circuits to be
captured into a design system for automatic circuit synthesis or for
system simulation. Like Pascal, C and C++, VHDL includes features
useful for structured design techniques, and offers a rich set of control
and data representation features. Unlike these other programming
languages, VHDL provides features allowing concurrent events to be
described. This is important because the hardware described using
VHDL is inherently concurrent in its operation. One of the most
important applications of VHDL is to capture the performance
specification for a circuit, in the form of what is commonly referred to as
a test bench. Test benches are VHDL descriptions of circuit stimuli and
corresponding expected outputs that verify the behavior of a circuit over
time. Test benches should be an integral part of any VHDL project and
should be created in tandem with other descriptions of the circuit.
B. Advantage of using VHDL
The key advantage of VHDL, when used for systems design, is that
it allows the behavior of the required system to be described (modeled)
and verified (simulated) before synthesis tools translate the design into
real hardware (gates and wires).

Another benefit is that VHDL allows the description of a concurrent

system. VHDL is a dataflow language, unlike procedural computing
languages such as BASIC, C, and assembly code, which all run
sequentially, one instruction at a time.
A VHDL project is multipurpose. Being created once, a calculation
block can be used in many other projects. However, many formational and
functional block parameters can be tuned (capacity parameters, memory
size, element base, block composition and interconnection structure).
A VHDL project is portable. Being created for one element base, a
computing device project can be ported on another element base, for
example VLSI with various technologies.
C. VHDL and Other HDL
Designers of electronic hardware describe the behavior and
structure of system and circuit designs using hardware description
languages (HDLs) specialized programming languages commonly
known as VHDL, Verilog, and System Verilog. They differ from software
programming languages because they include a means of describing
propagation time and signal strengths. These days, it would be
impossible to design a complex system on a chip (SoC) for a mobile
device or any other consumer electronics product without an HDL.
Each of the three HDLs has its own distinct style. VHDL and Verilog
implement register-transfer-level (RTL) abstractions. When they were first
introduced in the late 1980s, they were considered breakthrough
technologies because they enabled engineers to work at a higher level of
abstraction with RTL simulators. Previously, engineers simulated their
designs at the schematic or gate level.
System Verilog was developed to provide an evolutionary path
from VHDL and Verilog to support the complexities of SoC designs. Its a
bit of a hybridthe language combines HDLs and a hardware verification
language using extensions to Verilog, plus it takes an object-oriented
programming approach. System Verilog includes capabilities for test
bench development and assertion-based formal verification.
Comparing VHDL, Verilog, System Verilog
VHDL and Verilog are considered general-purpose digital design
languages, while System Verilog represents an enhanced version of
Verilog. Each has its own style and characteristics. VHDL has roots in the

Ada programming language in both concept and syntax, while Verilogs

roots can be tracked back to an early HDL called Hilo and the C
programming language.
With Verilog and VHDL, engineers can represent the desired
functionality as a software program. Then the model is simulated to
confirm the design will work as intended. Any problems can be corrected
in the model, and simulation will verify the correction.
VHDL is a rich and strongly typed language, deterministic and more
verbose than Verilog. As a result, designs written in VHDL are considered
self-documenting. Its syntax is non-C-like and engineers working in VHDL
need to do extra coding to convert from one data type to another. VHDL
often catches errors missed by Verilog. VHDL emphasizes unambiguous
semantics and allows portability between tools.
Sample VHDL Code

Verilog is weakly typed and more concise with efficient notation. It

is deterministic. All data types are predefined in Verilog and each has a
bit-level representation. Syntax is C-like.
Sample Verilog Code

System Verilog includes a set of extensions to the Verilog HDL to

help engineers design and verify larger and more complex designs. In
fact, many industry watchers consider it the first Hardware Description
and Verification Language (HDVL), because it combines VHDL and Verilog
features with those of Hardware Verification Languages (HVLs) Vera and e,
as well as C and C++. Its targeted at RTL coding, using constrained
random techniques for assertion-based and coverage-driven verification.
Sample System Verilog Code

Because of its structure, VDHL catches most errors early in the

design process. Verilog, on the other hand, enables engineers to quickly
write models. System Verilog attempts to capture the best features of
both, and includes features of HVLs to support test bench development
and formal verification techniques.
Conclusion
The language war days are long over, as engineering teams
worldwide effectively employ VHDL, Verilog and System Verilog for their
system on a chip (SoC) design needs. This overview provides a glimpse at
the differences between the three. In general, System Verilog can help

with both design and verification. Design tools from electronic-designautomation (EDA) companies can combine VHDL and Verilog to suit all
types of engineering requirements.