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  • Pass Transistor Logic PDF

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    Tejas Kumbar
    228 Ansichten25 Seiten
    This document discusses two basic ways of building logic circuits in MOS technology: pass transistor logic and transmission gate logic. Pass transistor logic uses transistors as switches to implement logic functions. It has advantages like faster speed and no static power consumption, but has drawbacks like logic level degradation and no regeneration. Complementary pass transistor logic addresses some issues but still has static power dissipation problems. Transmission gate logic uses a parallel combination of an n-MOS and p-MOS transistor to create a full-swing bidirectional switch. It overcomes logic level degradation issues but uses more area than pass transistor logic. Differential transmission gate logic is also discussed. Gate logic uses inverters as the basic building block

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    This document discusses two basic ways of building logic circuits in MOS technology: pass transistor logic and transmission gate logic. Pass transistor logic uses transistors as switches to implement logic functions. It has advantages like faster speed and no static power consumption, but has drawbacks like logic level degradation and no regeneration. Complementary pass transistor logic addresses some issues but still has static power dissipation problems. Transmission gate logic uses a parallel combination of an n-MOS and p-MOS transistor to create a full-swing bidirectional switch. It overcomes logic level degradation issues but uses more area than pass transistor logic. Differential transmission gate logic is also discussed. Gate logic uses inverters as the basic building block

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    © All Rights Reserved
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    228 Ansichten25 Seiten

    Pass Transistor Logic PDF

    Hochgeladen von

    Tejas Kumbar
    This document discusses two basic ways of building logic circuits in MOS technology: pass transistor logic and transmission gate logic. Pass transistor logic uses transistors as switches to implement logic functions. It has advantages like faster speed and no static power consumption, but has drawbacks like logic level degradation and no regeneration. Complementary pass transistor logic addresses some issues but still has static power dissipation problems. Transmission gate logic uses a parallel combination of an n-MOS and p-MOS transistor to create a full-swing bidirectional switch. It overcomes logic level degradation issues but uses more area than pass transistor logic. Differential transmission gate logic is also discussed. Gate logic uses inverters as the basic building block

    Copyright:

    © All Rights Reserved
    Als PDF, TXT herunterladen oder online auf Scribd lesen
    Markieren Sie unangemessene Inhalte
    von 25

    Pass Transistor and

    Transmission Gate Logic

    P.K. Shetty, MCIS, Manipal

    Building Logic Circuits

    In designing digital systems in MOS technology


    there are 2 basic ways of building logic circuits:

    Switch Logic

    Pass Transistor Logic


    Transmission Gate Logic

    Gate (Restoring) Logic

    P.K. Shetty, MCIS, Manipal

    Pass Transistor Logic


    B

    Approach is faster for smaller arrays


    Takes no static current from the supply rails. Thus power
    dissipation of such arrays is small since current only flows on
    switching
    The path through each switch is isolated from the signal
    activating the switch
    N transistors instead of 2N
    No static power consumption
    Ratioless
    Bidirectional (versus undirectional)
    P.K. Shetty, MCIS, Manipal

    Pass Transistor - Drawbacks

    Undesirable threshold voltage effects which give rise to


    the loss of logic levels (Logic level degradation)
    VDD

    output

    VDD

    output

    X(=0)

    X (=1)
    1
    0

    Vtn

    1
    0

    Vtp

    Pure PT logic is not regenerative - the signal gradually degrades after


    passing through a number of PTs (can fix with static CMOS inverter
    insertion)
    P.K. Shetty, MCIS, Manipal

    Complementary PT Logic (CPL)

    P.K. Shetty, MCIS, Manipal

    CPL Properties

    Differential; so complementary data inputs and outputs


    are always available (so dont need extra inverters)

    Still static, since the output defining nodes are always


    tied to VDD or GND through a low resistance path

    Design is modular; all gates use the same topology, only


    the inputs are permuted.

    Simple XOR makes it attractive for structures like adders

    Fast (assuming number of transistors in series is small)

    Additional routing overhead for complementary signals

    Still have static power dissipation problems


    P.K. Shetty, MCIS, Manipal

    4-input NAND in CPL

    P.K. Shetty, MCIS, Manipal

    CPL Full Adder

    P.K. Shetty, MCIS, Manipal

    NMOS Only PT Driving an Inverter

    Vx does not pull up to VDD, but VDD VTn

    Threshold voltage drop causes static power consumption (M2


    may be weakly conducting forming a path from VDD to GND)

    Notice VTn increase of pass transistor due to body effect (VSB)


    P.K. Shetty, MCIS, Manipal

    Voltage Swing of PT Driving an Inverter

    Body effect large VSB at x - when pulling high (B is tied


    to GND and S charged up close to VDD)
    So the voltage drop is even worse
    Vx = VDD - (VTn0 + ((|2f| + Vx) - |2f|))
    P.K. Shetty, MCIS, Manipal

    Cascaded NMOS Only PTs

    Pass transistor gates should never be cascaded as on


    the left

    Logic on the right suffers from static power dissipation


    and reduced noise margins
    P.K. Shetty, MCIS, Manipal

    Transmission Gate (TG) Logic

    The degradation of logic levels in simple n or p switches


    can be overcome by using transmission gates, comprising
    an n-pass and p-pass transistors in parallel.

    Transmission Gate

    Symbols Used

    P.K. Shetty, MCIS, Manipal

    Transmission Gates (TG)

    Most widely used

    Full swing bidirectional switch controlled by the gate


    signal C.
    A = B if C = 1

    P.K. Shetty, MCIS, Manipal

    Resistance of TG

    P.K. Shetty, MCIS, Manipal

    TG Multiplexer

    P.K. Shetty, MCIS, Manipal

    TG XOR

    P.K. Shetty, MCIS, Manipal

    TG Full Adder

    P.K. Shetty, MCIS, Manipal

    Differential TG Logic

    P.K. Shetty, MCIS, Manipal

    Transmission Gate - Drawbacks

    Occupies more area one pass transistor is replaced by


    2 transistors

    Requires complementary signals to drive it

    P.K. Shetty, MCIS, Manipal

    Gate Logic

    Inverter the most basic gate


    VDD
    Load (pull-up)
    VGG

    Out
    In
    Driver (pull-down)

    Note: The driver transistor is enhancement mode device to satisfy


    I/O compatibility.
    P.K. Shetty, MCIS, Manipal

    Basic Single Channel Inverters


    1.

    If VGGVT > VDD then the load is said to be NELT (N-channel


    Enhancement Load in Triode region) Needs a separate supply.

    2.

    If the load is maintained in the saturation region throughout, then the


    load is said to be NELS (N-channel Enhancement Load in Saturation)

    3.

    HMOS (High performance MOS) Trademark given to Intel.


    VDD

    VDD

    VDD

    VGG

    Out
    In

    Out
    In

    1. NELT

    Out
    In

    2. NELS
    P.K. Shetty, MCIS, Manipal

    3. HMOS

    HMOS

    The load is a depletion mode transistor.

    Advantages:

    Good noise margin


    High speed
    Low power consumption
    High packing density

    Limitations:

    It is difficult to fabricate both enhancement and depletion mode


    MOSFETs together

    R =

    (W/L)Load

    Determines the performance of the Inverter.

    (W/L)Driver
    P.K. Shetty, MCIS, Manipal

    Realization of Basic Gates


    VDD

    VDD

    F
    F

    A
    C

    B
    C

    1. NOR Gate

    2. NAND Gate

    P.K. Shetty, MCIS, Manipal

    Power Dissipation in Single Channel


    Inverters

    NELS : P VDD3

    NELT : P VDD3

    HMOS: P = LVDD VP;


    P VDD

    P.K. Shetty, MCIS, Manipal

    CMOS Inverter

    Realized by the series connection of a p and n


    device, as shown.

    Vin

    P.K. Shetty, MCIS, Manipal

    Vout

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