Edge-Sensitive Flip-Flops

Setup and Hold Time

Definition of Terms

Definition of Terms

There
Thereis
isaatiming
timing
"window"
"window"around
aroundthe
the
clocking
clockingevent
event
during
duringwhich
whichthe
theinput
input
must
remain
stable
must remain stable
and
andunchanged
unchanged
in
inorder
order
to
tobe
berecognized
recognized

Input:
Value sampled by flip-flop at clock edge.
Input

Input

Clock:
Periodic Event, causes state of memory
element to change. Input is sampled at
this clock edge.

Clock

Tsu
Clock

Th

Setup Time (Tsu)

Minimum time before the clocking event by
which the input must be stable

Example: D Flip-Flop
Input

Hold Time (Th)

Minimum time after the clocking event during
which the input must remain stable

Clock

Output

Edge-Sensitive Flip-Flops

Edge-Sensitive Flip-Flops

Invalid!

Input

Tsu

Input value changes after the setup

time. The input is not stable long
enough before the clock edge.

Clock

Invalid!

Input

Clock

Analogy - Taking Your Friend to the Train

If the train leaves at 8:00 and you live 20 minutes

away from the station, when should you leave your
house?

Input value changes before the hold

time. The input is not stable long
enough after the clock edge.
Th

Analogy - Taking Your Friend to the Train (cont.)

Your friend needs help boarding the train and the

train allows only 5 minutes for boarding.

How long should you stay after you have arrived?

At least five minutes (hold time) or 8:05 at the
earliest.

At 7:40! (setup time is 20 minutes)

If you leave after 7:40, you will miss the train. If you
leave before 7:40, you should have enough time to
get to the station before it leaves.

Without your help for the full 5 minutes, your friend

is not able to board and will miss the train.

Negative Hold Time

Negative Setup Time

The
Thevalid
validregion
regionor
or
"window"
"window"associated
associated
with
withthe
theclock
clockevent
event
does
nothave
doesnot
haveto
tobe
be
centered
centeredaround
aroundthe
the
clock
clockedge.
edge.

Input

Tsu

The
Theregion
regioncan
canbe
beto
to
the
theright
rightor
orleft
leftof
ofthe
the
clock
edge
when
clock edge whenthe
the
setup
setupor
orhold
holdtimes
times
are
negative.
arenegative.

Th (Negative Hold Time)

Clock

The
Thevalid
validregion
regionor
or
"window"
"window"associated
associated
with
withthe
theclock
clockevent
event
does
nothave
doesnot
haveto
tobe
be
centered
centeredaround
aroundthe
the
clock
clockedge.
edge.

Input

(Negative Setup Time)

Th

Clock

When the hold time is negative, the

valid region is to the left of the clock
edge.

When the setup time is negative, the

valid region is to the right of the clock
edge.

This allows the input to change

slightly before the clock edge without
disturbing the operation of the flip-flop.

This allows the input to change

slightly after the clock edge without
disturbing the operation of the flip-flop.

Propagation Delay

The
Theregion
regioncan
canbe
beto
to
the
theright
rightor
orleft
leftof
ofthe
the
clock
edge
when
clock edge whenthe
the
setup
setupor
orhold
holdtimes
times
are
negative.
arenegative.

Tsu

Note: you cannot have both

a negative setup time and
a negative hold time!

Edge-Triggered Timing Specifications

The output of a flip-flip does not change instantaneously at the

clock edge. The change in output occurs after a propagation
delay through the flip flop.

74LS74 Positive
Edge Triggered
D Flipflop
Setup time
Hold time
Minimum clock width
Propagation delays
(low to high, high to low,
max and typical)

Tsu
20
ns

Clk

Clk
Tplh

Th
5
ns

T su
20
ns

Tw
25
ns
Tplh
25 ns
13 ns

Th
5
ns

T phl
40 ns
25 ns

T phl

All measurements are made from the clocking event

that is, the rising edge of the clock

The propagation delay is usually different for the

low to high and high to low transitions.

Cascaded Flipflops

Cascaded Flipflops

Cascaded Flipflops and Setup/Hold/Propagation Delays

Are the Setup and Hold Times met?

Q0: Input is IN
IN

C Q

Q0

IN

Q1

C Q

C Q

CLK

CLK

Clock

Clock

IN

IN

Q0

Q0

Q1

Q1

Q0

C Q

Q1

Setup and hold

times are met
if the input, IN,
does not change
within the valid
region or
window.

Cascaded Flipflops

Cascaded Flipflops

Are the Setup and Hold Times met?

Are the Setup and Hold times of Q1 met?

Q1: Input is Q0
IN

Q0

C Q

Q1

Wait!

C Q

Q0 is changing
right at the clock
edge. Wont this
violate the hold
time of Q1?

CLK

Does it violate
the setup time of
Q1?

Clock

IN

IN
T plh

T phl

Q0
Th

Q0

Th

Q1
Q1

As long as Tplh > Th and Tphl > Th

Cascaded Flipflops

Cascaded Flipflops

Are the Setup and Hold times of Q1 met?

How fast can you clock this circuit?

IN

Q0

C Q

Q1

C Q

CLK

Tclk ?
IN
Clock

T plh
Q0

Tphl
Th

Th

Q0

Q1

If Tplh < Th or Tphl < Th, there is a hold time violation!

Cascaded Flipflops

Q1

Clock Skew

How fast can you clock this circuit?

IN

Q0

C Q

C Q

CLK

Tclk > Tp + Tsetup

Clock

Q1

Proper operation of synchronous systems

requires that all registered elements are clocked
at the same time
Some times this is not possible - the clock seen at
one flip-flop may be slightly delayed with respect
to the clock at another flip-flop
The relative delay of the clock is called clock
skew
IN

T plh
Q0
Tsetup
Q1

Q0

C Q

CLK 0

C Q

CLK 1

Clock Delay

Q1

Clock Skew

Clock Skew
Are the Setup and Hold Times of Q1 met?

CLK1 is a delayed version of CLK0 (delayed

by the clock skew, )

IN
IN

Q0

Q1

Q0

C Q
C Q

Q1

C Q

C Q

CLK 0

CLK 0

CLK 1

CLK 1

CLK0

CLK0

IN

IN

Q0

Q0

CLK1

CLK1

Clock Skew

Clock Skew

How do we guarantee proper operation?

IN

Q0

C Q

CLK 0

Are the Setup and Hold times of Q1 met?

Q

Q1

CLK0

C Q

CLK 1

IN
CLK0

T plh
Q0

IN

Tphl
Ts

Q0

Th

CLK1

Tsu

CLK1

Th

To insure hold-time constraints are met,Tskew + Thold < Tprop,

or Tskew < Tprop - Thold
Setup time will be guaranteed if hold-time constraints are met

State Machine Timing

State Machine Timing

Timing in Synchronous Systems

The maximum clock rate (i.e. minimum clock period) is determined by
the longest path from the output of a flip-flop to an input of a flip flop
(Q to D). We need to evaluate all Q to D paths and determine the path
that takes the longest time.

Inputs

Input
Forming
Logic

NS

CS

Output
Forming
Logic

clrcnt

Moore Machine - Review

State Flip-Flops
Input Forming Logic (IFL)
Output Forming Logic (OFL)

Inputs

Input
Forming
Logic

NS

What are the Critical Paths?

CS

Output
Forming
Logic

clrcnt

State Machine Timing

State Machine Timing

Critical Path #1

Critical Path #2

There may be multiple paths between the state FFs, through

the IFL and back into the FFs. You need to identify the longest
(i.e. slowest) path.

Inputs

Input
Forming
Logic

NS

CS

Output
Forming
Logic

clrcnt

1. Output of state flip-flops, through the IFL, and back into the FFs

FF propagation, IFL propagation, and FF setup time

Inputs

Input
Forming
Logic

NS

CS

Output
Forming
Logic

clrcnt

2. Inputs signals through the IFL and into the FFs

Input delay, IFL propagation, and FF setup time

Tp_ff + Tp_ifl + Tsu

Tinput + Tp_ifl + Tsu

State Machine Timing

State Machine Timing

Input Delay
specifies the maximum delay of a synchronous input

Moore Machine - Critical Path

#1 - FF, IFL, FF (Q to D)
#2 - Input, IFL, FF

relative to the clock edge.

You must identify the longest critical path!

CLK
Tinput
Inputs

Input

State Machine Timing

Input
Forming
Logic

NS

CS

Output
Forming
Logic

clrcnt

CS

Output
Forming
Logic

clrcnt

State Machine Timing

Moore Machine - Output Timing

Inputs

Input
Forming
Logic

NS

Moore Machine - Output Timing

CS

Output
Forming
Logic

clrcnt

Inputs

Input
Forming
Logic

NS

Tp_ff + Tp_ofl
When is the output signal valid?

When is the output signal valid?

State Machine Timing

State Machine Timing

Example

Example

Flip-Flop Timing

Input Timing

Flip-Flop Timing

Input Timing

Th

5 ns

Tinput

Th

5 ns

Tinput

Tsu

20 ns

Tsu

20 ns

Tplh

25 ns (max)
10 ns (min)
40 ns (max)
20 ns (min)

Tplh

25 ns (max)
10 ns (min)
40 ns (max)
20 ns (min)

Tphl

X
B

35 ns (max)
25 ns (min)
Gate Timing

Tplh

22 ns (max)
10 ns (min)
15 ns (max)
8 ns (min)

Tphl

Q
Q

B
A

Q
Q

Tphl

35 ns (max)
25 ns (min)
Gate Timing

Tplh

22 ns (max)
10 ns (min)
15 ns (max)
8 ns (min)

Tphl

Q
Q

Q
Q

CLK

Z
A

B
B

CLK

State Machine Timing

State Machine Timing

Example

Example

Flip-Flop Timing

Input Timing

Flip-Flop Timing

Input Timing

Th

5 ns

Tinput

Th

5 ns

Tinput

Tsu

20 ns

Tsu

20 ns

Tplh

25 ns (max)
10 ns (min)
40 ns (max)
20 ns (min)

Tplh

25 ns (max)
10 ns (min)
40 ns (max)
20 ns (min)

Tphl

X
B

35 ns (max)
25 ns (min)
Gate Timing

Tplh

22 ns (max)
10 ns (min)
15 ns (max)
8 ns (min)

Tphl

Q
Q

Tphl

A
Z
A

Tp_fl + Tp_ifl

Q
Q

35 ns (max)
25 ns (min)
Gate Timing

Tplh

22 ns (max)
10 ns (min)
15 ns (max)
8 ns (min)

Tphl

Q
Q

40 + 22 + 22 ns

B
A

A
Z
A

Q
Q

B
B

CLK

State Machine Timing

State Machine Timing

Example

Example

Flip-Flop Timing

Input Timing

Flip-Flop Timing

Input Timing

Th

5 ns

Tinput

Th

5 ns

Tinput

Tsu

20 ns

Tsu

20 ns

Tplh

25 ns (max)
10 ns (min)
40 ns (max)
20 ns (min)

Tplh

25 ns (max)
10 ns (min)
40 ns (max)
20 ns (min)

X
B

35 ns (max)
25 ns (min)
Gate Timing

Tplh

22 ns (max)
10 ns (min)
15 ns (max)
8 ns (min)

Tphl

Q
Q

Tphl

A
Z
A

Tinput

Q
Q

CLK

35 ns (max)
25 ns (min)
Gate Timing

Tplh

22 ns (max)
10 ns (min)
15 ns (max)
8 ns (min)

Tphl

Q
Q

35 ns

B
A

Tp_fl + Tp_ifl + Tsu

40 + 22 + 22 + 20 = 104 ns

B
A

CLK

Tphl

Tp_fl
40 ns

B
A

A
Z
A

Tinput + Tp_ifl
35 + 22 + 22 ns

B
A

Q
Q

CLK

B
B

State Machine Timing

State Machine Timing

Example

Example

Flip-Flop Timing

Input Timing

Flip-Flop Timing

Input Timing

Th

5 ns

Tinput

Th

5 ns

Tinput

Tsu

20 ns

Tsu

20 ns

Tplh

25 ns (max)
10 ns (min)
40 ns (max)
20 ns (min)

Tplh

25 ns (max)
10 ns (min)
40 ns (max)
20 ns (min)

Tphl

X
B

35 ns (max)
25 ns (min)
Gate Timing

Tplh

22 ns (max)
10 ns (min)
15 ns (max)
8 ns (min)

Tphl

Q
Q

Tphl

A
Z
A

Tinput + Tp_ifl + Tsu

Q
Q

B
A

Th

5 ns

Tinput

Tsu

20 ns

Tplh

25 ns (max)
10 ns (min)
40 ns (max)
20 ns (min)

Output Timing

35 ns (max)
25 ns (min)
Gate Timing

Tplh

22 ns (max)
10 ns (min)
15 ns (max)
8 ns (min)

Tphl

Q
Q

Q
Q

Input Timing

Th

5 ns

Tinput

Tsu

20 ns

Tplh

25 ns (max)
10 ns (min)
40 ns (max)
20 ns (min)

A
Z
A

Tp_fl

Output Timing

35 ns (max)
25 ns (min)
Gate Timing

Tplh

22 ns (max)
10 ns (min)
15 ns (max)
8 ns (min)

Tphl

Q
Q

Tp_fl + Tp_ofl

Z
A

40 + 22 = 62 ns

B
A

Q
Q

CLK

B
B

CLK

State Machine Timing

State Machine Timing

Example
Flip-Flop Timing

Input Timing

Th

5 ns

Tinput

Tsu

20 ns

Tplh

25 ns (max)
10 ns (min)
40 ns (max)
20 ns (min)

Flip-Flop Timing

Tphl

40 ns
D

Z
A

Example
Input Timing

Tphl

Q
Q

Example

B
A

State Machine Timing

Flip-Flop Timing

CLK

State Machine Timing

Critical Path: 104 ns (9.6 MHz)

22 ns (max)
10 ns (min)
15 ns (max)
8 ns (min)

Tphl

CLK

Tphl

Tplh

35 + 22 + 22 + 20 = 99 ns

B
A

Feedback Path: 104 ns

Input Path: 99 ns

35 ns (max)
25 ns (min)
Gate Timing

Output Path: 62 ns

35 ns (max)
25 ns (min)
Gate Timing

Tplh

Critical Path: 104 ns (9.6 MHz)

22 ns (max)
10 ns (min)
15 ns (max)
8 ns (min)

Tphl

Mealy Machine - Critical Path Same as the Moore Machine

#1 - FF, IFL, FF (Q to D)
#2 - Input, IFL, FF

Q
Q

Inputs Input/Output
Forming
Logic

NS

CS

Z
A

Outputs
B
A

Q
Q

CLK

B
B

State Machine Timing

State Machine Timing

Mealy Machine - Critical Path Same as the Moore Machine

#1 - FF, IFL, FF (Q to D)
#2 - Input, IFL, FF

Mealy Machine - Critical Path Same as the Moore Machine

#1 - FF, IFL, FF (Q to D)
#2 - Input, IFL, FF

Tp_ff + Tp_ifl + Tsu

Inputs Input/Output
Forming
Logic

NS

Tinput + Tp_ifl + Tsu

Inputs Input/Output
Forming
Logic

CS

NS

Outputs

CS

Outputs

State Machine Timing

State Machine Timing

Mealy Machine - Output Timing

#1 - FF, OFL
#2 - Input, OFL

Mealy Machine - Output Timing

#1 - FF, OFL
#2 - Input, OFL

Tinput + Tp_ofl
Inputs Input/Output
Forming
Logic

NS

Tp_ff + Tp_ofl
Inputs Input/Output
Forming
Logic

CS

NS

Outputs

State Machine Timing

Outputs

State Machine Timing

Example

Example

Flip-Flop Timing

Input Timing

Th

5 ns

Tinput

Tsu

20 ns

Tplh

25 ns (max)
10 ns (min)
40 ns (max)
20 ns (min)

Tphl

CS

Critical Path: 104 ns (9.6 MHz)

35 ns (max)
25 ns (min)
Gate Timing

Tplh

22 ns (max)
10 ns (min)
15 ns (max)
8 ns (min)

Tphl

Flip-Flop Timing

Input Timing

Th

5 ns

Tinput

Tsu

20 ns

Tplh

25 ns (max)
10 ns (min)
40 ns (max)
20 ns (min)

Tphl

35 ns (max)
25 ns (min)
Gate Timing

Tplh

22 ns (max)
10 ns (min)
15 ns (max)
8 ns (min)

Tphl

Output Path
X
B

Q
Q

B
A

Q
Q

CLK

X
B

Q
Q

Tp_ff

40 ns

B
A

Q
Q

CLK

B
B

State Machine Timing

State Machine Timing

Example

Example

Flip-Flop Timing

Input Timing

Flip-Flop Timing

Input Timing

Th

5 ns

Tinput

Th

5 ns

Tinput

Tsu

20 ns

Tsu

20 ns

Tplh

25 ns (max)
10 ns (min)
40 ns (max)
20 ns (min)

Tplh

25 ns (max)
10 ns (min)
40 ns (max)
20 ns (min)

Tphl

35 ns (max)
25 ns (min)
Gate Timing

Tplh

22 ns (max)
10 ns (min)
15 ns (max)
8 ns (min)

Tphl

Tphl

35 ns (max)
25 ns (min)
Gate Timing

Tplh

22 ns (max)
10 ns (min)
15 ns (max)
8 ns (min)

Tphl

Output Path
X
B

Q
Q

Tp_ff + Tp_ofl

Output Path
X
B

Q
Q

B
A

Q
Q

35 ns
B
A

Q
Q

CLK

B
B

CLK

State Machine Timing

State Machine Timing

Example

Example

Flip-Flop Timing

Input Timing

Flip-Flop Timing

Input Timing

Th

5 ns

Tinput

Th

5 ns

Tinput

Tsu

20 ns

Tsu

20 ns

Tplh

25 ns (max)
10 ns (min)
40 ns (max)
20 ns (min)

Tplh

25 ns (max)
10 ns (min)
40 ns (max)
20 ns (min)

Tphl

35 ns (max)
25 ns (min)
Gate Timing

Tplh

22 ns (max)
10 ns (min)
15 ns (max)
8 ns (min)

Tphl

Tphl

35 ns (max)
25 ns (min)
Gate Timing

Tplh

22 ns (max)
10 ns (min)
15 ns (max)
8 ns (min)

Tphl

Critical Path: 104 ns (9.6 MHz)

Output Path
X
B

Q
Q

Tinput + Tp_ofl

Output Path
X
B

Q
Q

A
A

35 + 22 = 57 ns
B
A

Q
Q

B
A

Example
Flip-Flop Timing

Input Timing

Th

5 ns

Tinput

Tsu

20 ns

Tplh

25 ns (max)
10 ns (min)
40 ns (max)
20 ns (min)

35 ns (max)
25 ns (min)
Gate Timing
22 ns (max)
10 ns (min)
15 ns (max)
8 ns (min)

Tphl

Q
Q

A
Z
A
clr

B
A

Counter

Tplh

S3
S2
S1
S0

Q
Q

CLK

B
B

Q
Q

CLK

State Machine Timing

CLK

Tphl

Tinput

40 + 22 = 62 ns

B
B

62 ns