1

A USB 2.0 Controller for an ARM77TDM-S

GA
Processoor Implemented in FPG
John Keithley L. Difuntorum, Kristine Mari U. Matutina, Al Jerome Merrvyn Z. Tong

Anastaciaa Ballesil Alvarez, Joy Alinda Reyes Madambba

Intel Microprocessorrs Laboratory, Microelectronics and Microprocessors Lab
Electrical and Electronicss Engineering Institute, University of the Philippiines - Diliman
Abstract In this paper, we present a deesign of a USB 2.0

M CONCEPT
II. SYSTEM

interface for an ARM7TDM-S system. Th

he whole system is
implemented on a Virtex-5 FPGA and uses a separate external
USB 2.0 transceiver hardware for signalingg requirements. The
design is coded in Verilog HDL. The projecct utilizes the Xilinx
ISE Design Suite workflow.
The system supports USB communicatioon from the ARM7
system on the FPGA to the USB Host PC, an
nd vice-versa.

The general idea of the project is shown in Fig. 1.

Index TermsARM7, FPGA, USB 2.0 Coontroller

I. INTRODUCTION

ith the advent of faster and more powerful

p
electronic
devices, modern mediums of comm
munication need to
adapt to the speed of this rapidly evoolving technology.
Universal Serial Bus (USB) is a standard communication
interface that has become a staple connnection method for
most computer peripherals. It provides a bi-directional,
b
lowcost, and high speed serial interface for daata transfer.

Figure 1. General Persspective of the System

The ARM7 system is connnected to the designed USB
controller and is loaded to an FPGA
F
board. Once a working
implementation is achieved, thee system is connected to a PC
through a USB 2.0 transceiver for
f exchange of data.

The Intel Microprocessors Laboratory has been

conducting studies on RISC processorss, specifically the
ARM and DLX processors. However, thee ARM7 core, with
its many enhancements is not yet providedd with an interface
that will allow external communication. In
I able to add this
functionality to the core, a good starting point would be a
USB interface.

N OF MODULES
III. DISCUSSION

A. ARM 7TDM-S
An ARM7TDM-S processor core acts as the logical brain
of the FPGA based system for handling data processing and
s
delegates USB 2.0
manipulation. The ARM7 system
communication to the USB conntroller, therefore it does not
have direct influence on USB data
d transfers.

In our study, a USB 2.0 interface is implemented and

integrated with the ARM7TDM-S core.
The USB communication implemented complies with
selected USB 2.0 specifications essentiial for basic data
transfer and is coded in Verilog HDL.
H
The USB
communication supports all transfers exxcept Isochronous
transfer. Direction is from the host computer to the
O
a single USB
ARM7TDM-S system and vice-versa. Only
connection to a PC is supported at any givven time.

B. ZBT SRAM (Internal FPG

GA SRAM)

Figure 2. ZBT Interface Module

t Virtex 5 FPGA is used as
A ZBT SRAM available on the
a data memory of both the ARM
M7 core and USB Controller.
A multiplexer is placed at thee input of the ZBT interface
module to allow data to be shared.
s
Sharing the memory
allows ease of processing of received
r
data from the USB
Host since the ARM7 core acceesses the same memory space
used by the USB controller.
978-1-4577-0255-6/11/$26.00 2011 IEEE

689

TENCON 2011

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CL)
E.1 USB Core Logic (UC

C. Bus Arbiter
The Bus Arbiter module gives control to either the USB
n
to access the
Controller or the ARM7 whenever one needs
Main Memory. It prioritizes the USB Controller
C
over the
ARM7. The Bus Arbiter sets the ARM7 on hold whenever it
t
as the USB
requires memory access at the same time
Controller to prevent bus contention.
D. USB Interface Module (USBI)
The USB Interface Module providdes compatibility
between the USB Controller and the ZBT
T SRAM. The USB
Controller accepts and sends data in byttes while the ZBT
SRAM receives and gives data in 32 bits.

Figure 6. USB Core Logic Block Diagram

Protocol Layer implementaation adhering to USB 2.0
Specification is implemented by the USB Core Logic. It
handles packet assembly and disassembly, data decoding,
flow control, error detection, annd fault recovery.
E.2 Endpoint Register Fille (ERF)
Data decoded from the UC
CL is routed to the various
endpoints of the Endpoint Regiister File. Data from different
endpoints have endpoint-speciffic functions. Table 1 shows
the functions of each endpoint.

m for USBI
Figure 3. STORE Timing Diagram

Endpoint
EP0
EP1
EP2
m for USBI
Figure 4. LOAD Timing Diagram
EP3
o the STORE and
Fig. 3 & 4 shows the timing diagrams of
LOAD operations of USBI respectively.

Functionality
Control Endpoint; for Control transfers
IN Endpoint; conttains USB data to be
transmitted to Host
OUT Endpoint; coontains SRAM Address for
both transmit andd receive operations
OUT Endpoint; coontains Data to be written to
SRAM for receivee operations
Table 1. Functionalitiess of Endpoints in ERF'

E.3 USB Function (USBF))

Standard device requests isssued by the USB Host are
handled by the USB Function. This includes status and
enumeration responses. Sincce it handles enumeration
specified in [2] for the ARM7 system side, it also contains
the main descriptors of the systeem.

E. USB Controller(USBC)

F. USB Transceiver

B
Diagram
Figure 5. USB Controller Top Level Block
USB communication on the ARM7 syystem side is fully
handled by the USB Controller while the ARM7 core
U
Controller has
focuses entirely on data processing. The USB
three main components: the USB Core Logic, the Endpoint
Register File, and the USB Function.

Figure 7. EVB-U
USB3300 [14]
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The USB Transceiver hardware is exteernal to the FPGAbased system. It handles the electrical andd physical layer of
the USB communication. Shown in Fig. 7 is the Evaluation
board of the SMSC USB3300 transceiver.

Fig. 9 shows the integrationn of all the modules of the

design. When the FPGA-based system and USB Transceiver
is connected to the Host PC, thee PC must detect the attached
device and begin enumeration. A USB Controller stub was
loaded into the FPGA for this too be possible.

G. Software
G.1 Application Software
Figure 10. USB Transceiverr Detection and High Speed
Initializzation

Figure 11. USB Trace of Trransceiver Initialization and

Start of Enuumeration

Figure 8. GUI for the Applicatiion Software

l
software that
The Application Software is the top layer
communicates with the end user on the Host
H PC. It is coded
in C using DevC++.
G.2 libUSB
libUSB provides drivers and a librarry of C functions
specifically for custom USB devices andd peripherals. It is
important for detecting and communnicating with the
attached ARM7 system.
G.3 USB Trace and NetMon
The Windows 7 operating system is equipped with its
own USB event tracing mechanism on a live system and log
recorder. Netmon, a Microsoft Network Monitor software
allows the user to view this log. It monittors the exchanged
data structures on the USB traffic.

Figure 12. USB Trace of Traansceiver Set in High Speed

Modde

YSIS
IV. RESULTS AND ANALY

Figure 13. Start off Control Transfers

C
Pro waveform and
Fig. 10, 11 and 12 shows the Chipscope
USB trace screenshots of the host PC successfully detecting
the USB transceiver as a Highh speed device. After device
detection, Control transfer can now ensue as shown in Fig.
s
figure, the Enumeration
13. However, as shown in the same
process was suspended, causinng the USB communication
not to commence. We attributee this failure to:
1. Copper Wire Interconneect
Ideally, the transceiver haardware requires a 100-pin
T&MT connector that allow
ws the transceiver to be a

Figure 9. Final System Implementation

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daughter card of the FPGA board. Since the Virtex-5 FPGA
does not have this connector, copper wires were used to
connect the transceiver pins to the Virtex-5 IO header pins,
as shown in Figure 9. This design decision introduced some
unwanted delays to the system.

accountable. This includes interconnect delays, clock

reliability, and logic delays. Due to these factors, complete
USB communication was not achieved.
The designed USB Controller has a recovery mechanism
in case of erroneous data through CRC and checksum
checking, data retransmission, and time-out mechanisms.
However, it does not support recovery from a bad physical
and link layer (i.e. interconnect and delay problems). In
High-Speed operations like USB, data integrity and
reliability is a necessity because the boon that comes from
fast data delivery can be marred by occasional data
retransmissions and unwarranted data disposal due to errors.
Successfully implementing a USB Controller for an
ARM7 system further enhances the ARM7 cores
capabilities. Other peripherals like PS2, I2C, and SPI can
also be implemented and thus, create a system-on-a-chip.
The addition a USB interface would allow the ARM7 to be
used in various applications.

2. Clock Reliability
Clock reliability poses a challenge to the whole system
design. The architecture of the design is built so that it
receives clock signal from one source, that of the external
transceiver. However, since this clock source drives the
clock signal of the whole system including the transceiver,
clock skews and clock signal attenuations provide
considerable drawbacks.
3. FPGA Internal Logic Delay
Figure 14 shows the post-route synthesis simulation of an
8-bit register with a 60 MHz clock implemented on a
Virtex-5 FPGA board. It can be deduced from the figure that
the latch delay from the time the positive edge of the clock
has triggered to the changing of the output signal is
approximately 6 ns, which is very near to the negative edge
of the clock. This design constraint has many repercussions.
First, since the system operates at a 60 MHz clock or 16.67
ns period, a 6 ns delay can induce setup and hold time
violations. Also, because of this inherent delay, overall
timing and synchronization between the transceiver
hardware and FPGA-based system is compromised. The
system will suffer unwarranted data errors and misaligned
control signals (i.e dir, nxt, stp) that will eventually lead to
miscommunication and faulty operation.

VI. REFERENCES
[1] Fatemeh Arbab Jolfaei et al., High Speed USB 2.0
Interface for FPGA Based Embedded Systems, Isfahan
University of Technology, Department of Electrical &
Computer Engineering
[2] Universal Serial Bus Specifications Revision 2.0
[3] www.usb.org [online]
[4] CY7C68001 EZ-USB SX2 High-Speed USB Interface
Device Datasheet, Cypress Corp., Jun 2005
[5] Jan Axelson, USB Complete - Everything you need to
develop custom USB peripherals, Lakeview research, 3rd
Edition, Aug 2005
[6] Virtex 5 ML507 Evaluation Platform, Xilinx Corp.
[7] Luna et al., Implementation of the Complete
ARM7TDMI-S Instruction Set on a Debug Capable
Core, Department of Electrical and Electronics
Engineering, University of the Philippines,
Diliman,
October 2008.
[8] Posada-Gomez et al., USB bulk transfers between a PC
and a PIC microcontroller for
embedded
applications, Instituto Tecnologico de Orizaba, Division
of Research and Postgraduate Studies, Orizaba,
Veracruz, Mexico, 2008
[9] Cypress TX2 USB 2.0 UTMI Transceiver Datasheet,
May 2 2006, Cypress Semiconductor Corp.
[10] Kouyama et al., The Design of a USB Device Controller
IYOYOYO, Graduate School of Engineering, Tokai
University
[11] Rudolf Usselmann, USB Function IP Core Revision 1.5,
January 27, 2002
[12] ISP1505A; ISP1505C ULPI Hi-Speed Universal Serial
Bus host and peripheral transceiver Rev. 01, October
19, 2006
[13] CY3688 MoBL-USB TX32UL USB 2.0 ULPI
Transceiver, September 22, 2010
[14] EVB-USB3300 User Manual Rev. 4.0, Dec 18, 2006
[15] UTMI + Low Pin Interface (ULPI) Specification
Revision 1.1, Oct. 20, 2004

Figure 14. Post-route Latch delay

V. CONCLUSION
This project demonstrates that implementing a USB
Controller system for the ARM7 system on an FPGA-board
can be done. The designed USB controller and USB
interface only accounts to 10 % of the over-all resource
usage on a Virtex-5 FPGA board. It also needs external
transceiver hardware to handle the physical and electrical
layers of USB communication. USB 2.0 specification
compliance of the designed USB controller is limited to
aspects involving basic data transfers.
During USB communication between the Host PC and
FPGA-based system, multiple factors have to be taken into
account. To achieve correct operation, timing and
synchronization between the FPGA-based system and the
external transceiver should be given proper consideration.
With a 60 MHz system clock, some timing problems that are
negligible on slower systems become more apparent and
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