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FlipFlop
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Adigitalcomputerneedsdeviceswhichcanstoreinformation.Aflipflopisabinarystoragedevice.Itcanstore
binarybiteither0or1.IthastwostablestatesHIGHandLOWi.e.1and0.Ithasthepropertytoremainin
onestateindefinitelyuntilitisdirectedbyaninputsignaltoswitchovertotheotherstate.Itisalsocalled
bistablemultivibrator.
Thebasicformationofflipflopistostoredata.Theycanbeusedtokeeparecordorwhatvalueofvariable
(input,outputorintermediate).Flipfloparealsousedtoexercisecontroloverthefunctionalityofadigital
circuiti.e.changetheoperationofacircuitdependingonthestateofoneormoreflipflops.Thesedevicesare
mainlyusedinsituationswhichrequireoneormoreofthesethree.
Operations,storageandsequencing.

LatchFlipFlop
TheRS(ResetSet)flipflopisthesimplestflipflopofallandeasiesttounderstand.Itisbasicallyadevice
whichhastwooutputsoneoutputbeingtheinverseorcomplementoftheother,andtwoinputs.Apulseon
oneoftheinputstotakeonaparticularlogicalstate.Theoutputswillthenremaininthisstateuntilasimilar
pulseisappliedtotheotherinput.ThetwoinputsarecalledtheSetandResetinput(sometimescalledthe
presetandclearinputs).
SuchflipflopcanbemadesimplybycrosscouplingtwoinvertinggateseitherNANDorNORgatecouldbe
usedFigure1(a)showsonRSflipflopusingNANDgateandFigure1(b)showsthesamecircuitusingNOR
gate.

Figure1:LatchRSFlipFlopUsingNANDandNORGates
TodescribethecircuitofFigure1(a),assumethatinitiallybothRandSareatthelogic1stateandthat
outputisatthelogic0state.
Now,ifQ=0andR=1,thenthesearethestatesofinputsofgateB,thereforetheoutputsofgateBisat1
(makingittheinverseofQi.e.0).TheoutputofgateBisconnectedtoaninputofgateAsoifS=1,both
inputsofgateAareatthelogic1state.ThismeansthattheoutputofgateAmustbe0(aswasoriginally
specified).Inotherwords,the0stateatQiscontinuouslydisablinggateBsothatanychangeinRhasno

effect.Alsothe1stateat
iscontinuouslyenablinggateAsothatanychangeSwillbetransmitted
throughtoQ.TheaboveconditionsconstituteoneofthestablestatesofthedevicereferredtoastheReset
statesinceQ=0.
NowsupposethattheRSflipflopintheResetstate,theSinputgoesto0.TheoutputofgateAi.e.Qwillgo

to1andwithQ=1andR=1,theoutputofgatesB(
)willgoto0with
now0gateAisdisabled
keepingQat1.Consequently,whenSreturnstothe1stateithasnoeffectontheflipflopwhereasachange
inRwillcauseachangeintheoutputofgateB.Theaboveconditionsconstitutetheotherstablestateofthe
device,calledtheSetstatesinceQ=1.NotethatthechangeofthestateofSfrom1to0hascausedtheflip
floptochangefromtheResetstatetotheSetstate.
Thereisanotherinputconditionwhichhasnotyetbeenconsidered.ThatiswhenboththeRandSinputsare

takentothelogicstate0.WhenthishappensbothQand
willbeforcedto1andwillremainsofaras
longasRandSarekeptat0.Howeverwhenbothinputsreturnto1thereisnowayofknowingwhetherthe

flipflopwilllatchintheResetstateortheSetstate.Theconditionissaidtobeindeterminatebecauseofthis
indeterminatestategreatcaremustbetakenwhenusingRSflipfloptoensurethatbothinputsarenot
instructedsimultaneously.
Table1:ThetruthtablefortheNANDRSflipflop
Initial
Conditions

Inputs
(Pulsed)

FinalOutput

indeterminate

indeterminate

ormoresimplyshowninTable2
Table2:SimpleNANDRSFlipFlopTruth
Table
S

indeterminate

Set(1)

Reset(0)

NoChange

WhenNORgateareusedtheRandSinputsaretransposedcomparedwiththeNANDversion.Alsothestable
statewhenRandSareboth0.Achangeofstateiseffectedbypulsingtheappropriateinputtothe1state.
TheindeterminatestateisnowwhenbothRandSaresimultaneouslyatlogic1.Table3showsthis
operation.
Table3:NORGateRSFlipFlopTruthTable
S

R
0

Q
0

NoChange

Reset(0)

Set(1)

Indeterminate

ClockedRSFlipFlop
TheRSlatchflipfloprequiredthedirectinputbutnoclock.Itisveryusefulltoaddclocktocontrolprecisely
thetimeatwhichtheflipflopchangesthestateofitsoutput.
IntheclockedRSflipfloptheappropriatelevelsappliedtotheirinputsareblockedtillthereceiptofapulse
fromanothersourcecalledclock.Theflipflopchangesstateonlywhenclockpulseisapplieddependingupon
theinputs.ThebasiccircuitisshowninFigure2.ThiscircuitisformedbyaddingtwoANDgatesatinputsto
theRSflipflop.InadditiontocontrolinputsSet(S)andReset(R),thereisaclockinput(C)also.

Figure2:ClockedRSFlipFlop
Table4:ThetruthtablefortheClockedRSflipflop
InitialConditions

Inputs(Pulsed)

FinalOutput

Q(t+1)

indeterminate

indeterminate

TheexcitationtableforRSflipflopisverysimplyderivedasgivenbelow
Table5:ExcitationtableforRSFlipFlop
S

NoChange

Reset(0)

Set(1)

Indeterminate

DFlipFlop
ADtype(Dataordelayflipflop)hasasingledatainputinadditiontotheclockinputasshowninFigure3.

Figure3:DFlipFlop
Basically,suchtypeofflipflopisamodificationofclockedRSflipflopgatesfromabasicLatchflipflopandNOR
gatesmodifyitintoaclockRSflipflop.TheDinputgoesdirectlytoSinputanditscomplementthroughNOT
gate,isappliedtotheRinput.
ThiskindofflipfloppreventsthevalueofDfromreachingtheoutputuntilaclockpulseoccurs.Theactionof
circuitisstraightforwardasfollows.
Whentheclockislow,bothANDgatesaredisabled,thereforeDcanchangevalueswithoutaffectingthe
valueofQ.Ontheotherhand,whentheclockishigh,bothANDgatesareenabled.Inthiscase,Qisforced
equaltoDwhentheclockagaingoeslow,QretainsorstoresthelastvalueofD.Thetruthtableforsuchaflip
flopisasgivenbelowintable6.
Table6:TruthtableforDFlipFlop
S

Q(t+1)

TheexcitationtableforDflipflopisverysimplyderivedgivenasunder.

Table7:ExcitationtableforDFlipFlop
S

Q
0

JKFlipFlop
OneofthemostusefulandversatileflipflopistheJKflipfloptheuniquefeaturesofaJKflipflopare:
1. IftheJandKinputarebothat1andtheclockpulseisapplied,thentheoutputwillchangestate,
regardlessofitspreviouscondition.
2. IfbothJandKinputsareat0andtheclockpulseisappliedtherewillbenochangeintheoutput.
Thereisnoindeterminatecondition,intheoperationofJKflipflopi.e.ithasnoambiguousstate.The
circuitdiagramforaJKflipflopisshowninFigure4.

Figure4:JKFlipFlop
WhenJ=0andK=0
TheseJandKinputsdisabletheANDgates,thereforeclockpulsehavenoeffectontheflipflop.Inother
words,Qreturnsitlastvalue.
WhenJ=0andK=1,
TheupperANDgateisdisabledthelowerANDgateisenabledifQis1therefore,flipflopwillbereset(Q=0,

=1)ifnotalreadyinthatstate.
WhenJ=1andK=0

ThelowerANDgateisdisabledandtheupperANDgateisenabledif

settheflipflop(Q=1,

=0)ifnotalreadyset

isat1,Asaresultwewillbeableto

WhenJ=1andK=1
IfQ=0thelowerANDgateisdisabledtheupperANDgateisenabled.ThiswillsettheflipflopandhenceQ
willbe1.OntheotherhandifQ=1,thelowerANDgateisenabledandflipflopwillberesetandhenceQwill
be0.Inotherwords,whenJandKarebothhigh,theclockpulsescausetheJKflipfloptotoggle.Truthtable
forJKflipflopisshownintable8.

Table8:ThetruthtablefortheJKflipflop
InitialConditions

Inputs(Pulsed)

FinalOutput

Q(t+1)

TheexcitationtableforJKflipflopisverysimplyderivedasgivenintable8.

Table6:ExcitationtableforJKFlipFlop
S

NoChange

Toggle

TFlipFlop
AmethodofavoidingtheindeterminatestatefoundintheworkingofRSflipflopistoprovideonlyoneinput(
theTinput)such,flipflopactsasatoggleswitch.Togglemeanstochangeinthepreviousstagei.e.switchto
oppositestate.ItcanbeconstructedfromclockedRSflipflopbeincorporatingfeedbackfromoutputtoinput
asshowninFigure5.

Figure5:TFlipFlop
Suchaflipflopisalsocalledtoggleflipflop.InsuchaflipflopatrainofextremelynarrowtriggersdrivestheT
inputeachtimeoneofthesetriggers,theoutputoftheflipflopchangesstage.ForinstanceQequals0just
beforethetrigger.ThentheupperANDgateisenableandthelowerANDgateisdisabled.Whenthetrigger
arrives,itresultsinahighSinput.
ThissetstheQoutputto1.WhenthenexttriggerappearsatthepointT,thelowerANDgateisenabledand
thetriggerpassesthroughtotheRinputthisforcestheflipfloptoreset.
Sinceeachincomingtriggerisalternatelychangedintothesetandresetinputstheflipfloptoggles.Ittakes
twotriggerstoproduceonecycleoftheoutputwaveform.Thismeanstheoutputhashalfthefrequencyof
theinputstatedanotherway,aTflipflopdividestheinputfrequencybytwo.Thussuchacircuitisalsocalled
adividebytwocircuit.
Adisadvantageofthetoggleflipflopisthatthestateoftheflipflopafteratriggerpulsehasbeenappliedis
onlyknownifthepreviousstateisknown.ThetruthtableforaTflipflopisasgiventable7.
Table7:TruthtableforTFlipFlop
Qn

Qn+1

T
0

TheexcitationtableforTflipflopisverysimplyderivedasshowninTable8.
Table8:ExcitationtableforT
FlipFlop
T

Q
0

Qn

1
n

GenerallyTflipflopICsarenotavailable.ItcanbeconstructedusingJK,RSorDflipflop.Figure6showsthe

relationofTflipflopusingJKflipflop.

ADtypeflipflopmaybemodifiedbyexternalconnectionasaTtypestageasshowninFigure7.SincetheQ
logicisusedasDinputtheoppositeoftheQoutputistransferredintothestageeachclockpulse.Thusthe

stagehavingQ0transistors
=1,Providingatoggleaction,ifthestagehadQ=1theclockpulsewould
resultinQ=0beingtransferred,againprovidingthetoggleoperation.TheDtypeflipflopconnectedasin
Figure6willthusoperateasaTtypestage,complementingeachclockpulse.

MasterSlaveFlipFlop
Figure8showstheschematicdiagramofmastersloaveJKflipflop

Figure8:MasterSlaveJKFlipFlop
Amasterslaveflipflopcontainstwoclockedflipflops.Thefirstiscalledmasterandthesecondslave.When
theclockishighthemasterisactive.Theoutputofthemasterissetorresetaccordingtothestateofthe
input.Astheslaveisincativeduringthisperioditsoutputremainsinthepreviousstate.Whenclockbecomes
lowtheoutputoftheslaveflipflopchangesbecauseitbecomeactiveduringlowclockperiod.Thefinaloutput
ofmasterslaveflipflopistheoutputoftheslaveflipflop.Sotheoutputofmasterslaveflipflopisavailableat

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