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Reducing Regression Turnaround Time using

Multi-Snapshot Incremental Elaboration
Anantha Ramanand Garlapati, Cirrus Logic
Babak Zakeri, Cadence Design Systems

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Agenda
Problem Statement and Motivation
Introduction to MSIE
Application of MSIE to UVM based Verification Environments

Enhancements and Results

Conclusions and Future Work

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Problem Statement
Complexity of Chips leading to
Huge Regression Turn Around Time for
full Chip RTL ,GATE and Mixed Signal Simulations.
Work space needed for compile libraries
typically GBs at Chip Level
Different configurations of Design/Testbench

All the mentioned problems can cause

A Barrier for productivity
An Impact on the Time to Market

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Motivation
Reduce overall TAT for
Regressions
Simulation Duration

At least 50%

A biggest bottle neck in Verification Execution.

one size fits all solution for all Subsystems

CHIP RTL/GLS/MS.
Verification levels
Re-usable flow
Avoid the need for a Test library.
No additional costs.

Single Simulations
Regressions

Breaks entire regression if there are erroneous check-ins

by test developers.
Utilising the available options.

Considering all these Opted for MSIE

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Introduction
to
Multi-Snapshot Incremental Elaboration

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Traditional Simulation Flow

Compilation
Phase

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All the source code including libraries are compiled.

Module instances are resolved, Parameters and macros processed, Timing info
annotated, etc.
Any change in the design, need to go through full elaboration. Repetitive in
Elaboration
Regressions.
Phase
A simulation image is created for the next step.

Simulation
Phase

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Stimulating the design.

Functional scenarios based on test.

MSIE flow at a Higher level

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Identify Unstable and Stable portions and partition them.

Partition the
Design/Testbench

Primary
Snapshots

Incremental
Snapshots

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Major and Stable portions compiled elaborated once to create primary

snapshots.

Compile - elaborate the unstable portion as Incremental snapshots and run the
simulation.

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Application of MSIE to UVM Based

Verification Environments

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Testbench Partitioning
Primary Instantiating Incremental
Most effective for regressions.
Primary Snapshot : Ex: DUT+ most of UVM TB stable.
Incremental Snapshot: Only small portion of test changing.

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Customizing Testbench
1

TestBench
Partitioning
TB_Top
Primary Top

Test case
Incremental
Top.

UVM Packages

Package imports

DUT and other

model
instances.

run_test()

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Href files

Automation

To handle
OOMRs

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Primary
Snapshot

Incremental
Snapshot

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Different configurations of the

Design/Testbench.
Use of multiple Third-party
VIPS/UVCs.
Gate level Corners with SDF
annotation.
Control macro enabled code in
Primary Partition.

Solution

Requirements

Multiple Primary Snapshots

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Create multiple primary snapshots.

Ex:
Normal [Default]
Slimbus Enabled
GLS_MAX
GLS_MIN
Automation for each simulation to
point respective primary snapshot.

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Enhancements & Results

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Simulation Flow Enhancement at Cirrus with MSIE

Legacy
Test 1

Elaborate

Simulation

Test 3

Compile

Compile

Elaborate

Compile

Elaborate

Simulation
Simulation
Simulation

Test 3

Simulation

Test 2

Elaborate

Incremental Snapshots

Simulation

Test 1000

Created n Primary Snapshots

Test 1000

Test 1

Compile

Test 2

New

Progression

Progression

Created 1000 Simulation Snapshots

Regression Start Time

Time

Time

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Regression Start Time

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Overall Regression TAT

Mode of Design

Overall Duration
[Legacy]

Overall Duration
[MSIE]

% Improvement

CHIP RTL
[1000 Tests]

~24 Hrs

~12 Hrs

50%

CHIP GLS
[140 Tests Min & Max]

~23 Hrs

~11 Hrs

52.1%

CHIP MS
[325 Tests]

~9 Hrs

~4Hrs

55.55%

-- 30 Tests in Parallel.

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Improvement in Elaboration Time

Single Simulation Statistics
Mode of Design

Average
Elaboration Time
[Legacy]

Average
Elaboration Time
[MSIE]

% Improvement

CHIP RTL - Normal

820s

11s

98.6%

CHIP RTL Slimbus

1006

9s

99%

CHIP GLS
[Min and Max]

1262s

25s

98%

720s

9s

98.75%

CHIP MS
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Additional Advantages
Runtime disk Memory Consumption with each Test
Enables more parallel simulations running without memory crashes.
Mode of Design

Disk space
[Legacy]

Disk space
[MSIE]

CHIP RTL

1.5GB

10MB

CHIP GLS

2GB

17MB

CHIP MS

1.3GB

9MB

Reduced load on the computing farm in proportion to the TAT

saving.
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Conclusions and Future Work

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Conclusions
Successfully utilised in couple of Projects.

Achieved a Partition approach which works for all levels of

verification.
Significant reduction in the regression TAT.
Overnight regressions.

Primary Snapshots re-used for both Single simulations and

regressions.

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Future Work
Extend MSIE to CPF simulations.
Make MSIE a default flow for all Projects.

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Thank You
Queries!!

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