CIRCUIT DESIGN PROCESS

MOS Layers, Stick Diagram, Design

rules and layout

9/4/2015

CMOS VLSI DESIGN

Circuit Design Process

MOS layers
Stick diagrams
Design rules and layout
Lambda-based design and other rules
Examples, layout diagrams symbolic diagrams

9/4/2015

CMOS VLSI DESIGN

Measure Twice and Fabricate Once

04-09-2015

Logic to Layouts
Frontend:
Simulation
Verification
Backend:
Turning codes or schematics into Masks-Gates
to Layouts.

04-09-2015

MOS Layers

1.
2.
3.
4.

MOS circuits are formed on four basic layers:

N-diffusion
P-diffusion
Polysilicon
Metal
They are isolated by a thick or thin SiO2 insulating layer
When polysilicon crosses diffusion transistors are formed
Some process use second metal layer and second polysilicon
Different layers are joined together at contact

9/4/2015

CMOS VLSI DESIGN

STICK DIAGRAM & Layout

Stick diagram: Conveys layer information through the color code.
Layout: Symbolic representation of stick diagram which reflect the
topology of the actual output.

N+

9/4/2015

CMOS VLSI DESIGN

N+

Color Coding

9/4/2015

CMOS VLSI DESIGN

Color Coding

9/4/2015

CMOS VLSI DESIGN

STICK DIAGRAM Notations

Metal 1
poly
ndiff

pdiff
Can also draw
in shades of
gray/line style.

Similarly for contacts, via, tub etc..

9/4/2015

CMOS VLSI DESIGN

STICK DIAGRAM Rules

Rule 1.
When two or more sticks of the same type
cross or touch each other that represents
electrical contact.

9/4/2015

CMOS VLSI DESIGN

10

STICK DIAGRAM Rules

Rule 2.
When two or more sticks of different type cross or
touch each other there is no electrical contact.
(If electrical contact is needed we have to show the connection explicitly).

9/4/2015

CMOS VLSI DESIGN

11

STICK DIAGRAM Rules

Rule 3
When a poly crosses diffusion it represents a
transistor.

Note: If a contact is shown then it is not a transistor.

9/4/2015

CMOS VLSI DESIGN

12

STICK DIAGRAM Rules

Rule 4
In CMOS a demarcation line is drawn to avoid touching of p-diff
with n-diff.
CMOS Technology (Demarcation Line p-Well Boundary)
Transistor above demarcation line PMOS
Transistor below demarcation line NMOS

9/4/2015

CMOS VLSI DESIGN

13

Rules to be followed

9/4/2015

CMOS VLSI DESIGN

14

STICK DIAGRAM(nMOS Process)

9/4/2015

CMOS VLSI DESIGN

15

STICK DIAGRAM(CMOS P-Well Process)

9/4/2015

CMOS VLSI DESIGN

16

STICK DIAGRAM
VDD

VDD
X

X
Gnd

9/4/2015

Gnd
CMOS VLSI DESIGN

17

STICK DIAGRAM

9/4/2015

CMOS VLSI DESIGN

18

STICK DIAGRAM Representation

1. Two Transistors in series

9/4/2015

CMOS VLSI DESIGN

19

STICK DIAGRAM Representation

2. Two Transistors in parallel

9/4/2015

CMOS VLSI DESIGN

20

N-MOS Design Style

Single metal, single polysilicon nMOS technology
Layout of nMOS involves:
N-diffusion and other thin oxide regions (Green)
Polysilicon 1 (red)
Metal-1 (Blue)
Implant (Yellow)
Contacts (black or brown)
1. First step is to draw metal vdd & Gnd rails.
2.Thin oxide (n-diffusion) paths are drawn between rails and
appropriate Contacts are made.

9/4/2015

CMOS VLSI DESIGN

21

STICK DIAGRAM

9/4/2015

CMOS VLSI DESIGN

22

Stick diagram
2 INPUT NOR GATE
A

N1

N2

Vout

OFF

OFF

ON

OFF

ON

ON

ON

OFF

ON

ON

ON

ON

2 INPUT NAND GATE

9/4/2015

CMOS VLSI DESIGN

N1

N2

Vout

OFF

OFF

ON

OFF

ON

ON

ON

OFF

ON

ON

ON

ON

0
23

Stick Diagram
Write the nMOS stick diagram for the following
1. f=(xy+x)
2. 3 input AND gate
3. 3 input OR gate
4. f=AB+C

9/4/2015

CMOS VLSI DESIGN

24

CMOS design style

CMOS design style are based on the contribution

made by MEAD and CONWAY
It do not use any depletion mode Transistor
NMOS TransistorDriver
PMOS TransistorLoad
CMOS Technology (Demarcation Line p-Well Boundary)
Transistor above demarcation line PMOS
Transistor below demarcation line NMOS

Diffusion paths must not cross the demarcation line

P-diffusion and n-diffusion must not join directly
N and p diffusion are normally joined by metal where connection is
needed
9/4/2015

CMOS VLSI DESIGN

25

2-Input NAND Gate

9/4/2015

CMOS VLSI DESIGN

N1

N2

P1

P2

Vou
t

OFF OFF ON

ON

OFF ON

OFF 1

ON

OFF OFF ON

ON

ON

ON

OFF OFF 0

26

2 input NOR Gate

9/4/2015

N1

P1

P2

Vo
ut

OFF OFF ON

ON

OFF ON

OFF 0

ON

OFF OFF ON

ON

ON

CMOS VLSI DESIGN

N2

ON

OFF OFF 0

27

2 input NOR Gate-STICK DIAGRAM

9/4/2015

CMOS VLSI DESIGN

28

STICK DIAGRAM
Write the stick diagram for the schematic
given:

9/4/2015

CMOS VLSI DESIGN

29

STICK DIAGRAM
Power

Out

C
B
Ground

9/4/2015

CMOS VLSI DESIGN

30

2 Input XOR Gate

9/4/2015

CMOS VLSI DESIGN

31

2 Input XNOR Gate

9/4/2015

CMOS VLSI DESIGN

32

2:1 MULTIPLXER
Write the schematic and stick diagram for 2:1 MUX
F=Po.S + P1.S
where, A & B Inputs S = Select input

9/4/2015

CMOS VLSI DESIGN

33

Euler Path
Euler graph is used to write the stick diagram for
the complex gates

9/4/2015

CMOS VLSI DESIGN

34

Euler Path

9/4/2015

CMOS VLSI DESIGN

35

Euler Path

9/4/2015

CMOS VLSI DESIGN

36

Euler Path

9/4/2015

CMOS VLSI DESIGN

37

Euler Path

9/4/2015

CMOS VLSI DESIGN

38

Euler path

9/4/2015

CMOS VLSI DESIGN

39

Euler path

9/4/2015

CMOS VLSI DESIGN

40

Euler path

9/4/2015

CMOS VLSI DESIGN

41

Euler path

9/4/2015

CMOS VLSI DESIGN

42

Euler Path

9/4/2015

CMOS VLSI DESIGN

43

Example-2

9/4/2015

CMOS VLSI DESIGN

44

Euler Path

9/4/2015

CMOS VLSI DESIGN

45

Stick diagram

9/4/2015

CMOS VLSI DESIGN

46

Layout Technique using Euler Graph Method

Euler Graph Technique can be used to

determine if any complex CMOS gate
can be physically laid out in an
optimum fashion
Start with either NMOS or PMOS tree
(NMOS for this example) and connect
lines for transistor segments, labeling
devices, with vertex points as circuit
nodes.
Next place a new vertex within each
confined area on the pull-down graph
and connect neighboring vertices with
new lines, making sure to cross each
edge of the pull-down tree only once.
The new graph represents the pull-up
tree and is the dual of the pull-down
tree.

The stick diagram at the left (done

with arbitrary gate ordering) gives a
very non-optimum layout for the
CMOS gate above.

Layout with Optimum Gate Ordering

By using the Euler path approach to re-order the

polysilicon lines of the previous chart, we can obtain an
optimum layout.
Find a Euler path in both the pull-down tree graph and the
pull-up tree graph with identical ordering of the inputs.
Euler path: traverses each branch of the graph exactly once!

By reordering the input gates as E-D-A-B-C, we can obtain

an optimum layout of the given CMOS gate with single
actives for both NMOS and PMOS devices (below).

CMOS 1-Bit Full Adder Circuit

1-Bit Full Adder logic function:

Sum = A XOR B XOR C
= ABC + ABC + ABC + ABC
Carry_out = AB + AC + BC
Exercise: Show that the sum function
can be written as shown at left
Sum = ABC + (A + B + C) carry_out

This alternate representation of the

sum function allows the 1-bit full adder
to be implemented in complex CMOS
with 28 transistors, as shown at left
below.
Carry_out internal node is used as an
input to the adder complex CMOS gate
Exercise: Show that the two P-trees in
the complex CMOS gates of the
carry_out and sum are optimizations of
the proper dual derivations from the
two N-tree networks.

CMOS Full Adder Layout (Complex Logic)

Mask layout of 1-bit full adder circuit is shown below

A layout designed with Euler method shows that the carry_out inverter requires separate
active shapes, but all other N (and P) transistors were laid out in a single active region
Layout below is non-optimized for performance
All transistors are seen to be minimum W/L

Design of n-bit full adder:

A carry ripple adder design uses the carry_out of stage k as the carry_in for stage k+1
Typically the layout is modified from that shown below in order to use larger transistors for the
carry_out CMOS gate in order to improve the performance of the ripple bit adder
See Fig. 7.30 in Kang and Leblebici

1 bit shift register

Schematic of 1 bit shift register

S & S of first TG is fed with clk-1

S & S of second TG is fed with clk-2
9/4/2015
Clk-1 is in not phase withCMOS
clk-2
VLSI DESIGN

51

1 bit shift register

9/4/2015

CMOS VLSI DESIGN

52

1 bit shift register

9/4/2015

CMOS VLSI DESIGN

53

1 bit shift register

9/4/2015

CMOS VLSI DESIGN

54

1 bit shift register

9/4/2015

CMOS VLSI DESIGN

55

1 bit shift register

9/4/2015

CMOS VLSI DESIGN

56

1 bit shift register

9/4/2015

CMOS VLSI DESIGN

57

Why we need design rules

9/4/2015

CMOS VLSI DESIGN

58

Lamda Based Design Rules

Design Rules:
Allow translation of circuit diagram (Stick diagram or
symbolic diagram) into the actual geometry in silicon.
Effective interface between circuit/system designer &
process engineer.
To obtain a circuit with optimum yield (functional circuits
versus non functional circuits) without comprising
reliability & area.
To provide best comprise between performance & yield.
It mainly focuses on geometrical reproduction of features
& interaction between layers.
Approaches: Micron design rule & Lamda based design
rules.
9/4/2015

CMOS VLSI DESIGN

59

Lamda Based Design Rules

Lamda Based Design Rules (Proposed Mead
& Conway) based on single parameter
Linear feature.
Permits first order scaling.
Revolution of the complete wafer implementation
process.
All parts in all layers are dimensioned in units.
1.0 um Technology min features size 2
Therefore, = 0.5 um.
9/4/2015

CMOS VLSI DESIGN

60

STICK DIAGRAM(nMOS Process)

9/4/2015

CMOS VLSI DESIGN

61

STICK DIAGRAM(CMOS P-Well Process)

9/4/2015

CMOS VLSI DESIGN

62

Design Rules for wires(nMOS &pMOS)

9/4/2015

CMOS VLSI DESIGN

63

Design Rules for wires

9/4/2015

CMOS VLSI DESIGN

64

9/4/2015

CMOS VLSI DESIGN

65

A N-well rules
A1 =10
A2= 6 wells at same potential
A2=8 wells at different potentials

9/4/2015

CMOS VLSI DESIGN

66

B Active Area Rules

Active Area Rules(n-diffusion, p-diffusion)

B1= 3
B2=3
B3=5
B4=3
B5=5
B6=3

9/4/2015

CMOS VLSI DESIGN

67

Transistor Design Rules nMOS, pMOS

& CMOS

9/4/2015

CMOS VLSI DESIGN

68

Transistor Design Rules nMOS, pMOS

& CMOS

9/4/2015

CMOS VLSI DESIGN

69

Contact cuts
When making contacts between polysilicon
and diffusion in nmos circuits there are 3
possible approaches
Poly to metal then metal to diffusion
Buried contact poly to diffusion
Butting Contact(poly to diff using metal)

9/4/2015

CMOS VLSI DESIGN

70

Contact cuts

9/4/2015

CMOS VLSI DESIGN

71

Contacts polysilicon to diffusion

9/4/2015

CMOS VLSI DESIGN

72

Cross section through some

contact structures

9/4/2015

CMOS VLSI DESIGN

73

2 input NAND gate

9/4/2015

CMOS VLSI DESIGN

74

2 input NOR gate

9/4/2015

CMOS VLSI DESIGN

75

Other design rules

Double Metal MOS process Rules
CMOS fabrication is much more complex than
nMOS fabrication
2 um Double metal, Double poly.
CMOS/BiCMOS Rules
1.2um Double Metal single poly.CMOs rules

9/4/2015

CMOS VLSI DESIGN

76

XOR Implementations using CMOS Transmission

Gates

The top circuit implements an XOR

function with two CMOS
transmission gates and two
inverters
8 transistors total (4 fewer than a
complex CMOS implementation)

The XOR can also be implemented

with only 6 transistors with one
transmission gate, one standard
inverter, and one special inverter
gate powered from B to B (instead
of Vdd and Vss) and inserted
between A and the output F.