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I. I NTRODUCTION
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 10, OCTOBER 2013
II. E XPERIMENT
The HEMT structures used in this paper are grown on
c-plane sapphire substrates. The layer structure for
AlGaN/GaN HEMT includes GaN buffer layer of 1-m
thickness, AlN spacer layer of 1-nm, and AlGaN barrier layer
of 24-nm thickness with Al mole fraction of 26%. The layer
structure for AlInN/GaN HEMT includes GaN buffer layer of
2-m thickness, AlN spacer layer of 1-nm, AlInN barrier
layer of 10-nm thickness with Al mole fraction of 83% and
Si-doped GaN capping layer of 2-nm thickness.
The samples were first degreased in organic solvents.
Following this, mesa etching was carried out in BCl3 /Cl2
inductively coupled plasma with photoresist as mask. The
mesa etch depth was 300 nm on both the samples. After
mesa etching, the resist mask was stripped and the samples
were immersed in ammonium sulfide solution with excess
sulfur [(NH4 )2 SX , 40% sulfur]. This not only removes the
native oxide but also passivates the surface and avoids the
formation of oxide. After this step, photoresist was coated
and windows were opened for ohmic contacts. Before loading
the samples into the metallization chamber, the samples were
immersed in HCl: H2 O (1:1) to remove any native oxide.
Ti/Al/Au (30 nm/150 nm/50 nm) was then evaporated and
lifted-off. The contact activation annealing was carried out
in a conventional furnace at 550 C for 5 min in nitrogen
ambient. Finally, Schottky contacts were patterned, Ni/Au
(20/75 nm) was evaporated and lifted-off. The devices were
not passivated. The gate length, source-to-gate spacing, and
source-to-drain spacing are 4, 10 and 30 m, respectively.
IV characterization was carried out on dark using Agilents
B1500A semiconductor device analyzer. CapacitanceVoltage
(CV ) characterization was carried out on large area Schottky
diodes fabricated on the same die. The measurements were
qb
J0 = A T exp
kT
Fig. 2. Variation of barrier height ( and ) and ideality factor ( and ) with
temperature obtained from the forward IG VG characteristics of AlGaN/GaN
(solid symbols) and AlInN/GaN (open symbols) HEMT. Inset: typical plots
of ln(J ) versus V for AlGaN/GaN and AlInN/GaN HEMTs.
q t (q E/i )
(2)
JPF = C Eexp
kT
where C is a constant, t is the barrier height for the electron
emission from the trap state and i is the permittivity of
the semiconductor at high frequency. Equation (2) can be
rearranged as
q
q
m(T ) =
kT i
qt
+ ln(C).
c(T ) =
kT
(3)
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Fig. 3. Plot of electric field as a function of gate voltage for AlGaN/GaN and
AlInN/GaN HEMT. Inset: the typical CV and nS versus VG characteristics
for AlGaN/GaN HEMT.
q(b n s )
(4)
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 10, OCTOBER 2013
Fig. 5.
Typical ln(JTAT ) versus (VG V0 ) plots for AlGaN/GaN and
AlInN/GaN HEMTs.
8 2m n (qeff )3
B=
3qh
Fig. 8.
FN tunneling plots for Reg II of the IG VG characteristics of
AlInN/GaN HEMT.
(7)
which indicates that the plot of ln( JFN /E 2 ) versus 1/E yields
a straight line. Fig. 8 shows that it is indeed a straight line
and the value of the effective barrier height extracted from
the slope is 2.3 eV using the effective mass of electron in
AlInN as 0.4m e , where m e is the free electron mass. The
extracted values of barrier height varied slightly (12%) with
temperature.
Apart from these three current components (TE, PF, and FN)
for AlInN/GaN devices, at low reverse bias, a defect-assisted
tunneling current has also been considered as discussed in the
case of AlGaN/GaN devices.
B. Comparison of Gate JV Characteristics of AlGaN/GaN
and AlInN/GaN HEMTs
To compare the J V characteristics, the reverse bias
region is considered first. As discussed in the previous
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 10, OCTOBER 2013
A. Model Formulation
The gate leakage current in AlGaN/GaN and AlInN/GaN
HEMTs can be modeled as a voltage and temperaturedependent current source I in series with a resistance R, where
I = Area (JTE + JPF + JFN + JTAT )
(9)
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