C. U.

SHAH COLLEGE OF ENGINEERING & TECHNOLOGY

Surendranagar - Ahmedabad High-way,
Nr. Kotharia Village, Wadhawancity 363030
Dist:- Surendranagar [Gujarat]

Electronics & Communication Engineering Department

MTech. VESD Semester-III

Subject: SMD

Question Bank
Chapter 1:- Introduction and Motivation
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What is the motivation of SRAM design?

Explain the role of SRAM in the Computer Memory Hierarchy.
Explain the Moores Law of semiconductor memories.
Explain the obstacles on the way of continuous scaling of SRAM.
Write short note on SRAM Test Economics.
Explain Area and Stability of SRAM Design Test.
Enlist the SRAM Design Test Trade-offs and explain any one in detail.
Explain Quality and Yield of SRAM Design Test.
Explain in detail the role of Redundancy in SRAM Design.
Chapter 2:- SRAM Circuit Design and Operation

10. Draw and explain the SRAM block structure in detail.

11. Draw and explain the Four-Transistor (4T) SRAM Cell with Polysilicon Resistor
Load.
12. Draw and explain the Six-Transistor (6T) CMOS SRAM Cell in detail.
13. Explain in detail the Read operation of 6T CMOS SRAM Cell.
14. Explain in detail the Write operation of 6T CMOS SRAM Cell.
15. Draw and explain the Four-Transistor (4T) Loadless SRAM Cell.
Chapter 3:- The SRAM Array
16. Explain the importance of Sense Amplifier and Bit Line Precharge-Equalization in
SRAM Design.
17. Draw and explain the typical circuit with a current-mirror type sense amplifier, a PRL
SRAM cell and precharge/load transistors.
18. Draw and explain the typical circuit with a latch-type sense amplifier, a full CMOS
6T SRAM cell, column mux and precharge.
19. Draw and explain the Write driver circuits used in SRAM.
20. Draw and explain the circuit diagram of Single-stage static and dynamic decoders.
21. Draw and explain the circuit diagram of Multi-stage static 4-16 decoder.
22. Draw and explain the Divided Word Line (DWL) row decoder architecture.
23. Draw and explain the Hierarchical Word Decoding (HWD) row decoder architecture.

24. Draw and explain the circuit diagram of the 4-1 pass-transistor column decoder with a
predecoder.
25. Draw and explain the circuit diagram of the 4-1 tree-based column decoder.
26. Explain with the help of circuit diagram the Address Transition Detector (ATD).
27. Enlist the Basic timing control methods used in SRAMs and explain any one of them
in detail.
28. Explain Direct Clocking timing control method used in SRAMs.
29. Explain with the help of block diagram Delay-Line Based Timing Control method
used in SRAMs.
30. Explain with the help of block diagram Replica-Loop Based Timing Control method
used in SRAMs.
31. Explain Pipelined Timing Control method used in SRAMs.
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