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Dipartimento di Elettronica, Universit di Pavia
Via Ferrata 1, I-27100 Pavia, Italy
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Centro per la Ricerca Scientifica e Tecnologica, Istituto Trentino di Cultura
Via Sommarive 18, I-38055 Povo (TN), Italy
e-mail: JXLGRWRUHOOL#HOHXQLSYLW
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The digital processing unit must process two types of digital signals: those
coming from the absolute traces, and those coming from the incremental ones.
These signals must be handled separately, at least in the first processing stage.
The absolute signal is an 11-bit word in Gray code and represents the 11 most
significant bits of the output data. To provide an output binary-weighted code,
the first processing step is the conversion from Gray code to binary code.
The incremental signal comes from the two outmost traces of the encoder disc.
The two analogue signals corresponding to these two traces are sampled and
converted by two 8-bit analogue-to-digital (A/D) converters with a sampling
frequency of 110 kHz. Due to the rotation of the disc, the two analogue signals
INC5
INC2ABS
OUTBUS
INBUS
SCALE
DEMUX19
(19 bit)
GRAY
ABS11
BIN2ANG16
(16 bit)
GRAY2BIN11
CLOCK
RESET
1ST STAGE
2ND STAGE
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The absolute encoder section of the disc produces 11-bit words in Gray code.
To merge these words together with the binary-weighted 5-bit words
corresponding to the incremental section, conversion into a binary code is
necessary. The Gray2Bin11 cell converts a Gray word ( J Q J Q 1...J1 J 0 ) into a
binary-weighted word ( EQ EQ 1...E1E0 ) in the following way:
EQ = J Q
EL = J L EL +1 , for L = 0, 1, 2, ..., Q 1
This conversion is implemented with EXOR gates [3].
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to the least significant bit (Abs<0>) of the absolute binary code, as is shown in
Fig. 3. To achieve a correct result from the interpolation process, the allowed
maximum frequency of the incremental signal is I inc, max = 2048 Hz, corresponding to 60 rpm. This limitation comes from the sampling frequency used
in the A/D conversion. However, this does not result in performance
degradation of the whole system, because motion control requires a fine
regulation only at very low rotation speed.
13th trace
12th trace
11th bit
10th bit
Angle
Figure 3. Absolute and incremental signals from the outmost four traces
After this linearisation, only 12 samples with 3-bit resolution need to be stored.
The maximum non-linearity error introduced in the interpolation process is
about 1 6 LSB.
EPU16 has been synthesised from VHDL, and its layout has been generated in a
0.8 m CMOS technology. The silicon area occupied by the digital processing
unit (without the A/D converters) is 1.27 mm2.
1
cos(x)
.75
ref(x)
.50
sin(x)
.25
pi/16
pi/8
3pi/16
pi/4
Figure 4. Plot of sin([), cos([) and ref([) for [ [0, / 4] (first eighth of the period)
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