ELE 222E INTRODUCTION TO ELECTRONICS (21604)

Midterm Exam #1  19 March 2003 10.00-12.00

nci LESZ, PhD, Tolga KAYA, MSE
SOLUTIONS w/CORRECTIONS

n = 1350 cm2/Vs

p = 480 cm2/Vs

Ln = 10-2 cm

Lp = 2 10-3 cm

ND = 1015 1/cm3

1. A Si diode in the making will have a junction

are of 1 mm2. n and p type doped areas will
have the properties shown on the left.
ni = 1.5 1010 1/cm3, q = 1.602 10-19 C, VT = 25
mV, r = 12, o = 8.85 10-12 F/m.
a.

What should NA be so that Io 2,5 pA at room

temperature? (15 points)

Using Einstein Eq. , i.e., D p / n = VT p / n , we find Dp = 12 cm2/s and Dn = 33.8 cm2/s. If

Dn
Ln

Dp
Dn
= 1016 1/cm3.
+
I o = A q ni2
2,5 pA, then for N A
Dp
L p N D Ln N A
2
I o Aqni
Lp N D
b.

What should the widths of n and p type doped areas (dn and dp) be for bulk resistances to be Rn =
1 and Rp = 0,25 , respectively? (15 points)
HINT: Rn / p =

n/ p

dn/ p
A

n/ p

dn/ p
A

ni2

;
We know p = q
N

+
n
A
p
N

ALSO: You may neglect the width of the depletion layer.

ni2

n = q NDn +
p Thus p = 0,769 1/( cm) and
ND

n = 0,216 1/( cm). Inserting these into the hint equation and reorganizing it we obtain
d n / p = n / p Rn / p A . Thus dn = 0,226 cm = 2,26 mm and dp = 19,2 m. OBSERVE THE
DIFFERENCE IN LENGTHS OF n AND p TYPE DOPED REGIONS!!!!
c.

Calculate the total depletion layer thickness and capacitance without any bias voltage applied to
this junction. (10 points)

NA ND
n2
i

From V B = VT ln

= 613 mV and wdep =

2 o r VB
q

1
1

+
NA ND

= 94.5 m.

SEE THAT NEGLECTING THE WIDTH OF THE DEPLETION LAYER IN p TYPED REGION IN
PART (a) HAS NOT BEEN A GOOD IDEA!!!!
Inserting the values into C = o r

A
we obtain C = 112 pF.
w

Device

IC
(mA)

IB
(mA)

IE
(mA)

2,0

2,0

1,0

0,01

1,4
1,01

0,99

100

2. Measurements taken on a variety of

transistors are incomplete and
possibly in error. The submitted data
are given on the left. Provide missing
data and correct for inconsistent
and/or wrong data. (20 points)
First remember a few definitions:

0,5

0,0025

1,2
0,51

0,98

200

0,8

0,08
0

0,8

IE = ( + 1) IB
IC = IB
= IC / IE

Now look at the four devices:

1. Assume given data are correct. If = then IC = IE and thus = 1 and IB = 0.
2. Assuming IC = 1 mA and = 100 are correct.
3. Assuming IC = 1 mA, = 0,98 and = 200 are correct.
4. Assuming IC = 0,8 mA, and = 1 are correct.
+10V
3. For the circuits shown on the right,
find the collector currents of both
transistors (|VBE| = 0.6 V), and the
labelled node voltages (V1, V2, V3, V4
and V5) for
a.

5k1

V2

V1

hFE = = (20 points)

Automatically, V1 = 0V and
thus V2 = 0.6 V.
IE1 = (VCC-V2)/9k1 = 1,03 mA.
THUS IC1 = 1,03 mA.
V3 = -VEE + IC1*9k1 = -0,6 V.
Therefore V4 = -1,2 V.
IE2 = (V4-VEE)/4k3 = 2,05 mA.
THUS IC2 = 2,05 mA.
V5 = VCC - IC2*5k1 = -0,45 V.
This last value makes sure that
T2 is still in the active region
because CB junction is reverse
biased.

b.

9k1

T1

V5

100k
T2

V3

V4
9k1

4k3
-10V

hFE = = 100 (20 points)

Direction 1: From ground over 100k to Vcc.

I C1 = hFE

VCC (V BE1 )
= 0,93 mA. V1 = IB1*100k = 0,93 V and V2 = 1,53 V.
100k + hFE 9k1

Loop 2: From VEE over C1 to B2 to E2 to VEE.

I C 2 = hFE

9k1 * I C1 VBE 2
= 1,77 mA. V3 = -VEE + 9k1 (IC1 IB2) = -1,70 V.
9k1 + (1 + hFE )4k 3

Therefore V4 = -2,30 V. V5 = VCC 5k1*IC2 = 0,95 V.