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Logic Families
Post-Laboratory Exercise
Group No: T5
Name: S.W.H.M.S.P.Herath
S.W.H.M.S.P.Herath
S.S.Ruwan Pathirana
1.
1.1. By
say
this
A(input1
)
0v
0v
5v
5v
B(input2
)
0v
5v
0v
5v
Table 1
Z(Output)
1.0v
1,0v
1.0v
3.6v
Diode Logic
looking at the observations in table01 what can you
about the two diodes used for
part of the experiment?
We cant get exactly 0V for logic 0 and 5V for logic 1 because two diodes perform deviation from their ideal
characteristics. We can solve this specifying threshold voltage values for logic 0 and 1
1.2. By looking at the observations in table 02 how many different logic low voltages that
you can observe? (you can consider the threshold value as 2.5V) Hence predict effect
on output voltage when the cascade level increases.
Diodes we used are not ideal. And three different low voltages are observed they are 1.0V, 1.5V and
1.6V. So there were slight variations of all the low voltages, when the output voltage is in high, the output voltage
will rise to 3.5V. It maybe goes into the forbidden zone, which is unspecified voltage zone. When we increase
cascade manner that will be limited for few number of circuits.
1.3. Comment on the limitations/drawbacks of the diode logic family in terms of fan-out.
The fan-out of the diode logic family is lower compared to the other families. The output of the gate
tends to reach the undefined voltage range when we adding a new diode. So the maximum number of
gates that can be connected together is lower. Therefore it may have a small fan-out value. Also it may
have low noise margin.
2.2 Comment on the effect of resistor values on the gate power dissipation.
According to our observations, when the resistor values increase, the power dissipation will decrease.
2.3 Comment on the effect of resistor values on the gate propagation delay.
When we increase the resistor values propagation delay is increased.
Logic 1
Vih(Min)
Vol(max)
Logic 2
VIl(Max)
3.2 By using the observations in table 03 in your lab sheet calculate the power dissipation of
the RTL gate you constructed.
Output voltage = 4.3V
Current drawn = 0.002 A
Power dissipation of the RTL gate = 4.30.002 = 8.6 mW
4.2 Using the observations in the section 4.3 in the lab sheet calculate the per gate
propagation delay of the TTL logic IC you used. Compare this value with the value
mentioned in the datasheet of the IC
Time of the wave form = 10-6/21.5=46.5 ns
Propagation delay per gate = 9.3 ns
References
[1] Electronic Devices & Circuits (Applied Electronic Vol I) by G.M. Mithal.
[2] Digital Electronics (3rd Edition) by Morris Mano