Xilinx XC4000

FPGA Devices

ECE 449 Computer Design Lab

George Mason University

World of ASICs
ASIC
(Application Specific Integrated Circuit)

Full-Custom

Semi-Custom

(ordered by users)

(designed by users)

PLD

PAL

PLA

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User
Programmable

FPGA

MAX

TLU
(Table Look-Up)

MUX

Gates
2

Which Way to Go?

Custom ASICs
High performance

FPGAs
Off-the-shelf
Low development cost

Low power
Short time to market
Low cost in
high volumes

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Reconfigurability

Other FPGA Advantages

Manufacturing cycle for ASIC is very costly,
lengthy and engages lots of manpower
Mistakes not detected at design time have
large impact on development time and cost
FPGAs are perfect for rapid prototyping of
digital circuits

Easy upgrades like in case of software

Unique applications
reconfigurable computing
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What is the FPGA?

FPGA Field Programmable Gate Array
Originally a large array of gates with programmable
interconnections

Now much more complex arrays of various components

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Major FPGA Vendors

Xilinx, Inc.
Share over 60% of the market
Altera Corp.
Lattice Semiconductor
Actel Corp.
Agere Systems
Cypress Semiconductor
Atmel
Quick Logic Corp.

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Xilinx FPGA Families

Mature Products
XC3000, XC4000, XC5200
Old 0.5m, 0.35m and 0.25m technology. Not
recommended for modern designs.

Modern Virtex FPGAs

Virtex (0.22m)
Virtex-E, Virtex-EM (0.18m)
Virtex-II, Virtex-II PRO (0.13m)

Low Cost Family

Spartan/XL derived from XC4000
Spartan-II derived from Virtex
Spartan-IIE derived from Virtex-E
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XC4000 Family (1)

Densities from 3k to 180k
gates
System performance
beyond 80MHz
0.35m process
PCI compliant (faster
grades)
SRAM-based in-system
configuration
IEEE 1149.1-compatible
boundary scan

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Flexible architecture
Abundant flip-flops
Flexible functions
generators
Dedicated high-speed carry
logic
Wide edge decoders
Internal 3-state bus
capability
Low-skew clock networks
Distributed Select-RAM
memory

XC4000 Family (2)

Device

CLB
Array

Logic cells
LUT

Maximum
Available
I/O

Number of
Flip-flops

Distributed
RAM bits

XC4002XL

8x8

128

64

256

2,048

XC4003E

10x10

200

80

360

3,200

XC4005E/XL

14x14

392

112

616

6,272

XC4006E

16x16

512

128

768

8,192

XC4008E

18x18

648

144

936

10,368

XC4010E/XL

20x20

800

160

1,120

12,800

XC4013E/XL

24x24

1,152

192

1,536

18,432

XC4020E/XL

28x28

1,568

224

2,016

25,088

XC4025E

32x32

2,048

256

2,560

32,768

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XC4000 Family (3)

Device

CLB
Array

Logic cells
LUT

Maximum
Available
I/O

Number of
Flip-flops

Distributed
RAM bits

XC4028EX/XL

32x32

2,048

256

2,560

32,768

XC4036EX/XL

36x36

2,592

288

3,168

41,472

XC4044XL

40x40

3,200

320

3,840

51,200

XC4052XL

44x44

3,872

352

4,576

61,952

XC4062XL

48x48

4,608

384

5,376

73,728

XC4085XL

56x56

6,272

448

7,168

100,356

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XC4000 Architecture (1)

I/ O
Block
Configurable
Logic
Block

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XC4000 Architecture (2)

CLBs provide the functional elements for
constructing logic
IOBs provide interface between the
package pins and the CLBs

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Configurable Logic Block

carry
up

carry
down

C1..C4

control
G4

A4

G3

A3

G2

A2

G1

A1

LUT
ROM
RAM

DIN
F
G
H

D
CE
CK

A3
A2

LUT

SR
FF
Q
LATCH

YQ

A1

control
F4

A4

F3

A3

F2

A2

F1

A1

LUT
ROM
RAM

DIN
F
G
H

D
CE
CK

H
F

SR
FF
Q
LATCH

XQ

CLK

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LUT Functionality
x1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

x2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

x3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

x4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

x1
x2
x3
x4

y
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0

LUT

x1 x2 x3 x4

x1 x2

x1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

x2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

x3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

x4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

y
0
1
0
0
0
1
0
1
0
1
0
0
1
1
0
0

Look-Up tables are

primary elements for
logic implementation
Each LUT can
implement any
function of 4 inputs
Capacity limited by
number of inputs,
not complexity
Can be configured
as LUT, ROM or
RAM

y
y

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Input/Output Block
T

O
D
CLK

FF
LATCH

CE

CK

PAD

I
Q
CLK

CE
CK

FF
LATCH
D

delay

CE

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IOB Functionality
IOB provides interface between the
package pins and CLBs
Each IOB can work as uni- or bi-directional
I/O
Outputs can be forced into High Impedance
Inputs and outputs can be registered
advised for high-performance I/O

Inputs can be delayed to achieve 0 ns hold

time
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Routing Resources
CLB

CLB

PSM
CLB

CLB

PSM
CLB

PSM
CLB

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CLB

Programmable
Switch
Matrix

PSM
CLB

CLB

17

Questions?

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