Lecture 1

ECE2072/TRC2300/TEC2172 Digital Systems:
Combinational Logic Technologies
based on textbook
Contemporary Logic Design, 2nd Edition
by R. H. Katz and G. Borriello
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IV - Combinational Logic
Technologies
Copyright 2004, Gaetano Borriello and Randy H. Katz
ECE2072/TRC2300: Combinational Logic

Technologies Summary (Katz2e Ch4)
Standard gates
Regular logic
gate packages
cell libraries
multiplexers
decoders
Two-level programmable logic
PALs
PLAs
ROMs
Technologies
Fixed/Random logic (Sec4.2.1 Katz2e)
Transistors quickly integrated into logic gates (1960s)

Catalog of common gates (1970s)
Texas Instruments Logic Data Book the yellow bible

all common packages listed and characterized (delays, power)
typical packages:
in 14-pin IC: 6-inverters, 4 NAND gates, 4 XOR gates
Today, very few parts are still in use

However, parts libraries exist for chip design
designers reuse already characterized logic gates on chips

same reasons as before
difference is that the parts dont exist in physical inventory
created as needed
Technologies
Fixed/Random logic
Too hard to figure out exactly what gates to use
map from logic to NAND/NOR networks

determine minimum number of packages
slight changes to logic function could decrease cost
Changes difficult to realize
need to rewire parts

may need new parts
design with spares (few extra inverters and gates on every board)
Technologies
Regular logic (eg. Multiplexers/decoders,

ROMs, PLAs/PALs etc)
Need to make design faster

Need to make engineering changes easier to make
Simpler for designers to understand and map to functionality
harder to think in terms of specific gates

better to think in terms of a large multi-purpose block
Technologies
Making connections (Sec4.2.2 Katz Ed2)
Direct point-to-point connections between gates
wires we've seen so far
Route one of many inputs to a single output --- multiplexer

Route a single input to one of many outputs --- demultiplexer
control
multiplexer
Technologies
control
demultiplexer
4x4 switch
Mux and demux
Switch implementation of
multiplexers and demultiplexers
can be composed to make

arbitrary size switching
networks
used to implement multiplesource/multiple-destination
interconnections
Technologies
Mux and demux (cont'd)
Uses of multiplexers/demultiplexers in multi-point connections

A0
Sa
A1
B0
B1
MUX
MUX
Sb
multiple input sources
Sum
Ss
DEMUX
S0
Technologies
multiple output destinations
S1
Multiplexers/selectors
Multiplexers/selectors: general concept
2n data inputs, n control inputs (called "selects"), 1 output

used to connect 2n points to a single point
control signal pattern forms binary index of input connected to
output
I
I
A
Z
A
0
1
Z = A' I0 + A I1
Z
I0
I1
functional form
logical form
two alternative forms
for a 2:1 Mux truth table
Technologies
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
0
0
1
1
1
Multiplexers/selectors (cont'd)
2:1 mux:
4:1 mux:
8:1 mux:
Z = A'I0 + AI1
Z = A'B'I0 + A'BI1 + AB'I2 + ABI3
Z = A'B'C'I0 + A'B'CI1 + A'BC'I2 + A'BCI3 +
AB'C'I4 + AB'CI5 + ABC'I6 + ABCI7
In general: Z =
I0
I1
2 n -1
k=0
(mkIk)
in minterm shorthand form for a 2n:1 Mux
2:1
mux
A
Technologies
I0
I1
I2
I3
4:1
mux
A B
I0
I1
I2
I3
I4
I5
I6
I7
8:1
mux
A B C
10
Gate level implementation of muxes
2:1 mux
4:1 mux
Technologies
11
Cascading multiplexers
Large multiplexers can be made by cascading smaller ones

I0
I1
I2
I3
I4
I5
I6
I7
8:1
mux
4:1
mux
2:1
mux
4:1
mux
B C
control signals B and C simultaneously choose

one of I0, I1, I2, I3 and one of I4, I5, I6, I7
control signal A chooses which of the
upper or lower mux's output to gate to Z
Technologies
alternative
implementation
I0
I1
2:1
mux
I2
I3
2:1
mux
I4
I5
2:1
mux
I6
I7
2:1
mux
C
8:1
mux
4:1
mux
A B
12
Multiplexers as general-purpose logic
A 2n:1 multiplexer can implement any function of n variables
with the variables used as control inputs and

the data inputs tied to 0 or 1
in essence, a lookup table
Example:
F(A,B,C) = m0 + m2 + m6 + m7
= A'B'C' + A'BC' + ABC' + ABC
= A'B'C'(1) + A'B'C(0)
+ A'BC'(1) + A'BC(0)
+ AB'C'(0) + AB'C(0)
+ ABC'(1) + ABC(1)
1
0
1
0
0
0
1
1
0
1
2
3
4 8:1 MUX
5
6
7
S2 S1 S0
Z
F
Z = A'B'C'I0 + A'B'CI1 + A'BC'I2 + A'BCI3 +

AB'C'I4 + AB'CI5 + ABC'I6 + ABCI7
Technologies
13
Multiplexers as general-purpose logic (Ex4.1)
A 2n-1:1 multiplexer can implement any function of n variables
with n-1 variables used as control inputs and

the data inputs tied to the last variable or its complement
Example:
1
0
1
0
0
0
1
1
F(A,B,C) = m0 + m2 + m6 + m7
= A'B'C' + A'BC' + ABC' + ABC
= A'B'(C') + A'B(C') + AB'(0) + AB(1)
0
1
2
3
4 8:1 MUX
5
6
7
S2 S1 S0
A
Technologies
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
F
1
0
1
0
0
0
1
1
C'
C'
0
1
C'
C'
0
1
0
1
4:1 MUX
2
3
S1 S0
A
C
14
Multiplexers as general-purpose logic (contd)

(Ex4.2 Katz Ed2)
Generalization
n-1 mux control
variables
I0
I1
. . . In-1 In
In
In'
single mux data

variable
Example:
G(A,B,C,D)
can be realized
by an 8:1 MUX
choose A,B,C as
control variables
Technologies
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
G
1
1
0
1
0
0
1
1
1
0
0
1
1
0
1
0
four possible
configurations
of truth table
rows can be
expressed as
a function of In
1
D
0
1
D'
D
1
D
0
1
D
D
D
D
0
1
2
3
4 8:1 MUX
5
6
7
S2 S1 S0
D
D
C
15
Activity
Realize F = BCD + ABC with a 4:1 multiplexer and a

minimum of other gates:
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Technologies
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Z
0
0
1
0
0
0
0
0
0
0
1
0
1
1
0
0
0 when BC
D when BC
A when BC
0
D
A
0
0
1
4:1 MUX
2
3
S1 S0
B
0 when BC
Z = BC(0) + BC(D) + BC(A) + BC(0)
16
Demultiplexers/decoders (Sec4.2.3 Katz Ed2)
Decoders/demultiplexers: general concept
single data input, n control inputs, 2n outputs

control inputs (called selects (S)) represent binary index of
output to which the input is connected
data input usually called enable (G)
1:2 Decoder:
O0 = G S
O1 = G S
2:4 Decoder:
O0 = G S1
O1 = G S1
O2 = G S1
O3 = G S1
Technologies
S0
S0
S0
S0
3:8 Decoder:
O0 = G S2 S1 S0
O1 = G S2 S1 S0
O2 = G S2 S1 S0
O3 = G S2 S1 S0
O4 = G S2 S1 S0
O5 = G S2 S1 S0
O6 = G S2 S1 S0
O7 = G S2 S1 S0
17
Gate level implementation of demultiplexers
1:2 decoders
active-high
enable
G
active-low
enable
\G
O0
O0
O1
O1
2:4 decoders
G
O0
active-high
enable
O1
S1 S0
Technologies
\G
O0
active-low
enable
O1
O2
O2
O3
O3
S1 S0
18
Demultiplexers as general-purpose logic
A n:2n decoder can implement any function of n variables
with the variables used as control inputs

the enable inputs tied to 1 and
the appropriate minterms summed to form the function
0
1
2
3
3:8 DEC 4
5
6
7
S2 S1 S0
A
Technologies
A'B'C'
A'B'C
A'BC'
A'BC
AB'C'
AB'C
ABC'
ABC
demultiplexer generates appropriate

minterm based on control signals
(it "decodes" control signals)
19
Demultiplexers as general-purpose logic (contd)

(Ex4.6 Katz Ed2)
F1 = A'BC'D + A'B'CD + ABCD

F2 = ABC'D' + ABC
F3 = (A' + B' + C' + D')
Enable
Technologies
4:16
DEC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A'B'C'D'
A'B'C'D
A'B'CD'
A'B'CD
A'BC'D'
A'BC'D
A'BCD'
A'BCD
AB'C'D'
AB'C'D
AB'CD'
AB'CD
ABC'D'
ABC'D
ABCD'
ABCD
F1
F2
F3
A B C D
20
Cascading decoders
5:32 decoder
1x2:4 decoder
4x3:8 decoders
0
2:4 DEC 1
2
S1 S0 3
A
0
1
2
3:8 DEC3
4
5
6
7
S2 S1 S0
0
1
2
3:8 DEC3
4
5
6
7
S2 S1 S0
C
Technologies
A'B'C'D'E'
ABCDE
0
1
2
3:8 DEC 3
4
5
6
7
S2 S1 S0
0
1
2
3:8 DEC 3
4
5
6
7
S2 S1 S0
C
A'BC'DE'
AB'C'D'E'
AB'CDE
21
Programmable logic arrays (Sec4.2.3 Katz Ed2)
Pre-fabricated building block of many AND/OR gates
actually NOR or NAND

"personalized" by making/breaking connections among the gates
programmable array block diagram for sum of products form

inputs
AND
array
product
terms
OR
array
outputs

Technologies
22
Enabling concept (Ex4.7 Katz Ed2)
Shared product terms among outputs

example:
F0
F1
F2
F3
=
=
=
=
A +
A C'
B' C'
B' C
B' C'
+ AB
+ AB
+ A
input side:
personality matrix
product
term
AB
B'C
AC'
B'C'
A
inputs
A
B
1
1
0
1
0
1
Technologies
1
0
0
outputs
F0 F1
0
1
0
0
0
1
1
0
1
0
1 = uncomplemented in term
0 = complemented in term
= does not participate
F2
1
0
0
1
0
F3
0
1
0
0
1
output side:
1 = term connected to output
0 = no connection to output
reuse of terms
23
Before programming
All possible connections are available before "programming"
in reality, all AND and OR gates are NANDs
Technologies
24
After programming
Unwanted connections are "blown"
fuse (normally connected, break unwanted ones)

anti-fuse (normally disconnected, make wanted connections)
A
AB
B'C
AC'
B'C'
A
Technologies
F0
F1
F2
F3
25
Alternate representation for high fan-in structures
Short-hand notation so we don't have to draw all the wires
signifies a connection is present and perpendicular signal is an

input to gate
notation for implementing
F0 = A B + A' B'
F1 = C D' + C' D
A B C D
AB
A'B'
CD'
C'D
Technologies
AB+A'B'
CD'+C'D
26
Programmable logic array example (Ex4.8 Katz

Ed2)
Multiple functions of A, B, C
F1 = A B C
F2 = A + B + C
F3 = A' B' C'
F4 = A' + B' + C'
F5 = A xor B xor C
F6 = A xnor B xnor C
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
F1
0
0
0
0
0
0
0
1
F2
0
1
1
1
1
1
1
1
Technologies
F3
1
0
0
0
0
0
0
0
F4
1
1
1
1
1
1
1
0
F5
0
1
1
0
1
0
0
1
F6
0
1
1
0
1
0
0
1
full decoder as for memory address

bits stored in memory
A B C
A'B'C'
A'B'C
A'BC'
A'BC
AB'C'
AB'C
ABC'
ABC
F1 F2 F3 F4 F5
F6
27
PALs and PLAs
Programmable logic array (PLA)
what we've seen so far

unconstrained fully-general AND and OR arrays
Programmable array logic (PAL)
constrained topology of the OR array

innovation by Monolithic Memories
faster and smaller OR plane
a given column of the OR array

has access to only a subset of
the possible product terms
Technologies
28
PALs and PLAs: design example

BCD to Gray code converter
A
0
0
0
0
0
0
0
0
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
1
C
0
0
1
1
0
0
1
1
0
0
1
Technologies
D
0
1
0
1
0
1
0
1
0
1
W
0
0
0
0
0
1
1
1
1
1
X
0
0
0
0
1
1
0
0
0
0
Y
0
0
1
1
1
1
1
1
0
0
Z
0
1
1
0
0
0
0
1
1
0
minimized functions:
W = A + BD + BC
X = BC'
Y=B+C
Z = A'B'C'D + BCD + AD' + B'CD'
29
PALs and PLAs: design example (contd)
Code converter: programmed PLA
A B
W = A + BD + BC
X = B C'
Y=B+C
Z = A'B'C'D + BCD + AD' + B'CD'
C D
A
BD
BC
BC'
B
C
not a particularly good

candidate for PAL/PLA
implementation since no terms
are shared among outputs
A'B'C'D
BCD
AD'
BCD'
Technologies
however, much more compact

and regular implementation
when compared with discrete
AND and OR gates
30

A B
C D
Code converter: programmed PAL
A
BD
BC
0
BC'
0
0
4 product terms
per each OR gate
0
B
C
0
0
A'B'C'D
BCD
AD'
B'CD'
Technologies
W X
Y Z
31
Code converter: NAND gate implementation
loss or regularity, harder to understand

harder to make changes
A
B
C
A
B
D
B
C
D
B
C
B
Technologies
A
\D
B
C
\B
C
\D
32
PALs and PLAs: another design example

(Ex4.10 Katz Ed2)
A B
C D
Magnitude comparator
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EQ
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
NE
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
LT
0
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
EQ = ABCD + ABCD + ABCD + ABCD
LT =
AC + ABD + BCD
Technologies
A'B'C'D'
GT
0
0
0
0
1
0
0
0
1
1
0
0
1
1
1
0
A'BC'D
ABCD
AB'CD'
AC'
A'C
B'D
BD'
A'B'D
B'CD
ABC
BC'D'
NE = AC + AC + BD + BD
GT = AC + ABC + BCD
EQ NE LT GT
33
Activity
Map the following functions to the PLA below:
W = AB + AC + BC
X = ABC + AB + AB
Y = ABC + BC + BC
A B C
W
Technologies
Y
34
Activity (contd)
9 terms wont fit in a 7 term PLA
ABC
observe that AB = ABC + ABC

can rewrite W to reuse terms:
W = ABC + ABC + AC
ABC
AC
Now it fits
A B C
8 terms wont fit in a 7 term PLA
can apply concensus theorem

to W to simplify to:
W = AB + AC
AB
W = ABC + ABC + AC
X = ABC + AB + AB
Y = ABC + BC + BC
AB
BC
BC
This is called technology mapping
manipulating logic functions

so that they can use available
resources
W
Technologies
Y
35
Read-only memories (Sec4.2.2 Katz Ed2)
word lines (only one

is active decoder is
just right for this)
Two dimensional array of 1s and 0s
entry (row) is called a "word"

width of row = word-size
index is called an "address"
address is input
selected word is output
n
2 -1
decoder
word[i] = 0011
word[j] = 1010
internal organization
0
n-1
Address
Technologies
bit lines (normally pulled to 1 through

resistor selectively connected to 0
by word line controlled switches)
36
ROMs and combinational logic
Combinational logic implementation (two-level canonical form)

using a ROM
F0 = A' B' C + A B' C' + A B' C
F1 = A' B' C + A' B C' + A B C
F2 = A' B' C' + A' B' C + A B' C'
F3 = A' B C + A B' C' + A B C'
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
F0
0
1
0
0
1
1
0
0
F1
0
1
1
0
0
0
0
1
F2
1
1
0
0
1
0
0
0
truth table
Technologies
F3
0
0
0
1
1
0
1
0
ROM
8 words x 4 bits/word
A B C
F0F1F2F3
address outputs
block diagram
37
ROM structure
Similar to a PLA structure but with a fully decoded AND array
completely flexible OR array (unlike PAL)

n address lines

inputs
decoder
2n word
lines
memory
array
(2n words
by m bits)
outputs

m data lines
Technologies
38
ROM vs. PLA
ROM approach advantageous when
ROM problems
size doubles for each additional input

can't exploit don't cares
PLA approach advantageous when
design time is short (no need to minimize output functions)

most input combinations are needed (e.g., code converters)
little sharing of product terms among output functions
design tools are available for multi-output minimization

there are relatively few unique minterm combinations
many minterms are shared among the output functions
PAL problems
constrained fan-ins on OR plane
Technologies
39
Regular logic structures for two-level logic
ROM full AND plane, general OR plane
PAL programmable AND plane, fixed OR plane
cheap (high-volume component)

can implement any function of n inputs
medium speed
intermediate cost
can implement functions limited by number of terms
high speed (only one programmable plane that is much smaller than
ROM's decoder)
PLA programmable AND and OR planes
most expensive (most complex in design, need more sophisticated tools)

can implement any function up to a product term limit
slow (two programmable planes)
Technologies
40
Multi-level logic:
Field-Programmable Gate Array (FPGA)
Combines density advantage of gate array with rapid

programmability of PAL/PLA
Basic components:
Logic Cell - can be programmed to implement any function of up

to five inputs (Xilinx)
Wiring channels - programmable connections between cells
IO Cells - interface to external signals at edge of array
Usually programmed using CAD (eg. Verilog) synthesizer for

optimal layout on target platform
Modern FPGA may contain over 10,000 logic cells, equivalent
to several million simple logic gates
Due to high flexibility, FPGAs are now one of the most popular
logic technologies
Technologies
41
Actel FPGA Architecture
Once-programmable using anti-fuse technology

Logic cell can implement all 1, 2-input functions, 223 3-input
functions and many other 4 to 8 input functions
horizontal
wiring tracks
IO buffers,
programming
and test logic
S0A
D0
D1
2:1
MUX
2:1
MUX
D2
row of
logic cells
S0 S1
D3
2:1
MUX
S0B
Logic Cell structure
Technologies
42
Xilinx FPGA Architecture
Must be reprogrammed on each power-up

Each CFB implements a 5-input function, or two 4-input functions
IO Buffers
S
4-input
LUT
logic
cell
Y
D Q
MUX
wiring channels
Combinational Function
Block (CFB) structure
(simplified)
Technologies
43
Xilinx FPGA
Technologies
44
Tri-State Outputs (Sec4.4.1 Katz Ed2)

The Third State
Logic States: "0", "1"
Don't Care/Don't Know State: "X" (must be some value in real circuit!)
Third State: "Z" high impedance infinite resistance, no connection
Tri-state gates: output values are "0", "1", and "Z"
additional input: output enable (OE)
A OE F
X 0 Z
0 1 0
1 1 1
When OE is high, this gate is a non-inverting "buffer"

When OE is low, it is as though the gate was
disconnected from the output!
This allows more than one gate to be connected to the
same output wire, as long as only one has its
output enabled at the same time
100
Non-inverting buffer's
timing waveform
A
OE
F
Technologies
"Z"
"Z"
45
Tri-state Outputs
Using tri-state gates to implement an economical multiplexer:
F
Input 0
OE
When SelectInput is asserted high

Input1 is connected to F
Input 1
OE
When SelectInput is driven low

Input0 is connected to F
This is essentially a 2:1 Mux
SelectInput
Technologies
46
Tri-state Outputs
Alternative Tri-state Fragment
F
Input 0
Active low tri-state enables

plus inverting tri-state buffers
OE
Input 1
OE
SelectInput
I
OE
Switch Level Implementation

of tri-state gate
Technologies
0
47
Tri-State Outputs
4:1 Multiplexer, Revisited
\EN
S1
S0
1G 1Y3
1Y2
3 139 1Y1
2 1B
1A 1Y0
15
7
6
5
4
D3
2G 2Y3 10
2Y2
13 2B
2Y1 11
14 2A 2Y0 12
D2
D1
D0
Decoder + 4 tri-state Gates
Technologies
48
Open Collector Outputs (Sec4.4.2 Katz Ed2)

Open Collector
another way to connect multiple gates to the same output wire
gate only has the ability to pull its output low; it cannot actively
drive the wire high
this is done by pulling the wire up to a logic 1 voltage through a
resistor
+5 V
Pull-up resistor
Open-collector
NAND gate
F
0V
A
A
B
C
D
OC NAND gates
Wired AND:
If A and B are "1", output is actively pulled low
if C and D are "1", output is actively pulled low
if one gate is low, the other high, then low wins
if both gates are "1", the output floats, pulled
high by resistor
Hence, the two NAND functions are AND'd
together! (by O/C outputs and wire)
Technologies
49
Open Collector Outputs

4:1 Multiplexer
\EN 1
Y3
139 Y2
3
Y1
B
S1
2
A
Y0
S0
G
+5V
7
6
5
4
\I3
OR
\I2
OR
\I1
OR
\I0
OR
Decoder + 4 Open Collector Gates
Technologies
50
Combinational logic technology summary
Random logic
Time response in combinational networks
gate delays and timing waveforms

hazards/glitches (what they are and why they happen)
Regular logic
Single gates or in groups

conversion to NAND-NAND and NOR-NOR networks
transition from simple gates to more complex gate building blocks
reduced gate count, fan-ins, potentially faster
more levels, harder to design
multiplexers/decoders
ROMs
PLAs/PALs
FPGAs
Non-gate logic
Tri-state outputs
Open-collector outputs
Technologies
51

Lecture 1

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ECE2072/TRC2300/TEC2172 Digital Systems:

Combinational Logic Technologies

Copyright 2004, Gaetano Borriello and Randy H. Katz

ECE2072/TRC2300: Combinational Logic

Two-level programmable logic

Copyright 2004, Gaetano Borriello and Randy H. Katz

Fixed/Random logic (Sec4.2.1 Katz2e)

Transistors quickly integrated into logic gates (1960s)

Texas Instruments Logic Data Book the yellow bible

in 14-pin IC: 6-inverters, 4 NAND gates, 4 XOR gates

Today, very few parts are still in use

designers reuse already characterized logic gates on chips

Copyright 2004, Gaetano Borriello and Randy H. Katz

Too hard to figure out exactly what gates to use

map from logic to NAND/NOR networks

slight changes to logic function could decrease cost

Changes difficult to realize

need to rewire parts

Copyright 2004, Gaetano Borriello and Randy H. Katz

Regular logic (eg. Multiplexers/decoders,

Need to make design faster

harder to think in terms of specific gates

Copyright 2004, Gaetano Borriello and Randy H. Katz

Making connections (Sec4.2.2 Katz Ed2)

Direct point-to-point connections between gates

wires we've seen so far

Route one of many inputs to a single output --- multiplexer

Copyright 2004, Gaetano Borriello and Randy H. Katz

Mux and demux

can be composed to make

Copyright 2004, Gaetano Borriello and Randy H. Katz

Mux and demux (cont'd)

Uses of multiplexers/demultiplexers in multi-point connections

multiple input sources

multiple output destinations

Multiplexers/selectors: general concept

2n data inputs, n control inputs (called "selects"), 1 output

Copyright 2004, Gaetano Borriello and Randy H. Katz

in minterm shorthand form for a 2n:1 Mux

Gate level implementation of muxes

Copyright 2004, Gaetano Borriello and Randy H. Katz

Large multiplexers can be made by cascading smaller ones

control signals B and C simultaneously choose

Copyright 2004, Gaetano Borriello and Randy H. Katz

Multiplexers as general-purpose logic

A 2n:1 multiplexer can implement any function of n variables

with the variables used as control inputs and

Z = A'B'C'I0 + A'B'CI1 + A'BC'I2 + A'BCI3 +

Copyright 2004, Gaetano Borriello and Randy H. Katz

Multiplexers as general-purpose logic (Ex4.1)

A 2n-1:1 multiplexer can implement any function of n variables

with n-1 variables used as control inputs and

Multiplexers as general-purpose logic (contd)

single mux data

Copyright 2004, Gaetano Borriello and Randy H. Katz

Realize F = BCD + ABC with a 4:1 multiplexer and a

Z = BC(0) + BC(D) + BC(A) + BC(0)

Copyright 2004, Gaetano Borriello and Randy H. Katz

Demultiplexers/decoders (Sec4.2.3 Katz Ed2)

Decoders/demultiplexers: general concept

single data input, n control inputs, 2n outputs

Copyright 2004, Gaetano Borriello and Randy H. Katz

Gate level implementation of demultiplexers

Demultiplexers as general-purpose logic