EC3021

COMPUTER ORGANISATION AND

ARCHITECTURE

LATEST TECHNOLOGIES IN MULTIPLIER

DESIGN

TECHNOLOGIES FOR MULTIPLICATION

Wallace tree
In Wallace tree architecture, all the bits of all of the partial products in
each column are added together by a set of counters in parallel
without propagating any carries. Another set of counters then reduces
this new matrix and so on, until a two row matrix is generated. The
most common counter used is the 3:2 counter which is a Full Adder.
The final results are added using usually carry propagate adder. The
advantage of Wallace tree is speed because the addition of partial
products is now O (logN). A block diagram of 4 bit Wallace Tree
multiplier is shown in below. As seen from the block diagram partial
products are added in Wallace tree block. The result of these additions
is the final product bits and sum and carry bits which are
added in the final fast adder (CRA).

Array multiplier
Array multiplier is well known due to its regular structure. Multiplier
circuit is based on add and shift algorithm. Each partial product is
generated by the multiplication of the multiplicand with one multiplier
bit. The partial product are shifted according to their bit orders and
then added. The addition can be performed with normal carry
propagate adder. N-1 adders are required where N is the multiplier
length.

Carry-Less Multiplication
Carry-less Multiplication (CLMUL) is an extension to the x86
instruction set used by microprocessors from Intel and AMD which
was proposed by Intel in March 2008 and made available in the Intel
Westmere processors announced in early 2010. The purpose is to
improve the speed of applications doing block cipher encryption in
Galois/Counter Mode, which depends on finite field multiplication.
Finite field (GF(2k)) multiplication can be implemented more efficiently
with the new CLMUL instructions than with the traditional instruction
set. Another application is the fast calculation of CRC values.
The instruction computes the 128-bit product of two 64-bit values. The
destination is a 128-bit XMM register. The source may be another
XMM register or memory. An immediate operand specifies which
halves of the 128-bit operands are multiplied. Mnemonics specifying
specific values of the immediate operand are also defined:
Instruction
PCLMULQDQ

Opcode
[rmi: 66 0f

Description
Perform a carry-less

xmmreg,xmmrm,imm

multiplication of two 64-bit

3a 44 /r ib] polynomials over the finite field
GF(2).

PCLMULLQLQDQ
xmmreg,xmmrm

[rm: 66 0f Multiply the low halves of the

3a 44 /r 00] two registers.

PCLMULHQLQDQ
xmmreg,xmmrm

Multiply the high half of the

[rm: 66 0f
destination register by the low
3a 44 /r 01]
half of the source register.

PCLMULLQHQDQ
xmmreg,xmmrm

Multiply the low half of the

[rm: 66 0f
destination register by the high
3a 44 /r 10]
half of the source register.

PCLMULHQHQDQ
xmmreg,xmmrm

[rm: 66 0f Multiply the high halves of the

3a 44 /r 11] two registers.

Karatsuba Multiplication
Multiplying two n-bit integers with the naive algorithm takes (n2)
time. But it can be done faster with the Karatsuba algorithm it takes
(nlog23)(n1.58) time, which gives a significant speed-up for large
numbers.
The Karatsuba multiplication algorithm for integers x and y is based on
the following observations:

1. Select a modulus mN+. Any number would work, but its most
efficient to choose a power of 2 that is near x. This lets the modulo
and divide be realized as bit masking and right shifting, and ensures
the split is as even as possible.
2. Let xlow=x mod m, and xhigh=x/m. We have x=mxhigh+xlow.
3. Let ylow=y mod m, and yhigh=y/m. We have y=myhigh+ylow.
4. Let a=xhighyhigh.
5. Let b=(xlow+xhigh)(ylow+yhigh).
6. Let c=xlowylow.
7. Then xy=am2+(bac)m+c.
Note that in steps 4 through 6, we perform Karatsuba multiplication
recursively as long as the numbers are above a certain size.

REFERENCES
1.http://users.encs.concordia.ca/~asim/COEN_65
01/Lecture_Notes/L3_Notes.pdf
2.en.wikipedia.org/wiki/CLMUL_instruction_set
3.http://www.nayuki.io/page/karatsubamultiplication