Beruflich Dokumente
Kultur Dokumente
6, NOVEMBER/DECEMBER 2004
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I. INTRODUCTION
The newly developed common-mode voltage reduction techniques [7], [8] have been shown to have no adverse effect on the
linear modulation range [13] and can be applied to both
and vector-controlled inverters with diode front ends. However,
the effect of dead time on the common-mode voltage issue has
not yet been discussed.
This paper investigates the optimal common-mode voltage
reduction pulsewidth modulation (PWM) techniques when
dead-time effect is taken into account. The effect of dead
time on common-mode voltage and the associated solution
are discussed. Based upon the investigations, an optimal
common-mode voltage reduction PWM technique will be
recommended. The common-mode voltage associated with
this technique is not affected by the dead time. Therefore,
the common-mode voltage can be reduced to one-third for
the inverter with diode front end, despite dead-time effect. Experimental results are presented to fully support the
above-mentioned claims.
The effect of dead time on inverter control will be explained
first, followed by the common-mode voltage reduction PWM
techniques. Then, the effects of dead time on the common-mode
voltage will be presented. Finally, an optimal common-mode
voltage reduction PWM technique will be recommended when
dead-time effect is considered
II. EFFECT OF DEAD TIME ON INVERTER CONTROL
In this section the effect of dead time on the inverter control
will be discussed for the development to follow.
Fig. 1 illustrates the block diagram for one of the three inverter legs. As shown in Fig. 1, the rising edges of PWM signals have proper delay which is greater than the turn-off time of
the power devices, such that the turn-off delay of power devices
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TABLE I
SWITCHING PATTERNS FOR COMMON-MODE VOLTAGE REDUCTION
PWM TECHNIQUE, NSVM 1
TABLE II
SWITCHING PATTERNS FOR COMMON-MODE VOLTAGE REDUCTION PWM
= Boolean Not of \S "
TECHNIQUE, NSVM 2; S
TABLE III
SWITCHING PATTERNS FOR COMMON-MODE VOLTAGE REDUCTION PWM
S = Exclusive OR of \S " and \S "
TECHNIQUE, NSVM 3; S
analysis has been shown [14] that the rms amplitude of fundamental voltage error is proportional to dead time and inverter
switching frequency as described in (1)
(1)
where
dc-link voltage;
dead time;
switching frequency.
For an inverter with 5-kHz switching frequency, dead time
s, and 310-V dc-link voltage, the voltage error caused by
kHz
s
V
V.
the dead time is:
Although the value seems trivial, the associated adverse effect
on vector-controlled drive performance becomes relevant in the
low-speed range, especially with high switching frequency and
greater dead-time value [15].
III. COMMON-MODE VOLTAGE REDUCTION TECHNIQUES
Fig. 2. Illustrations of control signals without and with dead-time control, and
the associated output voltages.
will not cause short circuit and damage to the power devices.
Fig. 2 illustrates the control signals without and with dead-time
control, and the associated output voltage. As shown in Fig. 2(a),
during the period of dead time (freewheeling period), the output
voltage is clamped to the negative dc-link rail by the low-side
antiparallel diode for providing a positive line current. Under
this circumstance, the output voltage is smaller than that of the
ideal case. In contrast, when the current is negative, the output
voltage is clamped to the positive dc-link rail by the upper side
antiparallel diode during the freewheeling period.
, defined as the inverter output voltage
The voltage error
minus its ideal counterpart (output without dead time), depends
upon the direction of current, as shown in Fig. 1. A simplified
LAI AND SHYU: OPTIMAL COMMON-MODE VOLTAGE REDUCTION PWM TECHNIQUE FOR INVERTER CONTROLPART I
Fig. 3.
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come out only at the instants when two phases commutate simultaneously. At these commutation instants, the outputs of three
phases are clamped to either the positive or negative dc-link
rail caused by the dead time, thereby increasing the commonmode voltage even when using only nonzero switching states. In
theory, the common-mode voltage reduction PWM techniques,
NSVM1 and NSVM2, work well for no dead-time effect.
It is well known that dead-time control is unavoidable for
inverter control. Can the dead-time effect on the common-mode
voltage be overcome? What would be the cost? Several deadtime compensation techniques have been proposed to deal with
the voltage distortion issue caused by dead-time control [14],
[16]. However, either a voltage or current sensor is required to
detect the direction of current and polarity of output voltage,
respectively.
Based upon the above-mentioned conclusion, there will be
no chance to clamp all three-phase outputs to either positive
or negative dc-link rails if only one of the three phases commutates at any commutation instant and no zero switching
state is invoked for inverter control. Under these two conditions,
the common-mode voltage will be limited within
and
, despite of the current
direction of currents or polarities of output voltages.
LAI AND SHYU: OPTIMAL COMMON-MODE VOLTAGE REDUCTION PWM TECHNIQUE FOR INVERTER CONTROLPART I
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Fig. 10.
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Fig. 11.
Experimental system.
Fig.
12. Experimental
results,
modulation index = 0:575 p.u.
NSVM
PWM
Fig.
13. Experimental
results,
modulation index = 0:8 p.u..
NSVM
PWM
technique,
Fig.
14. Experimental
results,
modulation index = 1:15 p.u..
NSVM
PWM
technique,
technique,
LAI AND SHYU: OPTIMAL COMMON-MODE VOLTAGE REDUCTION PWM TECHNIQUE FOR INVERTER CONTROLPART I
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VI. CONCLUSION
This paper has contributed to the investigation of the
dead-time effect on the common-mode voltage. It has been
shown that the common-mode voltage may not be restricted
to the theoretical value for common-mode voltage reduction
techniques under the effect of dead time. The reasons were
explored by both theoretical analysis and experimental results.
Based upon these results, an optimal common-mode voltage
reduction PWM technique was recommended, which restricts
the common-mode voltage peaks to one-third dc-link voltage,
without any compensation technique, while not causing any
adverse effect on the linear modulation range. Experimental
results were presented to fully support the above-mentioned
claims.
For the effect of common-mode voltage reduction PWM technique on the performance of motor drives, the reader can be
referred to [19]. Moreover, the effect of distribution of zero
voltage vectors on harmonic content has been discussed in [20].
We will report on the effect of common-mode voltage PWM
techniques without using zero voltage vectors on current harmonics and core losses in the future.
REFERENCES
Fig. 15.
X = 2 ms=div, Y = 50 V=div.
voltage caused by dead-time effect occur. Therefore, these experimental results confirm that the presented technique reduces the
common-mode voltage to one-third despite the inverter switching
frequency when dead-time effect is considered.
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Yen-Shin Lai (M96SM01) received the M.S. degree from National Taiwan University of Science and
Technology, Taipei, Taiwan, R.O.C., and the Ph.D.
degree from the University of Bristol, Bristol, U.K.,
both in electronic engineering.
In 1987, he joined National Taipei University of
Technology, Taipei, Taiwan, R.O.C., as a Lecturer.
He is currently a Professor and Chairman of the Department of Electrical Engineering. His research interests include design of control IC for the applications of power electronics, dcdc converter control
and inverter control.
Dr. Lai received the John Hopkinson Premium for the 19951996 session
from the Institution of Electrical Engineers, U.K., and the Third Prize Paper
Award from the Industrial Drives Committee of the IEEE Industry Applications
Society in 2002.