Computer Organization (CSD206): Assignment

ASSIGNMENT 1
Instructions
There are 07 questions in this assignment.
Assignment submitted after due date will not be evaluated.
Upload a pdf version of the document on BlackBoard.
Do not submit the assignment via e-mail.
Write your answer after each question in this document.
Name the document as A1_CO2015_John_Doe.pdf in case your name is John
Doe. [You are required to strictly follow the naming convention.]
Materials copied from the Internet or otherwise will attract penalty as per
course policy.
You are required to draw all the diagrams on your own.
Due Date: 5:00 pm, September 16, 2015
Grading Criteria
Correct answers (in terms of content and expression) will be awarded full points. This
assignment has 35 points (with weightage of 5% in your overall 100 points).

Questions
1. Explain the benefits of using multiple bus architecture compared to single bus
architecture. Discuss single bus configuration and multiple bus configuration.
ANS:Single Bus Configuration:
A system bus typically consists of about 50 to 100 separate lines which are mainly
classified into three functional groups.
1.Data lines which provide a path for moving data among system modules.
2. The address lines which are used to designate the source or destination of the
data on the data bus.
3. The control lines which are used to control the access to and the use of the data
and address lines.
If a great number of devices are connected to the bus, performance will suffer
because of two main reasons:
1.In general , the more devices attached to the bus, the greater the bus length and
hence greater the propagation delay. This delay determines the time it takes for
devices to coordinate the use of the bus. When control of the bus passes from one
device to another frequently, these propagation delays can noticeably affect
performance.

2.The bus may become a bottleneck as the aggregate data transfer demand
approaches the capacity of the bus. However , because the data rates generated by
the attached devices are growing rapidly, this is a race that a single bus is
ultimately destined to lose.
Hence, using multiple bus architecture is more beneficial.

2. Explain the main functions and structural components of a computer.

ANS:
The main functions that a computer can perform are
1. Data processing : Data processing unit of computer processes data which may
take different forms and which may require wide variety of processing ranges.
2. Data storage : This unit stores the data. If not huge amount, this unit stores at
least that amount of data which is being processed at that given moment.
3. Data movement : The computer must be able to move data between itself and
outside world. When data are received from or delivered to a device that is
directly connected to the computer, the process is known as inputoutput
(I/O),and the device is referred to as a peripheral. When data are moved over
longer distances, to or from a remote device, the process is known as data
communications.
4. Control : The control unit controls those three units. Within the computer, a
control unit manages the computers resources and orchestrates the
performance of its functional parts in response to those instructions.
There are four main structural components of a computer.
A. CPU(central processing unit) : It is the main part of the computer which performs
all the operations. It is usually named by processor.
B. Main Memory: This part of computer is used for storing the data.
C. I/O devices: Used for sending and receiving data from computer and other
devices. These are referred to as channel between the computer system and the
external world.
D. System Interconnection: Lines that connect several components to enable them
to perform their specific operations or some mechanism that is used for the
communication between CPU, main memory and I/O devices.
3. Explain the von Neumann architecture.
ANS:
The Von Neumann architecture , also known as the Von Neumann model and
Princeton architecture, is a computer architecture based on that described by
physicist and mathematician John Von Neumann. Computers using Von Neumann
architecture are known as general purpose computers. They consist of four parts,
arithmetic logic unit, the control unit, the memory and the input output devices. Von
Neumann computers can store not only the results of intermediate computation, but
also the instructions and orders that lead to computation.

Partial flow chart for IAS operation:

4. Consider the execution of a program that results in execution of 2 million

instruction on a 400 MHz processor.
Instruction
CPI
Type
Arithmetic and
1
logic
Load/store with
2
cache hit
Branch
4
Memory
12
reference with
cache miss
a) Determine the average CPI.
b) Determine the corresponding MIPS rate.

Instruction Mix
60%
18%
12%
10%

c) Now assume that the program can be executed in eight parallel tasks or threads with
roughly equal number of instructions executed in each task. Execution is on an 8-core
system with each core (processor) having the same performance as the single

Computer Organization (CSD206): Assignment

processor originally used. Coordination and synchronization between the parts adds
an extra 25,000 instruction executions to each task. Calculate the speedup factor.

[ Hint: The speedup factor is the ratio of the execution times

Speedup = Performance after enhancement / Performance before enhancement
= Execution time before enhancement / Execution time after enhancement]
ANS:Time of execution for one single processor is T=Ic/(MIPS*10^6)

=> T=(2*10^6)/(152*10^6)=1/76s=0.013s=13ms

a)
CPI= ( CPIi * Ii )
Ic
60% => Ii = 0.6;18% => Ii = 0.18;12% => Ii = 0.12; 10% =>Ii=0.1;
( CPIi * (Ii/Ic) ) =1*0.6 + 2*0.18 + 4*0.12 +12*0.1=0.6+0.36+0.48+1.2=2.64
b)
MIPS=frequency(Hz)/(CPI*10^6) = 400MHz/CPI = 400/2.64 = 152;
As there is increase in the value of CPI the value of MIPS decreases as they are inversely proportional.
MIPS value has been dropped.
c)
As 2 million instructions are passed to 8 parallel tasks the instructions will be split equally so each task
gets 2000000/8 instructions =250000 and asked to add 25000 more instructions to each task so final
number of instructions for each task are 275000.
Execution time T=Ic/(MIPS*10^6) so execution time for each task is
T'=Ic/(MIPS*10^6) = 275000/(152*10^6) = 0.275*10^6/(152*10^6)=0.275/152 = 0.0018s=1.8 ms.

SpeedUp=
time to execute program on a single processor
time to exectute program on N parallel processors
SpeedUp=T/T'=13/1.8=7.22.

5. A microprocessor has an increment memory direct instruction, which adds 1 to

the value in a memory location. The instruction has five stages: fetch opcode
(four bus clock cycles), fetch operand address (three cycles), fetch operand
(three cycles), add 1to operand (three cycles), and store operand (three cycles).
a) By what amount (in percent) will the duration of the instruction increase if we have
to insert two bus wait states in each memory read and memory write operation?
b) Repeat assuming that the increment operation takes 13 cycles instead of 3 cycles.
c) The microprocessor initiates the fetch operand stage of the increment memory
direct instruction at the same time that a keyboard actives an interrupt request
line. After how long does the processor enter the interrupt processing cycle?
Assume a bus clocking rate of 10 MHz.
ANS:a) If the case has no wait states, the instruction requires around 16 bus clock
cycles in which 4 are used to fetch opcode,3 for fetch operand address,3 for
fetch operand ,3 to add 1 to operand,3 to store operand.
As the instruction needs four memory accesses therefore 8 wait states will be required.
The instruction takes 16+8=24 clock cycles that is increased by 50% in the case where it has wait
states.
b)
If we take 13 cycles to add 1 to operand instead of 3 cycles then in the case where there is no
wait state there instruction need 26 bus cycles, and 26+8=34 bus cycles where we have wait
state that is increased by 8/26=31%.

c)
Clock rate = 10MHz => clock period = 1/10MHz = 10^(-7)s =100ns.
As said the microprocessor of initiates the fetch operand stage of the increment
memory direct instruction at the same time that a keyboard actives an interrupt request line,so
we need 4 bus clock cycles to fetch opcode and 3 to fetch operand address.
so, the processor requires 7 clock cycles to execute the instruction.
so the interrupts begins after 7*100 ns= 700ns.

6. Consider two microprocessors having 8- and 16-bit-wide external data buses, respectively.
The two processors are identical otherwise and their bus cycles take just as long.

a) Suppose all instructions and operands are two bytes long. By what factor do
the maximum data transfer rates differ?
b) Repeat assuming that half of the operands and instructions are one byte long.

ANS:a)
As 8-bit microprocessor transfers 1 byte through single bus cycle with 16-bit micro processer it transfers
2 bytes. Thus the 16-bit microprocessor has twice rate than 8-bit microprocessor.
b)
If we should transfer 50 operands and instructions in which 25 are 1 byte long and other 25 are 2 bytes
long, then 8-bit micro processer needs 25+2*25 bytes=75 bytes whereas 16-bit micro processer needs
25+25=50 bytes which is not twice but is 1.5 times that of 8-bit micro processer.

7. Compare and contrast Intel x86 processor and ARM processor based on:
a) Data Types
b) Types of Operations
c) Addressing Modes
d) Instruction Formats
a)As 8-bit microprocessor transfers 1 byte through single bus cycle with 16-bit micro processer it
transfers 2 bytes. Thus the 16-bit microprocessor has twice rate than 8-bit microprocessor.

a) Based on data types :Intel x86 processor :The x86 can deal with data types of 8 (byte),16 (word),32 (doubleword),64
(quadword), and 128 (double quadword) bits in length. The processor converts
the request for misaligned values into a sequence of requests for the bus
transfer.
Few more data types are general, Integer ordinal etc.