Switching Circuits & Logic Design

Combinational Circuit Design and

Simulation Using Gates
Professor Chien-Mo James Li
Graduate Institute of Electronics Engineering
National Taiwan University
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NTUEE C.M. Li

Objective of this Chapter

Understand real design issues

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Outline

Review of Combinational Circuit Design. *

Design of Circuits with Limited Gate Fan-In. *
Gate Delays and Timing Diagrams.
Hazards in Combinational Logic.
Simulation and Testing of Logic Circuits.

* 8.1 8.2 not in exam

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Circuits with Limited Gate Fan-in

Real Logic gates have limited numbers of gate fan-in

Usually no more than 4

Too many fan-ins of a single gate

Longer gate delay

Circuit design difficult

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Example
P 206

Requires two 4-input AND gates and one 5-input OR gate

Too many fan-in

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Solution
Factor
result

Requires only 3-input gates

Fig. 8-1
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How about Multiple Output Logic?

Factor each output separately
Example

Fig 8-2

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Example (contd)
Fig 8-3

F1 = b(a+c) + ab
F2=(b+c)(b+c)+ab
F3 = a(b+c)+b(a+c)
Underlined terms are common terms

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Food For Thought

Is it true that ANY Combinational Logic can be realized by ONLY

2-input OR , 2-input AND and inverter?

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Outline

Review of Combinational Circuit Design.

Design of Circuits with Limited Gate Fan-In.
Gate Delays and Timing Diagrams.
Hazards in Combinational Logic.
Simulation and Testing of Logic Circuits.

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Gate Delay and Timing Diagrams

Real gate cannot switch instantaneously
Propagation delay
The change in output is delay by with respect to input change
Fig 8-4

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Timing Diagram
Timing diagram shows the change of signals with time
Frequently used techniques for analysis of circuit timing
Unit of time
s = microsecond = 10-6 second
ns = nanosecond = 10-9 second
Fig 8-5

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Another Timing Diagram

Added delay element
1 s
Notice that pulse width of output waveform is
Smaller than the input waveform
How to implement delay?
Use inverters connected in series
Fig 8-6

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Outline

Review of Combinational Circuit Design.

Design of Circuits with Limited Gate Fan-In.
Gate Delays and Timing Diagrams.
Hazards in Combinational Logic.
Simulation and Testing of Logic Circuits.

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Hazards
Definition: Unwanted switching transients in output

Developed by McCluskey etc. in 1950s

Cause of hazards
Different paths from input to output have different propagation
delay
Also known as (AKA) Glitch, spike
4 Types
Static-0 hazard, static-1 hazard
Dynamic-0 hazard, dynamic-1 hazard
Fig 8-7

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Example of static-1 hazard

Fig 8-8
A=C=1
B falls
10 ns gate delay

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How Hazard Occurs

F = AB + BC
When B falls. Both terms can momentarily go to 0
Fig 8-9

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How to Detect Static-1 Hazard

Two level logic

1 write SOP expression

2. plot each term on K map and loop it
3. if any two adjacent ones are not covered by the same loop
static 1-hazard exists
Fig 8-9

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Remedy for Hazard

Add a term to make up for the GAP
Example Fig 8-9

New F = AB+BC+AC

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Static 0-Hazard
A=0 B=1 D=0; INV=3ns OR=AND=5ns

Fig. 8-10
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Remedy
Fig 8-11
Three terms added

F = (A+C)(A+D)(B+C+D)(C+D)(A+B+D)(A+B+C)
Original circuit 4 gates
New circuit 7 gates

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Rules
1. Find a SOP expression Ft for the output in which EVERY PAIR of

adjacent 1s is covered by a 1-term

A two-level AND-OR circuit based on this Ft will be free of static
1-hazards, static 0-hazards and dynamic hazards
2. if a different form of the circuit is desired, manipulate Ft to the
desired form by simple factoring, DeMorgans law etc
Treat each x and x as independent variables

Same thing for POS

ever pair of adjacent zeros is covered by a 0-term

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Food for Thought

Why is hazard prevention so important?
Cost more gates and no functional contribution?

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Outline

Review of Combinational Circuit Design.

Design of Circuits with Limited Gate Fan-In.
Gate Delays and Timing Diagrams.
Hazards in Combinational Logic.
Simulation and Testing of Logic Circuits.

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Verify Logic Circuit

By

Building a circuit, or
Simulation

Building circuit is expensive,

Computer Simulation is easier

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Simulation
Definition

Evaluate output of circuit by its model

Without actually building the circuit

Goals

1. verify logic correctness

2. verify timing
3. find test for the circuit

Elements of simulation

Input signals
Circuit model
Simulator software
Computer

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Verification v.s. Testing

Verification

Before manufacture
Testing
After manufacture

design

manufacture

specifications

=?

=?
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Silicon
Physical device

Design
Code/Netlist/
layout

verification

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testing

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Simulation Process
1. circuit inputs are applied to the first set of gates

Outputs of those gates are calculated

2. outputs of gates which changed in the previous step are fed into
the next level of gate inputs
Then calculate the outputs
3. step 2 is repeated until no more changes in the gate inputs occurs
4. step 1-3 are repeated every time a circuit input changes

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Example

Fig. 8-12 (a)

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Four-valued Logic
0
1
X = unknown

NOTE: Do not confuse unknown with dont care

Z = high impedance (hi-Z)
Signal not connected

TABLE 8-1

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Simulation of four-valued logic

Fig. 8-12 (b)

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Source of Problems
If your simulation fail, it can be caused by

1. Incorrect Design
2. Gates connected wrong
3. Wrong input signals to the circuit

If your simulation succeed but hardware fail,

1. Defective gates
2. Defective interconnect wires

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Debugging Problem
A=B=C=D=1

Good output F = 0
But now F = 1
Where is the problem? Need debugging or diagnosis
Go back from output to input
backtrace
Symptom = output; source of problem = disease

Fig. 8-13
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Debugging Problem
Gate 7 is good

Because input 10 gives output 1

Gate 6 is good because input 001 give 0
Gate 5 is correct because input 111 gives 1
Gate 3 is faulty because input 00 should produce output 0

Fig. 8-13

Notice: this debugging assume that all internal signals are available
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True in simulation but notNTUEE
true C.M.
in real
Li circuit
LogicDesign

Outline

Review of Combinational Circuit Design.

Design of Circuits with Limited Gate Fan-In.
Gate Delays and Timing Diagrams.
Hazards in Combinational Logic.
Simulation and Testing of Logic Circuits.
Design Example

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Design Example
Problem 8 p.236
Seven segment display

Four inputs: ABCD

Seven outputs: X1- X7
Segment i will be display if Xi =1
E.g. x2=x3=1 shows number 1
X1=x2=x7=x5=x4=1 shows number 2

Fig. 8-14
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Design Steps
Draw the truth table

4 input and 7 outputs

Draw K map for each output
Simplify the whole circuit
Use common terms if possible

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Next Time

ch 1 Introduction Number Systems

and Conversion
ch 2 Boolean Algebra
ch 3 Boolean Algebra (contd)
ch 4. Application of Boolean Algebra
ch 5 Karnaugh Maps
ch 7 Multi-Level Gate Circuits;
NAND NOR Gates
ch 8 Combinational Ckt Design

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