Beruflich Dokumente
Kultur Dokumente
Spartan-6
External
memory
Xilinx Training
Memory Options
Distributed
RAM/SRL32
Objectives
Granularity
DRAM
SDRAM
DDR
DDR3
FCRAM
SRAM RLDRAM
SRAM
Sync SRAM
FLASH DDR SRAM
ZBT
QDR
EEPROM FLASH
EEPROM
DRAM
BRAM
Fast Memory
Interfaces
Spartan-6
Capacity
8/27/2015
1.5 V to 2.5 V
Different protocols
Spartan-6
High performance
Slice3
Logic
Slice3
Slice3
Logic RAM
Shift Register
Slice3
Slice3
Logic
Slice3
Logic
Logic
Slice3
Logic
Logic RAM
Shift Register
Slice3
Logic RAM
Shift Register
Logic
Slice3
Logic
Slice3
R
A
M
Logic RAM
Shift Register
R
A
M
Slice3
Logic RAM
Shift Register
Slice3
Logic RAM
Shift Register
R
A
M
Distributed RAM
Slice3
Logic
Logic RAM
Shift Register
Slice3
Slice3
Slice3
Logic
Logic RAM
Shift Register
Slice3
Slice3
Logic
Logic RAM
Shift Register
Slice3
Logic
Slice3
Slice3
R
A
M
Slice3
Logic
Logic RAM
Shift Register
Slice3
Slice3
Logic
R
A
M
Logic RAM
Shift Register
Logic RAM
Shift Register
R
A
M
18Kb Memory
Dual-Port
BRAM
Byte-write enable
Enhances processor memory interfacing
8/27/2015
Addr A
Port A
36
Wdata A
18 Kb
Block
RAM
18 Kb
Memory
Array
9 Kb
Block RAM
Addr B
36
or
36
Rdata A
Wdata B
Port B
36
Rdata B
9 Kb
Block RAM
Port A
36
Wdata A
18 K
True dual-port
16Kx1, 8Kx2,
4Kx4, 2Kx9,
1Kx18, 512x36
Simple dual-port
16Kx1, 8Kx2,
4Kx4, 2Kx9,
1Kx18, 512x36,
256x72
Single-port
16Kx1, 8Kx2,
4Kx4, 2Kx9,
1Kx18, 512x36,
256x72
36
Rdata A
18 Kb
Memory
Array
Each 9 K
Addr A
Addr B
36
Wdata B
Port B
Rdata B
36
Make sure that the address and control signals are stable
during operation
8/27/2015
clk
address
data
memory @a0
ABCD
we[3:0]
1001
AFFD
FFFF
output
AFFD
DDR
DDR2
DDR3
LP DDR
Byte-write operation
during write-first mode
a0
MCB
Blk
Easy to design
Abstracts away complexity of memory interfacing
CORE Generator tool / MIG wizard and EDK
support
Interface
Spartan-6
FPGA
DDR3 SDRAM
800 Mbps*
DDR2 SDRAM
800 Mbps*
DDR SDRAM
400 Mbps*
LP DDR
400 Mbps*
MCB Features
Memory support
XC6SLX4
32
144
XC6SLX9
90
576
32
XC6SLX16
136
576
32
XC6SLX25
229
936
52
XC6SLX45
401
2,088
116
XC6SLX100
930
4,824
268
XC6SLX150
1,355
4,824
268
XC6SLX25T
229
936
52
XC6SLX45T
401
2,088
116
XC6SLX100T
930
4,824
268
XC6SLX150T
1,355
4,824
268
Automatic calibration
DQS centering
DQ per-bit de-skew
FPGA on-chip input termination
0
1
2
3
4
5
Arbiter Controller
32-bit
Bi-directional
32-bit
Bi-directional
32-bit
Uni-directional
Data Path
Dedicated Routing
Spartan-6 Device
PHY
32-bit
Uni-directional
32-bit
Uni-directional
32-bit
Uni-directional
8/27/2015
MCB Options
Block Diagram
Spartan-6 FPGA
User Interface
DDR
DDR2
DDR3
M
C
B
3
M
C
B
3
M
C
LX16 B
1
M
C
B
4
M
C
B
3
p0_cmd_clk
p0_cmd_en
p0_cmd_bl
p0_cmd_instr
p0_cmd_addr
M
C
B
5
LX100/T
M
C
B
1
CMD FIFO 0
CMD FIFO 1
CMD FIFO 2
CMD FIFO 3
CMD FIFO 4
CMD FIFO 5
Off-Chip Memory
Arbiter
Controller
p0_rd_clk
p0_rd_en
M
C
B
1
LX25/T
p0_cmd_full
p0_cmd_empty
M
M
C
C
B LX9 B
3
1
LX4
IP Wrapper
M
C
B
3
M
C
B
1
LX45/T
M
C
B
4
M
C
B
3
Bi -directional
32-bit
Bi -directional
32-bit
Uni -directional
p0_wr_clk
p0_wr_en
p0_wr_data
p0_wr_mask
M
C
B
5
LX150/T
32-bit
p0_rd_data
p0_rd_empty
p0_rd_full
p0_rd_overflow
p0_rd_count
p0_rd_error
P
H
Y
I
O
B
mcbx_dram_clk
mcbx_dram_clk_n
mcbx_dram_cke
mcbx_dram_ras_n
mcbx_dram_cas_n
mcbx_dram_we_n
mcbx_dram_odt
mcbx_dram_ddr3_rst
mcbx_dram_ba
mcbx_dram_addr
mcbx_dram_dq
mcbx_dram_dqs
mcbx_dram_dqs_n
mcbx_dram_udm
mcbx_dram_ldm
Uni -directional
32-bit
p0_wr_empty
p0_wr_full
p0_wr_underrun
p0_wr_count
p0_wr_error
M
C
B
1
Data Path
32-bit
Dedicated Routing
Uni- directional
32-bit
Uni -directional
MCB Performance
Design Considerations
PLL creates two phases of MCB
system clock
DDR
DDR2
DDR3
LPDDR
Data Rate
Min
TBD *
TBD *
TBD *
TBD *
Max
400 Mbps
(200 MHz)
800 Mbps
(400 MHz)
800 Mbps
(400 MHz)
400 Mbps
(200 MHz)
4-bit
8-bit
16-bit
1.6 Gbps
3.2 Gbps
6.4 Gbps
3.2 Gbps
6.4 Gbps
12.8 Gbps
MCB Block
User
Interface
User
Clks
Controller
Arbiter
Data Path
IOB
Memory
Type
PHY Layer
Memory
Interface
1X Clks
2 :2
PLL
3.2 Gbps
6.4 Gbps
12.8 Gbps
CLK
CLK
IN
CLKB
1.6 Gbps
3.2 Gbps
6.4 Gbps
IBUFDS
FB
CLK
SYSCLK_2X
OUT0
2X Clks
CLK
SYSCLK_2X_180
OUT1
BUFPLL_MCB
Clock Example:
DDR2 800 Mbps
2X clk = 800 MHz
1X clk = 400 MHz
IO Clock Network
8/27/2015
Design Considerations
The left and lower left MCB has the best migration path
MCB pins shared less with other functions compared to right side
Design Considerations
8/27/2015
Synthesize design
Place and route design
Timing simulation
Verify in hardware
MIG
Summary
Enables you to customize your
memory controller
Some options are specific to the
memory controller standard
(such as DDR2 and DDR3)
Distributed LUT
RAM
Block RAM
Bigger on-chip memories
High-Performance
Block RAM
FPGA
External Memory
Interfacing
8/27/2015
User Guides
Spartan-6 FPGA User Guide
Describes the complete FPGA architecture, including distributed memory,
block memory and the MCB