100%(1)100% fanden dieses Dokument nützlich (1 Abstimmung)

55 Ansichten43 Seitentổng hợp lý thuyết và bài tập mẫu về diode

Oct 17, 2015

© © All Rights Reserved

PDF, TXT oder online auf Scribd lesen

tổng hợp lý thuyết và bài tập mẫu về diode

© All Rights Reserved

Als PDF, TXT **herunterladen** oder online auf Scribd lesen

100%(1)100% fanden dieses Dokument nützlich (1 Abstimmung)

55 Ansichten43 Seitentổng hợp lý thuyết và bài tập mẫu về diode

© All Rights Reserved

Als PDF, TXT **herunterladen** oder online auf Scribd lesen

Sie sind auf Seite 1von 43

Lectures 1-7

Diode Circuit Applications

University of Technology

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture One - Page 1 of 7

Dr. Ahmed Saadoon Ezzulddin

Basic Construction:

When acceptor impurities are introduced into one side and donors into the other side of

a single crystal of a semiconductor, a p-n junction is formed. In general, the acceptor

ion is indicated by a minus sign because, after this atom "accepts" an electron, it

becomes a negative ion. The donor ion is represented by a plus sign because, after this

impurity atom "donates" an electron, it becomes a positive ion. Now, if a junction is

formed between a sample of p-type and one of an n-type semiconductor, this

combination possesses the properties of a rectifier (permits the flow of charge in one

direction). Such a two-terminal device is called a p-n junction diode.

W The two single crystal semiconductors (having four valence electrons) used

most frequently in the construction of p-n junction diodes are silicon (Si) and

germanium (Ge).

W The p-type is created by introducing those impurity elements (acceptors) that have

three valence electrons (trivalent), such as boron, gallium, and indium.

W The n-type is created by introducing those impurity elements (donors) that have five

valence electrons (pentavalent), such as antimony, arsenic, and phosphorus.

W In a p-type material the hole is the majority carrier and the electron is the minority

carrier.

W In an n-type material the electron is called the majority carrier and the hole the

minority carrier.

W The electrons and holes in the region of the junction will combine, resulting in a

lack of carriers in the region near the junction. This region of uncovered positive

and negative ions is called the "depletion region" due to the depletion of carriers in

this region.

Essential Characteristics:

The essential electrical characteristic of a p-n junction is that it constitutes a rectifier

which permits the easy flow of charge in one direction but restrains the flow in the

opposite direction. We consider now how this diode rectifier action comes above.

No Applied Bias (VD = 0 V):

In the absence of an applied bias voltage, the net flow of charge in any one direction for

a semiconductor diode is zero (see Fig. 1-1).

Fig. 1-1

University of Technology

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture One - Page 2 of 7

Dr. Ahmed Saadoon Ezzulddin

The current that exists under reverse-bias conditions is called the reverse saturation

current and is represented by Is (see Fig. 1-2).

Fig. 1-2

A semiconductor diode is forward-biased when the association p-type and positive and

n-type and negative has been established (see Fig. 1-3).

Fig. 1-3

P

Anode

Cathode

Forward-bias region

Reverse-bias region

Reverse-breakdown region

Fig. 1-4

I D = I S (e kVD / TK 1)

[1.1]

Where k = 11600/ with = 1 for Ge and = 2 for Si for relatively low levels of diode

current and =1 for Ge and Si for higher levels of diode current.

TK = TC + 273o.

University of Technology

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture One - Page 3 of 7

Dr. Ahmed Saadoon Ezzulddin

Resistance Levels:

1. DC or Static Resistance:

The application of a dc voltage to a circuit containing a p-n junction diode will result in

an operating point on the characteristic carve that will not change with time. The

resistance of the diode at the operating point can found simply by finding the

corresponding levels of VD and ID as shown in Fig. 1-5 and applying the following

equation:

RD =

VD

ID

[1.2]

Fig. 1-5

2. Ac or Dynamic Resistance:

If a sinusoidal rather than dc input is applied, the varying input will move the

instantaneous operating point up and down a region of the characteristics and thus

defines a specific change in current and voltage as shown in Fig. 1-6. With no applied

varying signal, the point of operation would be the Q-point determined by the applied

dc levels. A straight line drawn tangent to the curve through the Q-point will define a

particular change in voltage and current that can be used to determine the ac or

dynamic resistance for this region of the diode characteristics. In equation form,

rd =

Vd

I d

[1.3]

Fig. 1-6

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture One - Page 4 of 7

Dr. Ahmed Saadoon Ezzulddin

of the tangent line drawn at that point. Eq. [1.3], as defined by Fig. 1-6, is, therefore,

essentially finding the derivative of the function at the Q-point of operation. If we find

the derivative of the general Eq. [1.1] for the p-n junction diode with respect to the

applied forward bias and then invert the result, we will have an equation for the

dynamic or ac resistance in that region. That is;

d

d

(I D ) =

[ I S (e kVD / TK 1)]

dV

dVD

dI D

k

=

(I D + I S )

dVD TK

dI D

k

ID

( Generally, I D >> I S )

dVD Tk

dI D

K 11600

= 38.93I D

( = 1 & TK = 298o =>

=

38.93 )

TK

dVD

298

dV

0.026

r = v/i = D

dI D

ID

26mV

rd =

[1.4]

ID

All the resistance levels determined thus far have been defined by the p-n

junction and do not include the resistance of the semiconductor material itself

(called body resistance) and the resistance introduce by the connection between the

semiconductor material and the external metallic conductor (called contact resistance).

These additional resistance levels can be included in Eq. [1.4] by adding resistance

denoted by rB appearing in Eq. [1.5].

rd =

26mV

+ rB

ID

[1.5]

3. Average AC Resistance:

If the input signal is sufficiently large to produce a board swing such as indicated in

Fig. 1-7, the resistance associated with the device for this region is called the average

ac resistance. The average ac resistance is, by definition, the resistance determined by a

straight line drawn between the two intersection establish by the maximum and

minimum value of input voltage. In equation form,

rav =

Vd

I d

[1.6]

pt . to pt .

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture One - Page 5 of 7

Dr. Ahmed Saadoon Ezzulddin

Fig. 1-7

1. Piecewise-Linear Model: (see Fig.1-8);

Forward-bias;

+ VD

+ VT rav ( F )

VD > VT

ID

VD +

rav ( R )

Reverse-bias;

VD < VT

ID

ID

Fig. 1-8

rav (F )

rav (R ) 0 VT

VD

Forward-bias & Rnetwork >> rav(F);

+ VT

+ VD

V D > VT

ID

ID

Fig. 1-9

VD +

0 VT

VD < VT

VD

Forward-bias, Enetwork >> VT, Rnetwork >> rav(F) & VD = 0 V;

+ VD

VD > 0

ID

ID

Fig. 1-10

VD +

VD < 0

VD

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture One - Page 6 of 7

Dr. Ahmed Saadoon Ezzulddin

Load-Line Analysis:

From Fig. 1-11:

E VD VR = 0

E = VD + I D R

E

V

ID = D +

[1.7]

R

R

Eq. [1.7] is a linear equation;

y = mx + c ,

where m = 1 / R & c = E / R .

I D = 0 VD = E

[1.8]

E

VD = 0 I D =

R

ID

+

Fig. 1-11

Example 1-1:

Determine the currents I D1 , I D2 , and I R1 for the network of Fig. 1-12.

D1

R1

Si

3.3k

20V

D2

Si

R2

5.6k

Fig. 1-12

Solution:

VD2

0.7

= 0.212mA.

R1 3.3k

Appling KVL yields:

VR2 + E VD1 VD2 = 0

I R1 =

VR

18.6

= 3.32mA.

with I D1 = 2 =

R2 5.6k

Finally, I D2 = I D1 I R1 = 3.32m 0.212m = 3.108mA .

and

+VD

R VR

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture One - Page 7 of 7

Dr. Ahmed Saadoon Ezzulddin

Exercises:

Find the values of ID and Vo in the circuits shown in Fig. 1-13.

10V

Ge

ID

+ 10V

+ 16V

ID

I D1

Si

Si

Vo1

Ge

Si

Si

2k

2k

Si

1.2k

I D2

Vo

Vo2

Vo

3k

3.3k

2k

+ 12V

(a)

(b)

1k

Ge

Vo1

20V I D1

0.47k

Si

I D2

(c)

10Sint

Vo2

rav ( F ) = 0.1k

Si r

av ( R ) = 1M

I d (t )

Vo (t )

Ge

2k

(d)

(e)

Fig. 1-13

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture Two - Page 1 of 3

Dr. Ahmed Saadoon Ezzulddin

Basic Concepts:

Diode switching circuits typically contain two or more diodes, each of which is

connected to an independent voltage source. Understanding the operation of a diode

switching circuit depends on determining which diodes, if any, are forward biased and

which, if any, are reverse biased. The key to this determination is remembering that

a diode is forward biased only if its anode is positive with respect to its cathode

(see Fig. 2-1). One of the very import applications of diode switching circuits is

logic gates.

Fig. 2-1

+ 5V

5V

2V

+ 3V

7V

1k

1k

1k

1k

1k

+ 3V

+ 8V

2V

Logic Gates:

Diodes can be used to form logic gates, which perform some of the logic operations

required in digital computers.

OR Gate:

It has output when there a signal in any input channels (see Fig. 2-2).

D1

VA

D2

VB

Vo

R

VA

VB

D1

D2

Vo

0

0

off

off

0

0

1

off

on

1

1

0

on

off

1

1

1

on

on

1

Fig. 2-2

AND Gate:

It has output only when all inputs are present (see Fig. 2-3).

+V

D1

VA

Vo

D2

VB

VA

VB

D1

D2

Vo

0

0

on

on

0

0

1

on

off

0

1

0

off

on

0

1

1

off

off

1

Fig. 2-3

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture Two - Page 2 of 3

Dr. Ahmed Saadoon Ezzulddin

Example 2-1:

Determine which diodes are forward biased and which are reverse biased in the circuits

shown in Fig. 2-4. Assuming a 0.7-V drop across each forward-biased diode, determine

the output voltage Vo.

+ 5V

R

+ 5V

5V

+ 5V

5V

D1

D2

D3

Vo

+ 5V

0V

10V

D1

D2

+ 15V

10V

Vo

5V

+ 5V

D1

Vo

D2

D3

D4

(a)

(b)

(c)

Fig. 2-4

Solution:

In (a) the net forward-biasing voltage between supply and input for each diode is

D1 & D3:

+5 - (+5) = 0V,

D2 & D4:

+5 - (-5) = 10V.

Therefore, D2 and D4 are forward biased and D1 and D3 are reverse biased.

Vo = -5 + 0.7 = -4.3V.

While in (b) the net forward-biasing voltage between supply and input for each diode is

D1: +15 - (+5) = +10V,

D2: +15 - 0 = +15V,

D3: +15 - (-10) = +25V.

Therefore, D3 is forward biased and D1 and D2 are reverse biased.

Vo = -10 + 0.7 = -9.3V.

Finally, in (c) the net forward-biasing voltage between supply and input for each

diode is

D1: -5 - (-10) = +5V,

D2: +5 - (-10) = +15V.

Therefore, D2 is forward biased and D1 is reverse biased.

Vo = +5 - 0.7 = +4.3V.

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture Two - Page 3 of 3

Dr. Ahmed Saadoon Ezzulddin

Exercises:

Determine Vo and I for each circuit in Fig. 2-5. Assume that each of the diodes in these

circuits has a forward voltage drop of 0.7 V.

+ 2V

4V

+ 5V

1V

D1

+ 10V

15V

D2

2k

2k

D3

4V

D4

+ 6V

Vo

I

2V

2k

D1

D1

8V

Vo

D2

D3

5V

D4

(a)

Vo

D2

+ 3V

D3

D4

(b)

(c)

+ 20V

2k

VA

VB

D1

D2

1k

D1

1k

1k

Vo

I

5.1k

15V

D2

Vo1

D3

Vo2

1k

B

1k

1. V A = VB = 0V ,

2. V A = VB = 5V , and

3. V A = 0V & VB = 5V .

15V

1. No pulses at either A or B,

2. A 30 V positive pulse at A or B, and

3. Positive pulses (30 V) at both A and B.

(d)

(e)

Fig. 2-5

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture Three - Page 1 of 8

Dr. Ahmed Saadoon Ezzulddin

Basic Definition:

There are a variety of diode circuits called clippers (limiters or selectors) that have the

ability to "clip" off a portion of the input signal above (positive) or below (negative)

certain level without distorting the remaining part of the alternating waveform.

Depending on the orientation of the diode, the positive or negative region of the input

signal is "clipped" off.

There are two general categories of clippers: series and parallel. The series

configuration is dined as one where the diode is in series with the load. While the

parallel variety has the diode in a branch parallel to the load (see Fig. 3-1).

vi

vo

V

T

T/2

vi

R vo

T/2

0

V

vi

V

t

T/2

vo

R

+

D vo

vi

T/2

Fig. 3-1

Example 3-1:

Biased Series (Negative) Clipper, see Fig. 3-2.

vi

9

5.2V

Si

vi

0

T/2

-9

Fig. 3-2

vo

R

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

vi

Lecture Three - Page 2 of 8

Dr. Ahmed Saadoon Ezzulddin

E VT Vi

Vi

vo

Ideal

4.5V

13.5

R

4.5

For

and

For

and

t = 0 t1 and t2 T; D ON,

vo = vi + 4.5 V.

t = t1 t2; D OFF,

vo = 0 V.

T/2 t1

0

vo

13.5

13.5

4.5

4.5

- 4.5

- 4.5

vo

-9

t2 T

vi

Example 3-2:

Biased Parallel (Positive) Clipper, see Fig. 3-3.

vi

10

vi

vo

D

T/2

- 10

Fig. 3-3

Si

5.7V

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

R

+

id = 0

Vtransition

Lecture Three - Page 3 of 8

Dr. Ahmed Saadoon Ezzulddin

vo

vi

Si

10

5.7V

Vtransition id R Vd + E = 0;

Vtransition = 0.7 5.7 = 5 V.

For t = 0 t1 and t2 T; D ON,

and vo = 5 V.

For t = t1 t2; D OFF,

and vo = vi.

t1

0

-5

t

Vtransition

-5

- 10

vo

vo

- 10

T/2

t2

10

vi

-5

-5

- 10

- 10

Summary:

A variety of series and parallel clippers with the resulting output for the sinusoidal

input are provided in Fig. 3-4.

Fig. 3-4

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture Three - Page 4 of 8

Dr. Ahmed Saadoon Ezzulddin

Example 3-3:

Double Diode Series Clipper, see Fig. 3-5.

vi

E1

D1

3.3V

Si

E2

D2

7.7V

Ge

12

vi

0

T/2

-12

E1 + VT1 Vi1

vi

vo

4V

E2 + VT2 Vi2

D1

Ideal

D2

vo

R

8V

Ideal

Fig. 3-5

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture Three - Page 5 of 8

Dr. Ahmed Saadoon Ezzulddin

vi

both D1 and D2 will be OFF,

and vo = 0 V.

For t = t1 t2; D1 ON while D2 OFF,

and vo = Vi1 = vi 4 V.

For t = t3 t4; D1 OFF while D2 ON,

and vo = Vi2 = vi + 8 V.

Vi2

20

T/2

8

t1

-4

t2

t3

T

t4

- 16

vo

8

Vi1

vo

- 12

-8

0

12

vi

-4

-4

Example 3-4:

Double Diode Parallel Clipper, see Fig. 3-6.

vi

9

vi

vo

T

0

T/2

D1

Si

D2

E1

2.3V E 2

Si

5.3V

-9

R

+

Vtr1

id1 = 0D

1

E1

vo

Si

Vtr2

2.3V

id 2 = 0D

2

E2

vo

Si

5.3V

Vtr1 id1 R Vd E1 = 0;

Vtr2 + id2 R + Vd + E2 = 0;

Fig. 3-6

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture Three - Page 6 of 8

Dr. Ahmed Saadoon Ezzulddin

vi

both D1 and D2 will be OFF,

and vo = vi.

For t = t1 t2; D1 ON while D2 OFF,

and vo = 3 V.

For t = t3 t4; D1 OFF while D2 ON,

and vo = 6 V.

9

3

t1

t4 T

t

Vtr2

-6

-9

vo

3

3

0 3

vi

-6

-6

Example 3-5:

Special Type Clipper: A Comparator, see Fig. 3-7.

vi

10

vi

0

Vtr1

T/2

vo

-9 -6

t2 t3

T/2

vo

Idial

R

E

- 10

Fig. 3-7

5V

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture Three - Page 7 of 8

Dr. Ahmed Saadoon Ezzulddin

vi

10

For

and

For

and

t = 0 t1 and t2 T; D OFF,

vo = E = 5 V.

t = t1 t2; D ON,

vo = vi.

5

t2 T/2

t1

- 10

vo

vi

10

5

- 10

10

10

vi

Exercises:

1. Design biased parallel clippers (with silicon diodes) to perform the functions

indicated in the transfer characteristics of Fig. 3-8.

vo

vo

12

12

6

- 12

- 12

12

vi

-6

0

-6

(a)

(b)

Fig. 3.8

12

vi

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture Three - Page 8 of 8

Dr. Ahmed Saadoon Ezzulddin

2. Sketch the output voltage (vo) and the transfer characteristics (vo against vi) for each

circuit of Fig. 3-9 for the input (vi) shown.

vi

D

vi

T/2

vo

Ideal

(a)

4V

-8

vi

E1

vi

10

4V

vo

Si

(b)

2.3V

E2

vi

9

vi

T/2

vo

D1

Ge

D2

E1

3.3V E 2

Si

(c)

5.3V

-9

vi

vi

150

D2

D1

Ideal

R1

E1

0

Fig. 3-9

vo

Ideal

100k R2 200k

25V E 2

100V

(d)

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture Four - Page 1 of 4

Dr. Ahmed Saadoon Ezzulddin

Basic Definition:

The clamping circuit (clamper) is one will "clamp" a signal to a different dc level.

The circuit must have a capacitor, a diode, and a resistive element, but it can also

employ an independent dc supply to introduce an additional shift. The magnitude of

R and C must be chosen such that the time constant = RC is large enough to ensure

that the voltage across the capacitor does not discharge significantly during the interval

(T/2) the diode is nonconducting. Throughout the analysis we will assume that for all

practical purposes the capacitor will fully charge or discharge in five time constants.

Therefore, the condition required for the capacitor to hold its voltage during the

discharge period between pulses of the input signal is

5 = 5 RC >>

T

1

=

2 2f

[4.1]

Example 4-1:

Determine the output (vo) for the circuit of Fig. 4-1 for the input (vi) shown.

vi

0

-5

f = 1kHz

10

T/2

vi

3T/2

2T

0.1F

D

vo

Si

R 50k

5V

- 20

Fig. 4-1

Solution:

The analysis of clamping circuits are started by considering that the part of the input

signal that will forward bias the diode. For the circuit of Fig. 4-1, the diode is forward

bias ("on" state) during the negative half period of the input signal (vi) and the capacitor

will charge up instantaneously to a voltage level determined by the circuit of Fig. 4-2.

_ VC

_

20V

+

_

0.7V

+

5V

Fig. 4-2

+

50k vo

_

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture Four - Page 2 of 4

Dr. Ahmed Saadoon Ezzulddin

20 + VC + 0.7 5 = 0 => VC = 24.3 V.

The output voltage (vo) can be determined by KVL in the output section

+ 5 0.7 vo = 0 => vo = 4.3 V.

Now check that the capacitor will hold on or not its establish voltage level during

the period (positive half period in case of Example 4-1) when the diode is in the

"off" state (reverse bias). The total time constant 5 of the discharging circuit of

Fig. 4-3 is determined by the product 5RC and has the magnitude

5 = 5RC = 5 (50103) (0.110-6) = 25 ms.

The frequency ( f ) is 1 kHz, resulting in a period of 1 ms and an interval of 0.5 ms

between levels, that is

T/2 = 1/( 2f ) = 1/(2 1103) = 0.5 ms.

We find that

5 >> T/2 ( 25ms / 0.5ms = 50 times).

So that, it is certainly a good approximation that the capacitor will hold its voltage

(24.3 V) during the discharge period between pulses of the input signal.

_24.3V

+

+

10V

_

5V

50k vo

_

Fig. 4-3

The open-circuit equivalent for the diode will remove the 5-V battery from having any

effect on vo, and applying KVL around the outside loop of circuit will result in

+ 10 + 24.3 vo = 0 => vo = 34.3 V.

The resulting output appears in Fig. 4-4, where the input and the output swing

are the same.

vo

34.3

19.3

4.3

0

T/2

3T/2

Fig. 4-4

2T

5T/2

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture Four - Page 3 of 4

Dr. Ahmed Saadoon Ezzulddin

Example 4-2:

Using silicon diode, design a clamper circuit that will produce output vo = 10Sint5 V

when the input is vi = 10Sint+5 V. Draw the circuit diagram and the input and output

signals.

Solution:

From the input (vi) and output (vo) signals, we have a negative biased clamper.

Therefore, the diode is forward bias ("on" state) during the positive half period of the

input signal (vi). The output voltage (vo) at this positive period can be determined by

KVL in the output section of the circuit shown in Fig. 4-5.

E + 0.7 vo = 0 => E = 5 0.7 = 4.3 V.

VC _

For the input section KVL will result in

+

15 VC 5 = 0 => VC = 10 V.

+

+

0_.7V

vi = 15V

Fig. 4-5

R vo = 5V

_

The circuit diagram and the input and output signals are shown in Fig. 4-6.

vi

15

vi

5

T/2

3T/2

2T

vo

D

Si

4.3V

-5

vo

5

T/2

3T/2

-5

-15

Fig. 4-6

2T

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture Four - Page 4 of 4

Dr. Ahmed Saadoon Ezzulddin

Summary:

A number of clamping circuits and their effect on the square-wave input signal are

shown in Fig. 4-7.

Negative Clampers

Positive Clampers

Fig. 4-7

Exercise:

Sketch the output (vo) for the circuit of Fig. 4-8 for the input (vi) shown. Assume ideal

diodes.

vi

E0

15

+

T

0

T/2

3V

vi

-15

Fig. 4-8

R1

D1

D2

E1

7V E 2

R2 vo

10V

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture Five - Page 1 of 10

Dr. Ahmed Saadoon Ezzulddin

Basic Definition:

A diode circuit that converts an ac voltage to a pulsating dc voltage and permits current

to flow in one direction only is called "rectifier" and the ac-to-dc conversion process is

termed "rectification".

N1

N2

+

vi

V1

V2

VP/n

0

VP

VP

_

_

vi = V1

+ VT

vo

_

V2

i

RL

N

V

n= 2 = 2

N1 V1

VPR

vo

fo = fi = 1/ T

Fig. 5-1

For the half-wave rectifier circuit of Fig. 5-1:

W The average (dc) value of a half-wave rectified sine-wave voltage (Vdc) is

T

V

1

1

Vdc = vo (t ) dt =

VPR Sint dt = PR

2 0

T0

For VP close to VT,

Vdc = 0.318(VP VT )

[5.1a]

For VP >> VT,

Vdc = 0.318VP

[5.1b]

W The root mean square (rms) value of the load voltage (Vrms) is

Vrms =

1 2

vo (t ) dt =

T 0

For VP >> VT,

VPR

1

2

2

V

Sin

t

d

t

=

PR

2 0

2

Vrms = 0.5(VP VT )

[5.2a]

Vrms = 0.5VP

[5.2b]

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture Five - Page 2 of 10

Dr. Ahmed Saadoon Ezzulddin

W The rms value of the ac component (or the ripple voltage) of the rectified signal

[Vr(rms)] is

2

Vr (rms ) = Vrms

Vdc2 = (0.5VPR ) 2 (0.318VPR ) 2 = 0.385VPR

For VP close to VT,

Vr (rms) = 0.385(VP VT )

[5.3a]

For VP >> VT,

Vr (rms ) = 0.385VP

[5.3b]

W The percent ripple (r) in the rectified waveform (also called the ripple factor) is

0.385VPR

V (rms)

100% =

100% = 121%

r= r

0.318VPR

Vdc

W Efficiency () = [ Pdc(load) / Ptotal(circuit) ] 100%

2

I dc

RL

(0.318 I P ) 2 RL

40.5

= 2

%

100% =

100% =

2

1 + rd / RL

(0.5I P ) (rd + RL )

I rms (rd + RL )

For ideal diode (rd = 0 ), = max = 40.5 %

W The peak inverse voltage (PIV) of the diode is

PIV = VP

[5.4]

W The frequency of the output rectified signal (fo) is

fo = fi

[5.5]

1. A Bridge Full-Wave Rectifier:

N1

N2

+ (-)

+ (-)

+

vi

V1

V2

VP

VP/n

0

D4

(i2)

D2

- (+)

D1

i

+

vo

_

D3 R L

- (+)

vi = V1

i1

VP

V2

N

V

n= 2 = 2

N1 V1

Fig. 5-2

VPR

vo

T

fo = 2 fi

i = i1 + i2

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture Five - Page 3 of 10

Dr. Ahmed Saadoon Ezzulddin

W Vdc =

V Sint dt =

PR

0

For VP >> 2VT,

W Vrms =

2VPR

[5.6a]

Vdc = 0.636VP

[5.6b]

2

2

VPR Sin t dt =

0

For VP >> 2VT,

VPR

2

[5.7a]

Vrms = 0.707VP

[5.7b]

2

W Vr (rms ) = Vrms

Vdc2 = (0.707VPR ) 2 (0.636VPR ) 2 = 0.308VPR

For VP close to 2VT,

Vr (rms) = 0.308(VP 2VT )

[5.8a]

For VP >> 2VT,

Vr (rms) = 0.308VP

[5.8b]

W r=

0.308VPR

Vr (rms )

100% =

100% = 48.4%

0.636VPR

Vdc

2

I dc

RL

(0.636 I P ) 2 RL

81

W = 2

100% =

=

100

%

%

1 + 2rd / RL

I rms (2rd + RL )

(0.707 I P ) 2 (2rd + RL )

For ideal diode (rd = 0 ), = max = 81 %

W PIV = VP 2VT

W

fo = 2 fi

[5.9]

[5.10]

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture Five - Page 4 of 10

Dr. Ahmed Saadoon Ezzulddin

N1

+

vi

V2

V1

V2

VP/n

0

+ (-)

VP

i1

VP

(i2)

- (+)

+ (-)

- (+)

N2

vi = V1

D1

N2

VP

V2

+

vo

_

RL

D2

VPR

N

V

n= 2 = 2

N1 V1

vo

T

fo = 2 fi

i = i1 + i2

Fig. 5-3

For the center-tapped full-wave rectifier circuit of Fig. 5-3:

W Vdc =

V Sint dt =

PR

0

For VP >> VT,

W Vrms =

2VPR

Vdc = 0.636(VP VT )

[5.11a]

Vdc = 0.636VP

[5.11b]

2

2

VPR Sin t dt =

0

For VP >> VT,

VPR

2

Vrms = 0.707(VP VT )

[5.12a]

Vrms = 0.707VP

[5.12b]

2

W Vr (rms ) = Vrms

Vdc2 = (0.707VPR ) 2 (0.636VPR ) 2 = 0.308VPR

For VP close to VT,

Vr (rms) = 0.308(VP VT )

[5.13a]

For VP >> VT,

Vr (rms) = 0.308VP

[5.13b]

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

r=

Lecture Five - Page 5 of 10

Dr. Ahmed Saadoon Ezzulddin

Vr (rms )

0.308VPR

100% =

100% = 48.4%

Vdc

0.636VPR

2

I dc

RL

(0.636 I P ) 2 RL

81

=

%

100

%

100

%

2

1 + rd / RL

I rms

(0.707 I P ) 2 (rd + RL )

(rd + RL )

For ideal diode (rd = 0 ), = max = 81 %

W =

W PIV = 2VP VT

W

[5.14]

fo = 2 fi

[5.15]

Summary:

Different parameters for the HWR and FWR circuits are listed in Table 5-1.

Table 5-1

FWR

Parameter

HWR

Bridge

CT

VP 2VT

VP VT

VPR

VP VT

Vdc

0.318VPR

0.636VPR

Vrms

0.5VPR

0.707VPR

Vr

0.385VPR

0.308VPR

121%

48.4%

max

40.5%

81%

PIV

VP

fo

fi

VP 2VT

2VP VT

2fi

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture Five - Page 6 of 10

Dr. Ahmed Saadoon Ezzulddin

Example 5-1:

The input voltage to a full-wave rectifier employing a center-tapped step-down

transformer and two silicon diodes is 220 V rms, and the transformer has turns ratio

n = 0.125. Draw the rectifier circuit diagram when it is connected to a 100 load,

and find

1. the average value of the voltage across the load.

2. the average power dissipated by the load, and

3. the minimum PIV rating required for each diode.

Solution:

1. VP = 2vi n = 2 220 0.125 = 38.9V .

Vdc = 0.636(VP VT ) = 0.636(38.9 0.7 ) = 24.3V .

2

2

Vrms

(

27.0 )

Pav =

=

= 7.3W .

RL

100

n = 0.125

+

+

V_P

vi = 220V

+

V_P

_

D1

Si

D2

Si

Fig. 5-4

RL 100

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture Five - Page 7 of 10

Dr. Ahmed Saadoon Ezzulddin

Capacitor Filters:

A low-pass filter is connected across the output of a rectifier to suppress the ac

components and to pass the dc component. A rudimentary low-pass filter used in power

supplies consists simply of a capacitor (C) connected across the rectifier output, that is,

in parallel with the load (RL), as illustrated in Fig. 5-5.

Vo = VC

vi

RL

VPR

Charging

Discharging

Vr ( pp )

Vo

_

D OFF

T

D ON

D1

Vo = VC

+

vi

_

RL

D2

+

Vo

_

Vr ( pp )

VPR

Fig. 5-5

Operation:

W During the positive first quarter-cycle of the input, the diode is forward-biased

(when Vi > VC), allowing the capacitor to charge quickly to within a diode drop of

the input peak (VPR).

W When the input begins to decrease below its peak, the capacitor retain its charge

and the diode becomes reverse-biased (when VC > Vi).

W During the remaining part of the cycle, capacitor C can discharge slowly only

through load resistance RL at a rate determine by RLC time constant ().

W The voltage fluctuation in the filtered waveforms is called the peak-to-peak ripple

voltage [Vr(pp)]. In general, Vr(pp) in FWR is smaller than it is in HWR for same

RL and C values (see Fig. 5-5).

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture Five - Page 8 of 10

Dr. Ahmed Saadoon Ezzulddin

We will now derive an expression for the ripple in the output of a rectifier having a

capacitor filter (C) and load resistance (RL). The derivation that follows is applicable to

both HWR and FWR. We can assume that the ripple voltage in a lightly loaded filter

(RLC time constant () is large) is a sawtooth wave as illustrated in Fig. 5-6.

Vo = VC

Vr ( pp)

2

VPR

Vdc

Vr ( pp)

T

Fig. 5-6

and that its voltage decays linearly, instead of exponentially. Assuming that the voltage

decays linearly is equivalent to assuming that the discharge current (I) is constant and

equal to I = Vdc / RL where Vdc is the dc value of the filtered waveform. The total

charge in capacitor voltage is Vr(pp) volts, and this charge occurs over the period of

time T. Therefore, since Q = I .t ,

Q (Vdc / RL )T

Vr ( pp ) =

=

C

C

Since T=1/fr, where fr is the frequency of the fundamental component of the ripple,

that is, f r = f o = f i for HWR and f r = f o = 2 f i for FWR. So that

Vr ( pp ) =

or

Vdc

f r RL C

Vdc = Vr ( pp) f r RL C

V ( pp )

Vdc = VPR r

2

Subsuming from Eq. [5.16], we obtain

Vdc

Vdc = VPR

2 f r RL C

[5.16]

[5.17]

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture Five - Page 9 of 10

Dr. Ahmed Saadoon Ezzulddin

Solving for Vdc, we obtain an expression for the dc voltage (Vdc) in terms of the peak

rectifier voltage (VPR):

Vdc =

VPR

1

1+

2 f r RL C

[5.18]

The rms value of a sawtooth waveform having peak-to-peak value Vr(pp) is known to

be

V ( pp)

Vr (rms) = r

[5.19]

2 3

r=

Vr (rms)

V ( pp ) /(2 3 )

100% = r

100%

Vdc

Vr ( pp) f r RL C

r=

1

100%

2 3 f r RL C

[5.20]

Equation [5.20] confirms our analysis of the capacitor filter: a large RLC time

constant () results in a small ripple voltage, and vice versa. The light-load assumption

on which our derivation is based is generally valid for percent ripple (r) less than 6.5%.

From a design standpoint, the values of fr and RL, are usually fixed, and the designer's

task is to select a value of C that keeps the ripple below a prescribed value.

Example 5-2:

A full-wave rectifier is operated from a 50 Hz line and has a filter capacitor connected

across its output. What minimum value of capacitance is required if the load is 1.2 k

and the ripple must be no greater than 2.4%?

Solution:

1

r=

100%

2 3 f r RL C

1

0.024 =

=>

2 3 2 50 1.2 10 3 C

C 100 F .

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture Five - Page 10 of 10

Dr. Ahmed Saadoon Ezzulddin

Exercises:

1. A full-wave bridge rectifier isolated from the 220 V rms power line by a transformer.

Assuming the diode voltage drops are 0.7 V.

i. What turns ratio should the transformer have in order to produce an average

current of 1 A in a 10 load?

ii. What is the average current in each diode under the conditions of (i)?

iii. What minimum PIV rating should each diode have?

iv. How much power is dissipated by each diode?

2. A full-wave bridge rectifier is operated from a 50 Hz, 220 V rms line. It has a 100 F

filter capacitor and a 2 k load. Neglect diode voltage drops.

i. What is the percent ripple?

ii. What is the average current in the load?

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Voltage-Multiplier Circuits

Lecture Six - Page 1 of 3

Dr. Ahmed Saadoon Ezzulddin

Voltage-Multiplier Circuits

Basic Concepts:

Diodes and capacitors can be connected in various configurations to produce filtered,

rectified voltages that are integer multiples of the peak value of an input sine wave. The

principle of operation of these circuits is similar to that of the clamping circuits

discussed previously. By using a transformer to change the amplitude of an ac voltage

before it is applied to a voltage multiplier, a wide range of dc levels can be produced

using this technique. One advantage of a voltage multiplier is that high voltages can be

obtained without using a high-voltage transformer.

Voltage Doubler:

1. Half-Wave Voltage Doubler:

Figure 6-1 shows a half-wave voltage doubler circuit.

+

+

vi

_

+

VP

_

VP _

C1

D2 _

D1 2VP

+

_

C 2 Vo = 2VP

+

Fig. 6-1

Operation:

W During the positive half-cycle,

D1 ON and D2 OFF => Charging C1 up to VP.

W During the negative half-cycle,

D2 ON and D1 OFF => Charging C2 to 2VP.

W The output (Vo) of the half-wave voltage doubler is

Vo = VC2 = 2VP

[6.1]

If a load is connected to the output of the half-wave voltage doubler, the voltage

across capacitor C2 drops during the positive half-cycle (at the input) and the capacitor

is recharged up to 2VP during the negative half-cycle. The output waveform across

capacitor C2 is that of a half-wave signal filtered by a capacitor filter.

The peak inverse voltage (PIV) rating of each diode in the half-wave voltage

doubler circuit must be at least 2VP.

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Voltage-Multiplier Circuits

Lecture Six - Page 2 of 3

Dr. Ahmed Saadoon Ezzulddin

Figure 6-2 shows a full-wave voltage doubler circuit.

D1

+

vi

_

+

VP

_

+

VP _

+

C1

Vo = 2VP

+

VP _

C2

D2

Fig. 6-2

Operation:

W During the positive half-cycle,

D1 ON and D2 OFF => Charging C1 up to VP.

W During the negative half-cycle,

D2 ON and D1 OFF => Charging C2 up to VP.

W The output (Vo) of the full-wave voltage doubler is

[6.2]

If load current is drawn from the full-wave voltage doubler circuit, the voltage

across the capacitors C1 and C2 is the across a capacitor fed by a full-wave rectifier.

One difference is that of C1 and C2 in series, which is less than capacitance of either C1

and C2 alone. The lower capacitor value will provide poorer filtering action than the

single-capacitor filter circuit.

The peak inverse voltage across each diode is 2VP, as it is for filter capacitor

circuit.

Figure 6-3 shows an extension of the half-wave voltage doubler, which develops

three and four times the peak input voltage. It should be obvious from the pattern

of the circuit connection how additional diodes and capacitors may be connected

so that the output voltage may also be five, six, seven, and so on, times the basic peak

voltage (VP).

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Voltage-Multiplier Circuits

Lecture Six - Page 3 of 3

Dr. Ahmed Saadoon Ezzulddin

Tripler (3VP )

+

+

vi

_

+

VP

_

2VP_

+

VP _

C1

D1

C2

D2

C3

_

+

2VP

Doubler (2VP )

D3

C4

D4

_

+

2VP

Quadrupler ( 4VP )

Fig. 6-3

Operation:

W During the positive half-cycle,

D1 ON and D2, D3, D4 OFF => Charging C1 up to VP.

W During the negative half-cycle,

D2 ON and D1, D3, D4 OFF => Charging C2 to 2VP.

W During the next positive half-cycle,

D1, D3 ON and D2, D4 OFF => C2 charges C3 to 2VP.

W During the next negative half-cycle,

D2, D4 ON and D1, D3 OFF => C3 charges C4 to 2VP.

W The voltage across the combination of C1 and C3 is 3VP and that across C2 and

C4 is 4VP.

The PIV rating of each diode in the circuit must be at least 2VP.

Exercises:

1. A certain voltage doubler has 35 V rms on its input. What is the output voltage?

Sketch the circuit, indicating the output terminals and PIV for the diode.

3. The output voltage of a quadrupler is 620 V. What minimum PIV rating must each

diode have?

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture Seven - Page 1 of 7

Dr. Ahmed Saadoon Ezzulddin

Zener Diodes:

Diodes which are designed with plate power-dissipation capabilities to operate in the

breakdown region may be employed as voltage-reference or constant-voltage devices.

Such are known as avalanche, breakdown, or zener diodes. The zener diode is made

for operation in the breakdown region. By varying the doping level, a manufacturer can

produce zener diodes with breakdown voltages from about 2 to 250 V.

When the applied reverse voltage reaches the breakdown value, minority carries

in the depletion layer are accelerated and reach high enough velocities to dislodge

valence electrons from outer orbits. The newly liberated electrons can then gain high

enough velocities to free other valence electrons. In this way, we get an avalanche of

free electrons. Avalanche occurs for reverse voltages greater than 6 V or so.

The zener effect is different. When a diode is heavily doped, the depletion layer

is very narrow. Because of this, the electric field across the depletion layer is very

intense. When the field strength reaches approximately 3107 V/m, the field is intense

enough to pull electrons out of valence orbits. The creation of free electrons in this way

is called zener breakdown (also known as high-field emission).

The zener effect is predominant for breakdown voltages less than 4 V, the

avalanche effect is predominant for breakdown voltages greater than 6 V, and both

effects are present between 4 and 6 V. Originally, people thought the zener effect was

the only breakdown mechanism in diodes. For this reason, the name "zener diode"

came into widespread use before the avalanche effect was discovered. All diodes

optimized for operation in the breakdown region are therefore still called zener diodes.

I D (mA)

Cathode

VZ

Anode

VD (V )

rZ

I ZK

IZ

I ZM

Fig. 7-1

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture Seven - Page 2 of 7

Dr. Ahmed Saadoon Ezzulddin

Fig. 7-1 shows the schematic symbol and the current-voltage curve of a zener

diode. Negligible reverse current flows until we reach the breakdown voltage VZ.

In a zener diode, the breakdown has a very sharp knee, followed by an almost vertical

increase in current. Note that the voltage is approximately constant, equal to VZ over

most of the breakdown region. Data sheets usually specify the value of VZ at a

particular knee current IZK which is beyond the knee (see Fig. 7-1).

The power dissipation of a zener diode equals the product of its voltage and

current. In symbols,

PZ = VZ I Z

As long as PZ is less than the power rating PZ(max), the zener diode will not be destroyed.

Commercially available zener diodes have power ratings from 0.25 W to more than

50 W. Data sheets often specify the maximum current a zener diode can handle without

exceeding its power rating. This maximum current is designated IZM (see Fig. 7-1).

The relation between IZM and power rating is given by

I ZM =

PZ (max)

[7.1]

VZ

voltage produces a large increase in current. This implies that a zener diode has a small

dynamic resistance (rZ, see Fig. 7-1). We can calculate this zener resistance by

rZ =

v

i

The complete equivalent circuit of the zener diode in the zener region includes

a small dynamic resistance (rZ) and dc battery equal to the zener potential (VZ),

as shown in Fig. 7-2a. For all applications to follow, however, we shall assume as a

first approximation that the external resistors are much larger in magnitude than the

zener-equivalent resistor and that the equivalent circuit is simply the dc battery that

equal to VZ as indicated in Fig. 7-2b.

+

IZ

VZ

VZ

rZ

VZ

(a)

(b)

Fig. 7-2

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture Seven - Page 3 of 7

Dr. Ahmed Saadoon Ezzulddin

1. AC Voltage Regulators (Limiters or Clippers):

Two back-to-back zeners can be used as an ac regulator or a simple square-wave

generator as shown in Examples 7-1 and 7-2 respectively.

Example 7-1:

Sinusoidal ac regulator, see Fig. 7-3.

vi

VZ 2 + VT1

+12

+7.5

t1

0

-4

-12

t 2 t3

t4

vi

_

VZ1 + VT2

5k

D1[VZ1 = 3.3V , Si]

vo

+7.5

vo

D2 [VZ 2 = 6.8V , Si ]

0

-4

Fig. 7-3

For t = 0 t1 and t2 ; D1 ON and D2 OFF => vo = vi .

For t = t1 t2; D1 ON and D2 BREAKDOWN => vo = VZ 2 + VT1 .

For t = t3 t4; D2 ON and D1 BREAKDOWN => vo = VZ1 + VT2 .

Example 7-2:

Simple square-wave generator, see Fig. 7-4.

vi

+40

vi

_

5k

D1[VZ1 = 10V ]

D2 [VZ 2 = 10V ]

- 40

Fig. 7-4

vo

VZ 2

+10

vo

_

0

-10

VZ1

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture Seven - Page 4 of 7

Dr. Ahmed Saadoon Ezzulddin

2. DC Voltage Reference:

Two or more reference levels can be established by placing zener diodes in series as

shown in Fig. 7-5. As long as Vi is grater than the sum of VZ1 and VZ 2 , both diodes will

be in the breakdown state and the three reference voltages will be available.

+

E _

5k

50V

D1[VZ1 = 10V ]

+

10V

_

D2 [VZ 2 = 20V ]

+

20V

_

+

30V

_

Fig. 7-5

3. DC Voltage Regulators:

a. Fixed RL, Variable Vi:

For the regulator circuit shown in Fig. 7-6;

IL =

VZ

(Constant)

RL

I S (min) = I ZK + I L

Vi (min) = I S (min) RS + VZ

[7.2a]

RS

[7.2b]

Vi

IS

+

IZ

VZ

Fig. 7-6

I S (max) = I ZM + I L

Vi (max) = I S (max) RS + VZ

[7.2c]

IL

RL

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture Seven - Page 5 of 7

Dr. Ahmed Saadoon Ezzulddin

For the regulator circuit shown in Fig. 7-7;

IS =

Vi VZ

(Constant)

RS

[7.3a]

RS

I L (min) = I S I ZM

RL (max) =

VZ

[7.3b]

IZ

VZ

Vi

IL

RL

I L (min)

Fig. 7-7

I L (max) = I S I ZK

RL (min) =

IS

VZ

[7.3c]

I L (max)

For the regulator circuit shown in Fig. 7-8;

I ZK = I S (min) I L (max)

I S (min) =

I L (max) =

Vi (min) VZ

RS

[7.4a]

RS

VZ

RL (min)

Vi

IS

+

IZ

VZ

I ZM = I S (max) I L (min)

I S (max) =

I L (min) =

Vi (max) VZ

RS

VZ

RL (max)

[7.4b]

Fig. 7-8

IL

RL

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture Seven - Page 6 of 7

Dr. Ahmed Saadoon Ezzulddin

Example 7-3:

The reverse current in a certain 12 V, 2.4 W zener diode must be at least 5 mA to

ensure that the diode remains in breakdown. The diode is to be used in the regulator

circuit shown in Fig. 7-9, where Vi can vary from 18 V to 24 V. Find a suitable

value for RS and the minimum rated power dissipation that RS should have.

RS

S

+

Vi

VZ

RL 600

Fig. 7-9

Solution:

I ZK = 5mA and I ZM =

PZ 2.4

=

= 200mA .

VZ 12

I L (max) =

VZ

RL (min)

12

= 20mA (when the switch S is closed, RL = RL (min) = 600 ).

600

I ZK = I S (min) I L (max)

=>

5 10 3 = I S (min) 20 10 3

=>

I S (min) = 25mA .

I ZM = I S (max) I L (min)

=>

200 10 3 = I S (max) 0

=>

I S (max) = 200mA .

RS (max) =

Vi (min) VZ

I S (min)

Vi (max) VZ

18 12

= 240 .

25 10 3

24 12

= 60 .

I S (max)

200 10 3

Thus, we require 60 RS 240 .

RS (min) =

I S (max) =

Vi (max) VZ

RS

24 12

= 100mA .

120

Electrical and Electronic Engineering Department

Second Year, Electronics I, 2009 - 2010

Lecture Seven - Page 7 of 7

Dr. Ahmed Saadoon Ezzulddin

Exercises:

1. Sketch the output (vo) for the circuit of Fig. 7-10 for the input shown (vi) when

|Vm| equal to (i) 5 V, and (ii) 15 V.

vi

+Vm

5k

vi

D[VZ = 10V , Si ]

vo

-Vm

Fig. 7-10

2. Design the voltage regulator circuit of Fig. 7-11 to maintain VL at 12 V across RL

with Vi that will vary between 16 and 20 V. That is, determine the proper value of RS

and the power rating of the zener diode (PZ).

RS

+

VL RL 240

Vi

Fig. 7-11

3. The 6-V zener diode in Fig. 7-12 has a maximum rated power dissipated of

690 mW. Its reverse current must be at least 3 mA to keep it in breakdown. Find

a suitable value for RS if Vi can vary from 9 V to 12 V and RL can vary from

500 to 1.2 k.

RS

Vi

IS

+

6V

IZ

IL

RL

Fig. 7-12

maximum permissible value of Vi?

5. If RS in Exercise 3 is set equal to its minimum permissible value, what is the

minimum permissible value of RL?

6. If RS in Exercise 3 is set equal to 120 , what is the minimum rated power

dissipated that RS should have?

## Viel mehr als nur Dokumente.

Entdecken, was Scribd alles zu bieten hat, inklusive Bücher und Hörbücher von großen Verlagen.

Jederzeit kündbar.