3.

7 TUGAS
3.7.1 TABEL KEBENARAN
INPUT
X1
0
0
0
0
1
1
1
1

X2
0
0
1
1
0
0
1
1

A
0
1
X
X
X
X
X
X

B
X
X
0
1
X
X
X
X

3.7.2 RANGKAIAN GERBANG LOGIKA

3.7.3TIMING DIAGRAM

C
X
X
X
X
0
1
X
X

D
X
X
X
X
X
X
0
1

OUTPUT
Y
0
1
0
1
0
1
0
1

3.7.4 LISTING PROGRAM

entity FATONI is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
X1 : in STD_LOGIC;
X2 : in STD_LOGIC;
y : out STD_LOGIC);
end FATONI;

architecture Behavioral of FATONI is

begin

Y <= (( NOT X1) AND ( NOT X2) AND A ) OR (( NOT X1) AND X2 AND B ) OR ( X1
AND ( NOT X2 ) AND C ) OR ( X1 AND X2 AND D );
end Behavioral;

3.7.5 DESAIN SUMMARY

FATONI Project Status

Project File:

MULTIPLEXERKU.xis
Parser Errors:
e

No Errors

Module
Name:

FATONI

Implementation State:

Programming File
Generated

Target Device: xc3s500e-4cp132

Errors:

No Errors

Product
Version:

Warnings:

No Warnings

ISE 14.4

Design Goal:

Balanced

Design
Strategy:

Xilinx Default
(unlocked)

Timing
Constraints:

Environment: System Settings

All Signals
Completely
Routed

Routing Results:

0 (Timing
Final Timing Score: Report)

Device Utilization Summary

Use
d

Logic Utilization

[-]

Available

Utilizatio
Note(s)
n

Number of 4 input LUTs

9,312

1%

Number of occupied Slices

4,656

1%

Number of Slices containing only related

logic

100%

Number of Slices containing unrelated

logic

0%

Total Number of 4 input LUTs

9,312

1%

Number of bonded IOBs

92

7%

Average Fanout of Non-Clock Nets

1.14

Performance Summary

[-]

Final Timing Score:

0 (Setup: 0, Hold: 0)

Pinout Data: Pinout Report

Routing Results:

All Signals Completely Routed

Clock Data:

Timing Constraints:

Clock Report

Detailed Reports

[-]

Report Name

Status Generated

Error Warning
Infos
s
s

Synthesis Report

Curren Mon Dec 8

t
18:24:43 2014

Translation Report

Curren Mon Dec 8

t
18:24:53 2014

Map Report

Curren Mon Dec 8

t
18:24:58 2014

2 Infos (0 new)

Place and Route Report

Curren Mon Dec 8

t
18:25:08 2014

1 Info (0 new)

Post-PAR Static Timing Curren Mon Dec 8

Report
t
18:25:11 2014

6 Infos (0 new)

Curren Mon Dec 8

t
18:25:47 2014

Power Report

Bitgen Report

Secondary Reports
Report Name

Status

Generated

ISIM Simulator Log

Current

Mon Dec 8 18:26:41 2014

WebTalk Report

Current

Mon Dec 8 18:25:48 2014

WebTalk Log File

Current

Mon Dec 8 18:25:59 2014

3.7.6 SINTESYS REPORT

Release 14.4 - xst P.49d (nt64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp

[-]

Total REAL time to Xst completion: 0.00 secs

Total CPU time to Xst completion: 0.13 secs

--> Parameter xsthdpdir set to xst

Total REAL time to Xst completion: 0.00 secs

Total CPU time to Xst completion: 0.13 secs

--> Reading design: FATONI.prj

TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT

================================================
=========================
*

Synthesis Options Summary

================================================
=========================
---- Source Parameters
Input File Name

: "FATONI.prj"

Input Format

: mixed

Ignore Synthesis Constraint File : NO

---- Target Parameters

Output File Name

: "FATONI"

Output Format

: NGC

Target Device

: xc3s500e-4-cp132

---- Source Options

Top Module Name

: FATONI

Automatic FSM Extraction

: YES

FSM Encoding Algorithm

: Auto

Safe Implementation
FSM Style

: No
: LUT

RAM Extraction
RAM Style

: Yes
: Auto

ROM Extraction
Mux Style

: Yes
: Auto

Decoder Extraction
Priority Encoder Extraction

: YES
: Yes

Shift Register Extraction

: YES

Logical Shifter Extraction

: YES

XOR Collapsing
ROM Style

: YES
: Auto

Mux Extraction

: Yes

Resource Sharing

: YES

Asynchronous To Synchronous
Multiplier Style

: NO

: Auto

Automatic Register Balancing

: No

---- Target Options

Add IO Buffers

: YES

Global Maximum Fanout

: 100000

Add Generic Clock Buffer(BUFG)

Register Duplication
Slice Packing

: 24

: YES
: YES

Optimize Instantiated Primitives : NO

Use Clock Enable

: Yes

Use Synchronous Set

: Yes

Use Synchronous Reset

: Yes

Pack IO Registers into IOBs

: Auto

Equivalent register Removal

: YES

---- General Options

Optimization Goal

: Speed

Optimization Effort

:1

Keep Hierarchy

: No

Netlist Hierarchy

: As_Optimized

RTL Output

: Yes

Global Optimization
Read Cores

: AllClockNets
: YES

Write Timing Constraints

: NO

Cross Clock Analysis

: NO

Hierarchy Separator

:/

Bus Delimiter

: <>

Case Specifier

: Maintain

Slice Utilization Ratio

BRAM Utilization Ratio
Verilog 2001

: 100
: 100
: YES

Auto BRAM Packing

: NO

Slice Utilization Ratio Delta

:5

================================================
=========================

================================================
=========================
*

HDL Compilation

================================================
=========================
Compiling vhdl file "D:/vhdl/multiplexerku/FATONI.vhd" in Library work.
Architecture behavioral of Entity fatoni is up to date.

================================================
=========================
*

Design Hierarchy Analysis

================================================
=========================
Analyzing hierarchy for entity <FATONI> in library <work> (architecture
<behavioral>).

================================================
=========================
*

HDL Analysis

================================================
=========================
Analyzing Entity <FATONI> in library <work> (Architecture <behavioral>).
Entity <FATONI> analyzed. Unit <FATONI> generated.

================================================
=========================
*

HDL Synthesis

================================================
=========================

Performing bidirectional port resolution...

Synthesizing Unit <FATONI>.

Related source file is "D:/vhdl/multiplexerku/FATONI.vhd".
Unit <FATONI> synthesized.

================================================
=========================
HDL Synthesis Report

Found no macro
================================================
=========================

================================================
=========================
*

Advanced HDL Synthesis

================================================
=========================

================================================
=========================
Advanced HDL Synthesis Report

Found no macro
================================================
=========================

================================================
=========================
*

Low Level Synthesis

================================================
=========================

Optimizing unit <FATONI> ...

Mapping all equations...

Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block FATONI, actual ratio is 0.

Final Macro Processing ...

================================================
=========================
Final Register Report

Found no macro
================================================
=========================

================================================
=========================
*

Partition Report

================================================
=========================

Partition Implementation Status

-------------------------------

No Partitions were found in this design.

-------------------------------

================================================
=========================
*

Final Report

================================================
=========================
Final Results
RTL Top Level Output File Name

: FATONI.ngr

Top Level Output File Name

Output Format

: FATONI
: NGC

Optimization Goal

: Speed

Keep Hierarchy

: No

Design Statistics
# IOs

:7

Cell Usage :
# BELS

:3

LUT3

:2

MUXF5

:1

# IO Buffers

:7

IBUF

OBUF

:6
:1

================================================
=========================

Device utilization summary:

---------------------------

Selected Device : 3s500ecp132-4

Number of Slices:

1 out of 4656

Number of 4 input LUTs:

Number of IOs:
Number of bonded IOBs:

---------------------------

0%

2 out of 9312

0%

7
7 out of

92

7%

Partition Resource Summary:

---------------------------

No Partitions were found in this design.

---------------------------

================================================
=========================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
-----------------No clock signals found in this design

Asynchronous Control Signals Information:

---------------------------------------No asynchronous control signals found in this design

Timing Summary:
--------------Speed Grade: -4

Minimum period: No path found

Minimum input arrival time before clock: No path found

Maximum output required time after clock: No path found
Maximum combinational path delay: 6.530ns

Timing Detail:
-------------All values displayed in nanoseconds (ns)

================================================
=========================
Timing constraint: Default path analysis
Total number of paths / destination ports: 7 / 1
------------------------------------------------------------------------Delay:
Source:

6.530ns (Levels of Logic = 4)

b (PAD)

Destination:

y (PAD)

Data Path: b to y
Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------IBUF:I->O
LUT3:I0->O
MUXF5:I0->O
OBUF:I->O

1 1.218 0.595 b_IBUF (b_IBUF)

1 0.704 0.000 y_F (N5)
1 0.321 0.420 y (y_OBUF)
3.272

y_OBUF (y)

---------------------------------------Total

6.530ns (5.515ns logic, 1.015ns route)

(84.5% logic, 15.5% route)

================================================
=========================

Total REAL time to Xst completion: 6.00 secs

Total CPU time to Xst completion: 6.17 secs

-->

Total memory usage is 239664 kilobytes

Number of errors :
Number of warnings :
Number of infos

0 ( 0 filtered)
0 ( 0 filtered)
0 ( 0 filtered)

ANALISA DATA

Dari percobaan ketiga yang saya buat adalah rangkaian Multiplekser dengan
menggunakan 4 inputan dan 1 outputan dan 2 selektor sebagai yang mempengaruhi Outputan.
Dimana dalam rangkaian tersebut terdapat 3 buah gerbang logika yaitu gerbang NOT, AND
dan OR.
Pada percobaan 3 ini saya juga memakai model deskripsi behavioral . Keterangan
bagian-bagian listing di xilinx.
KESIMPULAN

Pada tugas ketiga merupakan rangkaian Multiplekser yang terdiri dari gerbang NOT,

AND, dan OR.

Output yang dihasilkan dipengaruhi oleh selektor, jadi apabila kita telah menentukan

selektornya maka outputan akan mengikuti selektor pada inputan.

.IEEE merupakan library tempat menyimpan desain unit IEEE seperti package
std_1164 dan numeric_std.