Department of Computer Science and Electronics

Fac. Of Mathematics and Natural Sciences

Universitas Gadjah Mada, Yogyakarta - Indonesia

Tentang ARM CMSIS

Dr. Agfianto Eko Putra, M.Sc.
http://agfi.staff.ugm.ac.id
agfi68@gmail.com
agfi@ugm.ac.id

Apa itu CMSIS?

The Cortex Microcontroller Software Interface
Standard (CMSIS) is a vendor-independent
hardware abstraction layer for the Cortex-M
processor series and defines generic tool interfaces.
The CMSIS...
enables consistent device support and simple software
interfaces to the processor and the peripherals,
simplifying software re-use,
reducing the learning curve for microcontroller
developers, and
reducing the time to market for new devices.

Cortex Microcontroller Software

Interface Standard

Komponen2 CMSIS (1/4)

CMSIS-CORE: API for the Cortex-M processor core and
peripherals.
It provides at standardized interface for Cortex-M0, CortexM3, Cortex-M4, SC000, and SC300.
Included are also SIMD intrinsic functions for Cortex-M4 SIMD
instructions.

CMSIS-Driver: defines generic peripheral driver

interfaces for middleware making it reusable across
supported devices.
The API is RTOS independent and connects microcontroller
peripherals with middleware that implements for example
communication stacks, file systems, or graphic user
interfaces.

Komponen2 CMSIS (2/4)

CMSIS-DSP: DSP Library Collection with over 60
Functions for various data types: fix-point (fractional
q7, q15, q31) and single precision floating-point (32bit). The library is available for Cortex-M0, Cortex-M3,
and Cortex-M4.
The Cortex-M4 implementation is optimized for the SIMD
instruction set.

CMSIS-RTOS API: Common API for Real-Time operating

systems.
It provides a standardized programming interface that is
portable to many RTOS and enables therefore software
templates, middleware, libraries, and other components that
can work across supported the RTOS systems.

Komponen2 CMSIS (3/4)

CMSIS-Pack: describes with a XML based package
description (PDSC) file the user and device relevant
parts of a file collection (called software pack) that
includes source, header, and library files,
documentation, Flash programming algorithms, source
code templates, and example projects.
Development tools and web infrastructures use the PDSC file
to extract device parameters, software components, and
evaluation board configurations.

CMSIS-SVD: System View Description for Peripherals.

Describes the peripherals of a device in an XML file and can
be used to create peripheral awareness in debuggers or
header files with peripheral register and interrupt definitions.

Komponen2 CMSIS (4/4)

CMSIS-DAP: Debug Access Port.
Standardized firmware for a Debug Unit that connects to
the CoreSight Debug Access Port.
CMSIS-DAP is distributed as separate package and well
suited for integration on evaluation boards.
This component is provided as separate download.

Untuk NUC100 apa yang dibutuhkan?

NUC100.h (device header file)
Interrupt Number Definition
Device Peripheral Access Layer
Provides definitions for all device peripherals. It contains all data structures and
the address mapping for the device specific peripherals

To define the peripherals for the actual device. It can use several other
include files to define the peripherals of the actual devices

startup_NUC100.s (startup_device assembly)

Cortex-M0 startup code and the complete Interrupt Vector Table

system_NUC100.c (system_device)
ARM offer 2 files

core_cm0.h
core_cm0.c

IC Vendor Offer 3files

Definisi Nomor Interupsi pada NUC100

typedef enum IRQn
{
/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
NonMaskableInt_IRQn
= -14, /*!< 2 Non Maskable Interrupt
*/
HardFault_IRQn
= -13, /*!< 3 Cortex-M0 Hard Fault Interrupt
*/
SVCall_IRQn
= -5,
/*!< 11 Cortex-M0 SV Call Interrupt
*/
PendSV_IRQn
= -2,
/*!< 14 Cortex-M0 Pend SV Interrupt
*/
SysTick_IRQn
= -1,
/*!< 15 Cortex-M0 System Tick Interrupt
*/
/****** ARMIKMCU Swift specific Interrupt Numbers ************************************************/
BOD_IRQn
= 0,
WDT_IRQn
= 1,
EINT0_IRQn
= 2,
EINT1_IRQn
= 3,
GPAB_IRQn
= 4,
GPCDE_IRQn
= 5,
PWM0_IRQn
= 6,
PWM1_IRQn
= 7,
TMR0_IRQn
= 8,
TMR1_IRQn
= 9,
TMR2_IRQn
= 10,
TMR3_IRQn
= 11,
UART0_IRQn
= 12,
UART1_IRQn
= 13,
The interrupt number is defined
SPI0_IRQn
= 14,
SPI1_IRQn
= 15,
the NUC1xx.h file
SPI2_IRQn
= 16,
SPI3_IRQn
= 17,
I2C0_IRQn
= 18,
I2C1_IRQn
= 19,
CAN0_IRQn
= 20,
CAN1_IRQn
= 21,
SD_IRQn
= 22,
USBD_IRQn
= 23,
PS2_IRQn
= 24,
ACMP_IRQn
= 25,
PDMA_IRQn
= 26,
I2S_IRQn
= 27,
PWRWU_IRQn
= 28,
ADC_IRQn
= 29,
DAC_IRQn
= 30,
RTC_IRQn
= 31
} IRQn_Type;

in

startup_NUC100Series.s (1/2)
_Vectors DCD
DCD
DCD
DCD
DCD
DCD
DCD
DCD
DCD
DCD
DCD
DCD
DCD
DCD
DCD
DCD

__initial_sp
Reset_Handler
NMI_Handler
HardFault_Handler
0
0
0
0
0
0
0
SVC_Handler
0
0
PendSV_Handler
SysTick_Handler

; Top of Stack
; Reset Handler
; NMI Handler
; Hard Fault Handler
; Reserved
; Reserved
; Reserved
; Reserved
; Reserved
; Reserved
; Reserved
; SVCall Handler
; Reserved
; Reserved
; PendSV Handler
; SysTick Handler

These exception names

are fixed and define the
start of the vector table
for a Cortex-M0

startup_NUC100Series.s (2/2)
; External Interrupts
DCD BOD_IRQHandler
DCD WDT_IRQHandler
DCD EINT0_IRQHandler
DCD EINT1_IRQHandler
DCD GPAB_IRQHandler
DCD GPCDE_IRQHandler
DCD PWMA_IRQHandler
DCD PWMB_IRQHandler
DCD TMR0_IRQHandler
DCD TMR1_IRQHandler
DCD TMR2_IRQHandler
DCD TMR3_IRQHandler
DCD UART02_IRQHandler
DCD UART1_IRQHandler
DCD SPI0_IRQHandler
DCD SPI1_IRQHandler
DCD SPI2_IRQHandler
DCD SPI3_IRQHandler
DCD I2C0_IRQHandler
DCD I2C1_IRQHandler
DCD CAN0_IRQHandler
DCD Default_Handler
DCD Default_Handler
DCD USBD_IRQHandler
DCD PS2_IRQHandler
DCD ACMP_IRQHandler
DCD PDMA_IRQHandler
DCD I2S_IRQHandler
DCD PWRWU_IRQHandler
DCD ADC_IRQHandler
DCD Default_Handler
DCD RTC_IRQHandler

These interrupt names are

fixed and define the start of the
vector table for a Cortex-M0

PWRCON Register (Structure Bit Field SYSCLK_PWRCON_T Data Type)

31

30

29

28

27

26

25

24

19

18

17

16

11

10

RESERVED
23

22

21

20
RESERVED

15

14

13

12

PD_WAIT_CPU
7

PWR_DOWN

PD_WU_STS

WINT_EN

WU_DLY

OSC10K_EN

OSC22M_EN

XTL32K_EN

XTL12M_EN

LSB

MSB

/*---------------------------- Clock Controller ------------------------------*/

typedef struct
{
__IO uint32_t XTL12M_EN:1;
__IO uint32_t XTL32K_EN:1;
__IO uint32_t OSC22M_EN:1;
__IO uint32_t OSC10K_EN:1;
__IO uint32_t WU_DLY:1;
__IO uint32_t WINT_EN:1;
__IO uint32_t INTSTS:1;
__IO uint32_t PWR_DOWN:1;
__IO uint32_t PD_WAIT_CPU:1;
__I uint32_t RESERVE:23;
} SYSCLK_PWRCON_T;

New Data Type

Group Registers for fixed CLK_BA BaseAddr (SYSCLK_T Data

Type)

typedef struct
{
SYSCLK_PWRCON_T
SYSCLK_AHBCLK_T
SYSCLK_APBCLK_T
uint32_t
SYSCLK_CLKSEL0_T
SYSCLK_CLKSEL1_T
SYSCLK_CLKDIV_T
uint32_t
SYSCLK_PLLCON_T
uint32_t
SYSCLK_TREG_T
} SYSCLK_T;

PWRCON;
AHBCLK;
APBCLK;
RESERVED;
CLKSEL0;
CLKSEL1;
CLKDIV;
RESERVED2;
PLLCON;
RESERVED3[3];
TREG;

Register

Offset

PWRCON

CLK_BA + 00

AHBCLK

CLK_BA + 04

APBCLK

CLK_BA + 08

CLKSEL0

CLK_BA + 10

CLKSEL1

CLK_BA + 14

CLKSEL2

CLK_BA + 1C

CLKDIV

CLK_BA_+ 18

PLLCON

CLK_BA + 20

FRQDIV

GCR_BA + 24

Untuk mengakses register...

#define AHB_BASE 0x50000000
#define SYSCLK_BASE (AHB_BASE
+ 0x00200)
#define SYSCLK
((SYSCLK_T *) SYSCLK_BASE)
AHB Modules Space (0x5000_0000 0x501F_FFFF)
0x5000_0000 0x5000_01FF

GCR_BA

System Global Control Registers

0x5000_0200 0x5000_02FF

CLK_BA

Clock Control Registers

0x5000_0300 0x5000_03FF

INT_BA

Interrupt Multiplexer Control Registers

0x5000_4000 0x5000_7FFF

GPIO_BA

GPIO Control Registers

0x5000_8000 0x5000_BFFF

PDMA_BA

SRAM_APB DMA Control Registers

0x5000_C000 0x5000_FFFF

FMC_BA

Flash Memory Control Registers

SYSCLK->PWRCON.XTL12M_EN = 1;

Cortex-M0 Core Registers Access (core_cm0.h)

Function Definition

Core Register

Description

void __enable_irq (void)

PRIMASK = 0

Global Interrupt enable (using the instruction CPSIE i)

void __disable_irq (void)

PRIMASK = 1

Global Interrupt disable (using the instruction CPSID i)

void __set_PRIMASK (uint32_t

value)

PRIMASK = value

Assign value to Priority Mask Register (using the instruction MSR)

uint32_t __get_PRIMASK
(void)

return PRIMASK

Return Priority Mask Register (using the instruction MRS)

void __set_CONTROL
(uint32_t value)

CONTROL = value

Set CONTROL register value (using the instruction MSR)

uint32_t __get_CONTROL
(void)

return CONTROL

Return Control Register Value (using the instruction MRS)

void __set_PSP (uint32_t

TopOfProcStack)

PSP =
TopOfProcStack

Set Process Stack Pointer value (using the instruction MSR)

uint32_t __get_PSP (void)

return PSP

Return Process Stack Pointer (using the instruction MRS)

void __set_MSP (uint32_t

TopOfMainStack)

MSP =
TopOfMainStack

Set Main Stack Pointer (using the instruction MSR)

uint32_t __get_MSP (void)

return MSP

Return Main Stack Pointer (using the instruction MRS)

Cortex-M0 Instruction Access

Function Name

CPU Instruction

Description

void __WFI (void)

WFI

Wait for Interrupt

void __WFE (void)

WFE

Wait for Event

void __SEV (void)

SEV

Set Event

void __ISB (void)

ISB

Instruction Synchronization Barrier

void __DSB (void)

DSB

Data Synchronization Barrier

void __DMB (void)

DMB

Data Memory Barrier

uint32_t __REV (uint32_t value)

REV

Reverse byte order in integer value.

uint32_t __REV16 (uint16_t value)

REV16

Reverse byte order in unsigned short

value.

sint32_t __REVSH (sint16_t value)

REVSH

Reverse byte order in signed short

value with sign extension to integer.

NVIC Setup Function Call

Function Name

Parameter

Description

void NVIC_SetPriorityGrouping (uint32_t

PriorityGroup)

Priority Grouping Value

Set the Priority Grouping (Groups .

Subgroups)

void NVIC_EnableIRQ (IRQn_Type IRQn)

IRQ Number

Enable IRQn

void NVIC_DisableIRQ (IRQn_Type IRQn)

IRQ Number

Disable IRQn

uint32_t NVIC_GetPendingIRQ (IRQn_Type

IRQn)

IRQ Number

Return 1 if IRQn is pending else 0

void NVIC_SetPendingIRQ (IRQn_Type IRQn)

IRQ Number

Set IRQn Pending

void NVIC_ClearPendingIRQ (IRQn_Type IRQn)

IRQ Number

Clear IRQn Pending Status

void NVIC_SetPriority (IRQn_Type IRQn,

uint32_t priority)

IRQ Number, Priority

Set Priority for IRQn

uint32_t NVIC_GetPriority (IRQn_Type IRQn)

IRQ Number

Get Priority for IRQn

uint32_t NVIC_EncodePriority (uint32_t

PriorityGroup, uint32_t PreemptPriority,
uint32_t SubPriority)

IRQ Number, Priority Group, Encode priority for given group,

Preemptive Priority,
preemptive and sub priority
Sub Priority

NVIC_DecodePriority (uint32_t Priority, uint32_t

PriorityGroup, uint32_t* pPreemptPriority,
uint32_t* pSubPriority)

IRQ Number, Priority,

pointer to Priority
Group, pointer to
Preemptive Priority,
pointer to Sub Priority

Decode given priority to group,

preemptive and sub priority

void NVIC_SystemReset (void)

(void)

Resets the System

Memory Map defined in NUC100Series.h

/* Peripheral and SRAM base address */
#define FLASH_BASE
(( uint32_t)0x00000000)
#define SRAM_BASE
(( uint32_t)0x20000000)
#define AHB_BASE
(( uint32_t)0x50000000)
#define APB1_BASE
(( uint32_t)0x40000000)
#define APB2_BASE
(( uint32_t)0x40100000)
/* Peripheral memory map */
#define GPIO_BASE
(AHB_BASE

+ 0x4000)

#define GPIOA_BASE
(GPIO_BASE
)
#define GPIOB_BASE
(GPIO_BASE
+ 0x0040)
#define GPIOC_BASE
(GPIO_BASE
+ 0x0080)
#define GPIOD_BASE
(GPIO_BASE
+ 0x00C0)
#define GPIOE_BASE
(GPIO_BASE
+ 0x0100)
#define GPIO_DBNCECON_BASE (GPIO_BASE
+
0x0180)
#define UART0_BASE
#define UART1_BASE
#define UART2_BASE

(APB1_BASE
(APB2_BASE
(APB2_BASE

+ 0x50000)
+ 0x50000)
+ 0x54000)

#define TIMER0_BASE
#define TIMER1_BASE
#define TIMER2_BASE
#define TIMER3_BASE
#define WDT_BASE
#define SPI0_BASE
#define SPI1_BASE
#define SPI2_BASE
#define SPI3_BASE
#define I2C0_BASE
#define I2C1_BASE
#define RTC_BASE
#define ADC_BASE
#define ACMP_BASE
#define SYSCLK_BASE
#define GCR_BASE
#define INT_BASE
#define FMC_BASE
#define PS2_BASE
#define CAN0_BASE
#define CAN1_BASE
#define C_CAN_BASE

(APB1_BASE + 0x10000)
(APB1_BASE + 0x10020)
(APB2_BASE + 0x10000)
(APB2_BASE + 0x10020)
(APB1_BASE + 0x4000)
(APB1_BASE + 0x30000)
(APB1_BASE + 0x34000)
(APB2_BASE + 0x30000)
(APB2_BASE + 0x34000)
(APB1_BASE + 0x20000)
(APB2_BASE + 0x20000)
(APB1_BASE + 0x08000)
(APB1_BASE + 0xE0000)
(APB1_BASE + 0xD0000)
(AHB_BASE
+ 0x00200)
(AHB_BASE
+ 0x00000)
(AHB_BASE
+ 0x00300)
(AHB_BASE
+ 0x0C000)
(APB2_BASE + 0x00000)
(APB2_BASE + 0x80000)
(APB2_BASE + 0x84000)
(APB2_BASE + 0x88000)

Peripheral Name define its Base Address

#define GPIOA
((GPIO_T *) GPIOA_BASE)
#define GPIOB
((GPIO_T *) GPIOB_BASE)
#define GPIOC
((GPIO_T *) GPIOC_BASE)
#define GPIOD
((GPIO_T *) GPIOD_BASE)
#define GPIOE
((GPIO_T *) GPIOE_BASE)
#define GPIO_DBNCECON
((GPIO_DBNCECON_T *)
GPIO_DBNCECON_BASE)
#define GPIO_BIT_ADDR_BASE (GPIO_BASE + 0x200)
#define UART0
#define UART1
#define UART2
#define TIMER0
#define TIMER1
#define TIMER2
#define TIMER3
#define WDT
#define SPI0
#define SPI1
#define SPI2
#define SPI3

((UART_T *) UART0_BASE)
((UART_T *) UART1_BASE)
((UART_T *) UART2_BASE)
((TIMER_T *) TIMER0_BASE)
((TIMER_T *) TIMER1_BASE)
((TIMER_T *) TIMER2_BASE)
((TIMER_T *) TIMER3_BASE)
((WDT_T *) WDT_BASE)
((SPI_T *) SPI0_BASE)
((SPI_T *) SPI1_BASE)
((SPI_T *) SPI2_BASE)
((SPI_T *) SPI3_BASE)

#define I2C0
#define I2C1
#define I2S
#define RTC
#define ADC
#define ACMP
#define SYSCLK
#define SYS
#define SYSINT
#define FMC
#define PS2
#define CAN
#define USBD

((I2C_T *) I2C0_BASE)
((I2C_T *) I2C1_BASE)
((I2S_T *) I2S_BASE)
((RTC_T *) RTC_BASE)
((ADC_T *) ADC_BASE)
((ACMP_T *) ACMP_BASE)
((SYSCLK_T *) SYSCLK_BASE)
((GCR_T *) GCR_BASE)
((GCR_INT_T *) INT_BASE)
((FMC_T *) FMC_BASE)
((PS2_T *) PS2_BASE)
((CAN_T *) CAN0_BASE)
((USBD_T *) USBD_BASE))