Digital Circuits

BLG231E
Instructor: Dr. Fuat Kucuk

BLG231E DIGITAL CIRCUITS by Fuat Kucuk

These lecture notes have been prepared on the basis

of the course reference book.

BLG231E DIGITAL CIRCUITS by Fuat Kucuk

Five variable map

A five-variable map requires 32 squares. The more variable the more
complex map that we handle.
5 variable map can be assumed to be formed by two four-variable map so
that we can apply the same procedure.
Let us assume A,B,C,D,E are the variables. For the minterms from 0 to 15
(first table), A is 0 and for minterms from 16 to 31, A is 1 (second table).
A=0

A=1
DE

DE
BC

00 01 11 10

BC

00 01 11 10

00 0

00 16 17 19 18

01 4

01 20 21 23 22

11 12 13 15 14

11 28 29 31 30

10 8

10 24 25 27 26

11 10

BLG231E DIGITAL CIRCUITS by Fuat Kucuk

Example: Five variable K-map

Simplify the Boolean function
F(A, B, C, D, E) = (0, 2, 4, 6, 9, 13, 21, 23, 25, 29, 31)
A=0

A=1
DE

DE
BC

00 01 11 10

00 1

01 1

11

10

BC

00 01 11 10

00
A'B'E'
A'BD'E

01

11

10

ACE
ABD'E

F=A'B'E'+BD'E+ACE

BLG231E DIGITAL CIRCUITS by Fuat Kucuk

Dont Care Conditions

In practice, there are applications where the function is not
specied for certain combinations of the input variables. For example,
in a 4-bit BCD code, the outputs are unspecied for the input
combinations between 1010-1111.
Functions that have unspecied outputs for some input
combinations are incompletely specied functions.
The unspecied minterms of a function are called the dont-care
conditions, or simply the dont-cares, and often denoted as Xs.
These dont-care conditions can be used on a map to provide
further simplication of the Boolean expression.
Each X can be assigned an arbitrary value, 0 or 1, to help the
simplication procedure.
BLG231E DIGITAL CIRCUITS by Fuat Kucuk

Example: Dont cares

Simplify the Boolean function f ( w , x, y , z )= (1 , 3, 7, 11 , 15)
that has the dont-care conditions d (w ,x, y , z )= (0 , 2, 5) .

BLG231E DIGITAL CIRCUITS by Fuat Kucuk

Example: Dont cares

Either one of the above expressions satises the conditions stated.
Note that the above 2 expressions represent 2 functions that are
algebraically unequal: each covers different dont-care terms.
We may or may not include any of the Xs, while all the 1s must be
included.
It is also possible to obtain a simplied POS expression using the dontcares. Taking the required Xs with 0s, we can write the complement

F'=z'+wy'
Taking the complent of F again by De Morgan rule

F=z(w '+y)
Because we include dont care minterms 0 ad 2 with the 0s and 5 with
1s
F(w, x, y, z) = z(w' + y) = (1,3,5,7,11, 15)
BLG231E DIGITAL CIRCUITS by Fuat Kucuk

Tabulation (Quine-McCluskey) Method

The map method is not convenient when the number of variables
exceeds 5. That is because the visualization of the adjacency becomes
more and more complicated.
The tabulation method is a systematic process that promises to
result a simplied standard-form of a function.
It can be applied to functions with any number of variables and is
suitable for machine computation because of having algorithmic
process.
The tabulation method was rst formulated by Quine (1952) and
later improved by McCluskey (1956), thus it is also known as the
Quine-McCluskey method.

BLG231E DIGITAL CIRCUITS by Fuat Kucuk

Tabulation (Quine-McCluskey) Method

The simplification steps in this method is as follows:
1. List the minterms with their BCD values.
2. Group minterms according to the number of 1s they contain.

3. Combine any 2 minterms that differ from each other by exactly

one variable.
4. Remove the unmatched variable. Try this for all possible pairs of
minterms.
5. Place a mark to the right of minterms if they have been used in a
match.
6. Repeat the process until no further groups are formed.
7. The sum of unmarked terms results the simplified form of the
function. If any terms may appear twice, cancel one of them.
BLG231E DIGITAL CIRCUITS by Fuat Kucuk

Example: K-map and Table methods

Simplify the Boolean function F(w,x, y, z) = (0, 1, 2, 8, 10, 11, 14, 15)
with a) map (K-map) b) table (Quine-McCluskey) methods.
a) map (K-map) metod
w'x'y'
yz

00 01 11 10
wx
00 1 1
1

x'z'

01

11

10 1

wy

F= x'z'+wy+w'x'y'
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Example: K-map and Table methods

b) table (Quine-McCluskey)

w'x'y'

x'z'
wy
F= x'z'+wy+w'x'y'

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Example: Table methods for five variables

Simplify the Boolean function F(A, B, C, D, E) = (0, 2, 4, 6, 9, 13, 21, 23, 25, 29, 31)
with table method. (it was previously simplified by K-map method.)
Decimal Grouped
indices BCDs
0
00000

2
4

00010
00100

6
9

00110
01001

13
21
25

01101
10101
11001

23
29

10111
11101

31

11111

Matched
indices
0,2
0,4

Matched
indices
0,2,4,6
0,4,2,6

0000
0000

000
000

A'B'E'

2,6
4,6

0010
0010

9,13,25,29
9,25,13,29

101
101

BD'E

9,13
9,25

0101
1001

21,23,29,31
21,29,23,31

111
111

ACE

13,29
21,23
21,29
25,29

1101
1011
1101
1101

23,31
29,31

1111
1111

BLG231E DIGITAL CIRCUITS by Fuat Kucuk

F=A'B'E'+BD'E+ACE

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NAND and NOR implementation

Digital circuits are often built with NAND or NOR gates instead of
using AND and OR gates.
NAND and NOR gates are easier to fabricate with electronic
components and are the basic gates used in all digital logic families.
Therefore, rules and procedures have been developed for the
implementation of Boolean functions given in terms of AND, OR, and
NOT with equivalent NAND and NOR logic diagrams.

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NAND implementation
Inverter x

AND

x'
x
y

xy

x
OR

(x'y')'=x+y
y

Two graphic symbol for NAND gate

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Two-level NAND Implementation

The implementation of Boolean functions with NAND gates
requires that the function be in sum of products form.
Three Ways to Implement of F = AB + CD
The function is implemented with AND and
OR gates.
the AND gates are replaced by
NAND gates and the OR gate is
replaced by an NAND gate with an
OR-invert graph symbol.

the output NAND gate is redrawn with

the AND-invert graph
symbol F = ((AB)'(CD)')'
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Procedure for two level NAND implementation

1. Simplify the function and express it in sum of products.

2. Draw a NAND gate for each product term of the expression that
has at least two literals. The inputs to each NAND gate are the
literals of the term. This constitutes a group of first- level gates.
3. Draw a single gate using the AND-invert or the invert-OR graphic
symbol in the second level, with inputs coming from outputs of
first level gates.

4. A term with a single literal requires an inverter in the first level.

However, if the single literal is complemented, it can be connected
directly to an input of the second level NAND gate.

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Example: NAND implementation

Implement the following Boolean function with NAND gates:
F(x,y,z) = (1,2,3,4,5,7)
Solution:
1.

F = xy' + x'y + z
=[ (xy')'(x'y)'z']'

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Example: NAND implementation

2.

x
y'
x'
y
z

3-4.

x
y'

x'
y
z'
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General Procedure of Multi level NAND implementation

1. Convert all AND gates to NAND gates with AND-invert

graphic symbols.
2. Convert all OR gates to NAND gates with invert-OR graphic
symbols.
3. Check all the bubbles in the diagram. For every bubble that
is not compensated by another small circle along the same
line, insert an inverter (one-input NAND gate) or complement
the input literal.

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Example: Multi level implementation with NANDs

BLG231E DIGITAL CIRCUITS by Fuat Kucuk

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Example: Multi level implementation with NANDs

BLG231E DIGITAL CIRCUITS by Fuat Kucuk

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NOR gate implementation

Inverter x

OR

x'

x+y

AND

Logic Operations
with NOR Gates

(x'+y')'=xy

Two grahic symbols for NOR Gate

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NOR gate implementation

The NOR operation is the dual of the NAND operation.
A two-level implementation with NOR gates requires that the
function be simplified in product of sums. Remember that the
simplified product of sums expression is obtained from the map by
combining the 0's and complementing.

The procedure for converting a multilevel AND-OR diagram to an

all NOR diagram is similar to the one presented for NAND gates.
For the NOR case, we must convert each OR gate to an OR- invert
symbol and each AND gate to an invert-AND symbol. Any bubble
that is not compensated by another bubble along the same line
needs an inverter or the complementation of the input literal.

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NOR gate implementation

Implementing
F =(A + B)(C + D)E
with NOR Gates

Implementing
F =(AB' + A'B)(C + D')
with NOR Gates
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Example:Possible two level implementations

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Example:Possible two level implementations

BLG231E DIGITAL CIRCUITS by Fuat Kucuk

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