Beruflich Dokumente
Kultur Dokumente
December 1992
Features
Pinout
CD4027BMS
TOP VIEW
Q2 1
16 VDD
Q2 2
15 Q1
CLOCK 2 3
14 Q1
RESET 2 4
13 CLOCK 1
K2 5
12 RESET 1
J2 6
11 K1
SET 2 7
10 J1
9 SET 1
VSS 8
Functional Diagram
SET 1
VDD
16
15 Q1
J1 10
K1 11
CLOCK1 13
F/F1
14 Q1
Applications
RESET1 12
SET2
J2
K2
CLOCK2
Description
CD4027BMS is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K masterslave flip-flops. Each flip-flop has provisions for individual J, K,
Set Reset, and Clock input signals. Buffered Q and Q signals
are provided as outputs. This input-output arrangement provides for compatible operation with the Intersil CD4013B dual D
type flip-flop.
RESET 2
1 Q2
F/F2
2 Q2
8
VSS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
7-780
File Number
3302
Specifications CD4027BMS
Absolute Maximum Ratings
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . .
ja
jc
Ceramic DIP and FRIT Package . . . . . 80oC/W
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
o
Maximum Package Power Dissipation (PD) at +125 C
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
PARAMETER
Supply Current
SYMBOL
IDD
IIL
CONDITIONS (NOTE 1)
VDD = 20V, VIN = VDD or GND
IIH
LIMITS
TEMPERATURE
A
A
-55oC
+25oC
-100
nA
+125o
VDD = 20
-1000
nA
-55oC
-100
nA
+25oC
100
nA
+125oC
1000
nA
100
nA
50
mV
-55oC
Output Voltage
VOL15
1, 2, 3
Output Voltage
VOH15
1, 2, 3
VDD = 18V
UNITS
200
+25
+125oC
MAX
VDD = 20
MIN
-
oC
VDD = 18V
Input Leakage Current
GROUP A
SUBGROUPS
IOL5
+25oC
0.53
mA
IOL10
+25oC
1.4
mA
IOL15
+25oC
3.5
mA
IOH5A
+25oC
-0.53
mA
IOH5B
+25oC
-1.8
mA
IOH10
+25oC
-1.4
mA
IOH15
+25oC
-3.5
mA
-2.8
-0.7
0.7
2.8
N Threshold Voltage
VNTH
+25oC
P Threshold Voltage
VPTH
+25oC
+25oC
+25oC
8A
+125oC
8B
Functional
VIL
1, 2, 3
VIH
1, 2, 3
VIL
VIH
7-781
-55oC
+25oC,
+125oC, -55oC
1.5
3.5
1, 2, 3
1, 2, 3
11
Specifications CD4027BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Propagation Delay
Clock To Q, Q
Propagation Delay
Set To Q Reset To Q
Propagation Delay
Set To Q, Reset To Q
Transition Time
SYMBOL
TPHL1
TPLH1
TPLH2
TPHL3
TTLH
TTHL
CONDITIONS (NOTE 1, 2)
GROUP A
SUBGROUPS TEMPERATURE
FCL
LIMITS
MIN
MAX
UNITS
+25oC
300
ns
10, 11
+125oC, -55oC
405
ns
+25oC
300
ns
10, 11
+125oC, -55oC
405
ns
+25 C
400
ns
10, 11
+125oC, -55oC
540
ns
+25oC
200
ns
10, 11
+125oC, -55oC
270
ns
+25oC
3.5
MHz
10, 11
+125oC, -55oC
3.5/1.35
MHz
MIN
MAX
UNITS
30
60
NOTES:
1. VDD = 5V, CL = 50pF, RL = 200K
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
NOTES
1, 2
TEMPERATURE
-55oC,
+25oC
+125oC
VDD = 10V, VIN = VDD or GND
1, 2
-55oC,
+25oC
+125oC
VDD = 15V, VIN = VDD or GND
Output Voltage
VOL
1, 2
1, 2
+125oC
120
+25oC, +125oC,
50
mV
-55oC,
+25oC
-55oC
Output Voltage
VOL
1, 2
+25oC, +125oC,
-55oC
50
mV
Output Voltage
VOH
1, 2
+25oC, +125oC,
-55oC
4.95
Output Voltage
VOH
1, 2
+25oC, +125oC,
-55oC
9.95
IOL5
1, 2
+125oC
0.36
mA
-55oC
0.64
mA
+125oC
0.9
mA
-55oC
1.6
mA
IOL10
IOL15
IOH5A
IOH5B
IOH10
1, 2
1, 2
1, 2
1, 2
1, 2
7-782
+125oC
2.4
mA
-55oC
4.2
mA
+125oC
-0.36
mA
-55oC
-0.64
mA
+125oC
-1.15
mA
-55oC
-2.0
mA
+125oC
-0.9
mA
-55oC
-1.6
mA
Specifications CD4027BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
IOH15
VIL
CONDITIONS
VDD =15V, VOUT = 13.5V
NOTES
TEMPERATURE
MIN
MAX
UNITS
1, 2
+125oC
-2.4
mA
-55oC
-4.2
mA
+25oC, +125oC,
1, 2
-55oC
Input Voltage High
VIH
Propagation Delay
Clock To Q, Q
TPHL1
TPLH1
Propagation Delay
Set To Q, Reset To Q
TPLH2
Propagation Delay
Set To Q, Reset To Q
TPHL3
Transition Time
Input Capacitance
+25oC
130
ns
90
ns
130
ns
+25 C
+25 C
+25 C
90
ns
1, 2, 3
+25oC
170
ns
VDD = 15V
1, 2, 3
+25oC
120
ns
ns
1, 2, 3
+25 C
100
VDD = 15V
1, 2, 3
+25oC
80
ns
VDD = 10V
1, 2, 3
+25oC
MHz
VDD = 15V
1, 2, 3
+25oC
12
MHz
VDD = 5V
1, 2, 3
+25oC
200
ns
1, 2, 3
+25oC
75
ns
VDD = 15V
1, 2, 3
+25oC
50
ns
VDD = 5V
1, 2, 3
+25oC
180
ns
VDD = 10V
1, 2, 3
+25oC
80
ns
1, 2, 3
+25oC
50
ns
VDD = 5V
1, 2, 3
+25oC
140
ns
VDD = 10V
1, 2, 3
+25oC
60
ns
1, 2, 3
+25oC
40
ns
1, 2, 3, 4
+25oC
45
VDD = 10V
1, 2, 3, 4
+25oC
VDD = 15V
1, 2, 3, 4
+25oC
1, 2
+25oC
7.5
pF
VDD = 10V
TRCL
TFCL
1, 2, 3
1, 2, 3
VDD = 15V
Clock Input Rise Or Fall
Time (Note 5)
VDD = 10V
FCL
TW
1, 2, 3
VDD = 15V
Minimum Clock Pulse
Width
VDD = 15V
VDD = 10V
TW
+25oC, +125oC,
-55oC
1, 2, 3
VDD = 10V
TTHL
TTLH
TS
1, 2
VDD = 5V
CIN
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. If more than one unit is cascaded in a parallel clocked operation, trCL should be made less than or equal to the sum of the fixed propagation delay time at 15pF and the transition time of the output driving stage for the estimated capacitive load.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
VDD = 20V, VIN = VDD or GND
7-783
NOTES
TEMPERATURE
MIN
MAX
UNITS
1, 4
+25oC
7.5
Specifications CD4027BMS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
N Threshold Voltage
VNTH
N Threshold Voltage
Delta
VTN
P Threshold Voltage
VTP
P Threshold Voltage
Delta
VTP
Functional
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
1, 4
+25oC
-2.8
-0.2
1, 4
+25oC
1, 4
+25oC
0.2
2.8
1, 4
+25oC
+25oC
VOH >
VDD/2
VOL <
VDD/2
1, 2, 3, 4
+25oC
1.35 x
+25oC
Limit
ns
TPHL
TPLH
VDD = 5V
SYMBOL
DELTA LIMIT
IDD
0.2A
IOL5
IOH5A
GROUP A SUBGROUPS
100% 5004
1, 7, 9
100% 5004
1, 7, 9
100% 5004
1, 7, 9
100% 5004
1, 7, 9, Deltas
100% 5004
1, 7, 9
CONFORMANCE GROUP
PDA (Note 1)
Interim Test 3 (Post Burn-In)
PDA (Note 1)
Final Test
Group A
Group B
Subgroup B-5
Subgroup B-6
Group D
100% 5004
1, 7, 9, Deltas
100% 5004
Sample 5005
Sample 5005
Sample 5005
1, 7, 9
Sample 5005
1, 2, 3, 8A, 8B, 9
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TEST
MIL-STD-883
METHOD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
1, 9
Table 4
7-784
CD4027BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
Static Burn-In 1
Note 1
1, 2, 14, 15
3 - 13
16
Static Burn-In 2
Note 1
1, 2, 14, 15
3 - 7, 9 - 13, 16
4, 7 - 9, 12
5, 6, 10, 11, 16
1, 2, 14, 15
3 - 7, 9 - 13, 16
Irradiation
Note 3
9V -0.5V
50kHz
12, 14, 15
3, 13
25kHz
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V
2. Each pin except VDD and GND will have a series resistor of 4.75K 5%, VDD = 18V 0.5V
3. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V 0.5V
Logic Diagram
RESET
*4(12)
Q
CL
2(14)
MASTER
*6(10)
*5(11)
CL
p
TG
n
p
TG
n
SLAVE
Q
1(15)
K
CL
CL
SET
*7(9)
CL
CL
CL
p
TG
n
p
TG
n
CL
CL
VDD
CL
PROTECTED BY
CMOS PROTECTION
NETWORK
*3(13)
CLOCK
LOGIC DIAGRAM AND TRUTH TABLE FOR CD4027BMS (ONE OF TWO IDENTICAL J-K FLIP-FLOPS)
TRUTH TABLE
NEXT STATE
PRESENT STATE
INPUTS
OUTPUT
OUTPUTS
CL*
No Change
* = Level change
X = Dont care
7-785
VSS
CD4027BMS
25
20
15
10V
10
5
5V
0
10
15
15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
10.0
10V
7.5
5.0
2.5
5V
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
0
-5
-10
-15
-10V
-20
-25
-15V
-30
-5
-10V
10
8
6
4
CD = 15pF
CL = 50pF
SUPPLY VOLTAGE
(VDD) = 15V
10V
102
10V
8
6
4
5V
10
8
6
4
102
4 68
4 68
4 68
103
104
105
INPUT FREQUENCY (fI) (Hz)
4 68
106
-15
2
3
-10
-15V
8
6
4
30
4 68
200
SUPPLY VOLTAGE (VDD) = 5V
150
100
10V
50
15V
107
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
7-786
CD4027BMS
200
SUPPLY VOLTAGE (VDD) = 5V
150
100
10V
15V
50
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
10
15
SUPPLY VOLTAGE (VDD) (V)
20
METALLIZATION:
PASSIVATION:
AL.
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notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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787