Q1) Define Memory Cell.

A1 ) The memory cell is the fundamental building block of computer

memory. The memory cell is an electronic circuit that stores one bit of
binary information and it must be set to store a logic 1 (high voltage
level) and reset to store a logic 0 (low voltage level). Its value is
maintained/stored until it is changed by the set/reset process. The value
in the memory cell can be accessed by reading it.

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Q2 ) Differentiate between RAM and ROM.

A2)
RAM

ROM

Definition Random Access Memory or RAM is

a form of data storage that can be
accessed randomly at any time, in
any order and from any physical
location, allowing quick access and
manipulation.

Read-only memory or ROM is also a

form of data storage that can not be
easily altered or reprogrammed. Stores
instructions that are not necessary for rebooting up to make the computer
operate when it is switched off. They are
hardwired.

Stands for Random Access Memory

Read-only memory

Use RAM allows the computer to

read data quickly to run
applications. It allows reading and
writing.

ROM stores the program required to

initially boot the computer. It only
allows reading.

Volatility RAM is volatile i.e. its contents are

It is non-volatile i.e. its contents are
lost when the device is powered off. retained even when the device is
powered off.
Types The two main types of RAM are
static RAM and dynamic RAM.

The types of ROM include PROM,

EPROM and EEPROM.

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Q3 ) Define Resolution.
A3 ) The performance of ADCs and DACs mainly depends on their
Resolution and Speed.The Resolution of a converter is expressed in the
number of Bit. For an ADC, the Resolution states the number of intervals
or levels which can be divided from a certain analog input range. An n-bit

ADC has the resolution of 1 / 2n. For example, the Resolution of a 16-bit
ADC is 1 / 65536, since 216 = 65536. If the measuring voltage range is
10 V, then this input range can be resolved into 10 V / 65536 = 0.153 mV
precision.
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Q4 ) What is glitch and lock of condition?

A4) An electronics glitch is an undesired transition that occurs before the
signal settles to its intended value. In other words, glitch is an electrical
pulse of short duration that is usually the result of a fault or design error,
particularly in a digital circuit. For example, many electronic components
such as flip-flops are triggered by a pulse that must not be shorter than a
specified minimum duration, otherwise the component may malfunction.
A pulse shorter than the specified minimum is called a glitch.

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LONG ANSWER QUESTIONS!

Q1) Explain TTL logic family.

A1) The full form of TTL is Transistor Transistor Logic. This is a logic
family which is mainly build up of NPN transistors, PN junction diodes and
diffused resistors. The basic building block of this logic family is NAND
gate and there are various subfamilies of this logic gate those are
standard TTL, advanced Schottky TTL, schottky TTL, low power TTL, high
power TTL, fast TTL etc. now to know about this family in a more
descriptive way we will discuss the internal structure and characteristic
parameters of some of its subfamilies.

Standard TTL

The above figure shows the internal structure and characteristics of a

standard TTL NAND gate. The NAND gate of it is a quad two input type.
And it has four circuits of 5400/740. In plain ways the circuit of this type
of TTL operates as follows. The Q1 showed in the figure is a two emitter
NPN transistor. This type is NAND gate is analogous to two transistors
whose base and emitter terminals are joined together. The diodes named
as D2 and D3 are used to limit the input voltages which are negative in
nature.

Low Power TTL

This is a subfamily under the main family. This is named so because lower
power consumption and dissipation is achieved. Though the speed at
which the operation is done is somewhat reduced. The above figure is of a
low power TTL which is made using NAND gates. The NAND gate used in
this is of 74L00 or 54L00 type and is of quad two input type. The
construction of this type of TTL is almost similar to that of standard TTL
except the resistance which is of a higher value. For this increased value
of the resistance the power dissipation of the circuit is lowered.

High Power TTL

Unlike the low power TTL the High power TTL is the high speed edition of
the standard TTL. The speed of operation of this type of TTL is more than
the previously discussed. The power dissipation for this higher than other
previously discussed TTLs. The above diagram is of a high power TTL
NAND gate. The NAND gate is a quad two input of type 74H00 or 54H00.
The above drawn figure is very similar to that of a standard TTL except Q3
transistor and D1 diode combination, which has been replaced by an
arrangement of Q3, Q5 and R5. The speed of operation is higher and the
power dissipation is also higher for this type of TTLs.

Schottky TTL

A
nother TTL subfamily is Schottky TTL. This design was used to speed up
the time of operation. The speed offered by this type of TTL is twice the
speed that is offered by the high power TTL. The power dissipation for
both the TTLs are same and there is no extra power consumption. The
figure above represents the basic NAND based diagram of Schottky TTL.
The circuit diagram is pretty much similar to that of a high power TTL,
here the Q transistor of high power TTL is missing. The Schottky
transistor which is used for this type TTL is nothing but a bipolar transistor
which has its base and collector connected by a schottky diode. This
Schottky TTL is further devided in many parts like low power Schottky,
Advanced low power schottky and advanced Schottky whose discussion
has been avoided due to complexities.

---------------------------------------------------------------------------------Q2 ) Differentiate between Synchronous and Asynchronous

Circuits.
A2 )

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Q3 ) Explain Dual Slope ADC ( Analog Digital Converter ).

A3 ) An Analog-Digital Converter (ADC) is a widely used electronic
component that converts an analog electric signal (usually a voltage) into
a digital representation. The ADCs are at the front-end of any digital
circuit that needs to process signals coming from the exterior world.

Dual-slope ADC, which solves an inherent single-slop problem called

calibration drift, which leads to inaccuracy over time because the
integrator isnt linked to the clock signal (i.e., the sawtooth waveform isnt
synchronized with the counter clock).
A classic dual-slope ADC can be seen below

The analog switch first connects Vin to the integrator. With that, the
integrator starts generating the sawtooth waveform, and the switch
position will remain set at Vin during a fixed number of clock cycles. When
this number of clock cycles is reached, the analog switch moves its
position to allow Vref to enter the integrator. Since Vref is a negative
voltage, the sawtooth waveform goes towards zero, using a number of
clock cycles proportional of the Vin value.
For a better understanding, see Figure 12, where we show the waveform
at the integrator output. So, T1 is fixed, while T2 duration is proportional
to the value of Vin. Vin sets the slope angle: the higher Vin is, the higher
the angle will be.

...

Waveform found at the integrator output

...

T2 = T1 x Vin / Vref.

---------------------------------------------------------------------------------Q4 ) Explain synchronous decade counter or mod 10 counter with

timing diagram.
A4 ) A synchronous counter, in contrast to an asynchronous counter, is
one whose output bits change state simultaneously, with no ripple. The
only way we can build such a counter circuit from J-K flip-flops is to
connect all the clock inputs together, so that each and every flip-flop
receives the exact same clock pulse at the exact same time.

Binary 4-bit Synchronous Down Counter

As synchronous counters are formed by connecting flip-flops together and

any number of flip-flops can be connected or cascaded together to form
a divide-by-n binary counter, the modulos or MOD number still applies
as it does for asynchronous counters so a Decade counter or BCD counter
with counts from 0 to 2n-1 can be built along with truncated sequences.
All we need to increase the MOD count of an up or down synchronous
counter is an additional flip-flop and ANDgate across it.

---------------------------------------------------------------------------------Q5) Design 3 bit up and down synchronous counter with timing

diagram.
A5)
Synchronous 3-bit Up/Down Counter

The circuit above is of a simple 3-bit Up/Down synchronous counter using

JK flip-flops configured to operate as toggle or T-type flip-flops giving a
maximum count of zero (000) to seven (111) and back to zero again.
Then the 3-Bit counter advances upward in sequence (0,1,2,3,4,5,6,7) or
downwards in reverse sequence (7,6,5,4,3,2,1,0).
Generally most bidirectional counter chips can be made to change their
count direction either up or down at any point within their counting
sequence. This is achieved by using an additional input pin which
determines the direction of the count, either Up or Down and the timing
diagram gives an example of the counters operation as this Up/Down
input changes state.
Nowadays, both up and down counters are incorporated into single IC that
is fully programmable to count in both an Up and a Down direction
from any preset value producing a completeBidirectional Counter chip.
Common chips available are the 74HC190 4-bit BCD decade Up/Down
counter, the 74F569 is a fully synchronous Up/Down binary counter and
the CMOS 4029 4-bit Synchronous Up/Down counter.

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