THE BOOLEAN FUNCTION

(Sum of Minterms)

OBJECTIVES
 To simplify the given functions 𝐹1 and 𝐹2 by means of maps.
 To design and construct a circuit with four inputs 𝐴, 𝐵, 𝐶, and 𝐷, and two outputs 𝐹1
and 𝐹2 , implementing the two functions together using a minimum number of ICs.
 To verify that the truth table for 𝐹1 and 𝐹2 obtained from the circuit coincides with
the minterms listed for each function.

MATERIALS
 Alexan Digital Trainer
 one 7400 quad two-input NAND gate
 one 7410 tri three-input NAND gate
 insulated connecting wires
 cutter or scissors

PROBLEM ANALYSIS
The given Boolean functions to be simplified are expressed in sum-of-minterms form:

𝐹1 𝐴, 𝐵, 𝐶, 𝐷 = Σ 0, 1, 4, 5, 8, 9, 10, 12, 13 ,
𝐹2 𝐴, 𝐵, 𝐶, 𝐷 = Σ 3, 5, 7, 8, 10, 11, 13, 15 .
Because both functions consist of four variables, a four-variable K-map must be used for each.
For the first function 𝐹1 , the minterms are marked by 1’s in the map of Figure 8-1. The eight
adjacent squares marked with 1’s can be combined to form the one-literal term 𝐶′. Also, since
the right and left edges of the map touch each other, the remaining single square on the right
edge can be combined with an adjacent square (on the left edge) that has already been used
once. This combination gives the three-literal term 𝐴𝐵′𝐷′. The simplified function then
becomes
𝐹1 = 𝐴𝐵 ′ 𝐷′ + 𝐶 ′ .

The map for the second function 𝐹2 is shown in Figure 8-2. There are eight squares
marked by 1’s, one for each minterm of the function. Four adjacent squares are combined in
the third column to give a two-literal term 𝐶𝐷 . Two of these squares can be combined with
another two squares, this time from the second column, to form a bigger square that can be
represented by the two-literal term 𝐵𝐷 . The remaining two 1’s, when combined, can be
 Laboratory Activity No . 8| 2

represented by the three-literal term 𝐴𝐵′𝐷′ similar to that in 𝐹1 . The simplified function is
the logical sum of the three terms:

𝐹2 = 𝐴𝐵 ′ 𝐷′ + 𝐵𝐷 + 𝐶𝐷 .

CD CD
AB 00 01 11 10 AB 00 01 11 10
𝑚0 𝑚1 𝑚3 𝑚2 𝑚0 𝑚1 𝑚3 𝑚2
00 1 1 00 1
𝑚4 𝑚5 𝑚7 𝑚6 𝑚4 𝑚5 𝑚7 𝑚6
01 1 1 01 1 1
𝑚12 𝑚13 𝑚15 𝑚14 𝑚12 𝑚13 𝑚15 𝑚14
11 1 1 11 1 1
10 𝑚8 𝑚9 𝑚11 𝑚10 10 𝑚8 𝑚9 𝑚11
1 𝑚10
1 1 1 1 1 1

𝑩𝑫
𝑨𝑩′𝑫′ 𝑪′ 𝑨𝑩′𝑫′ 𝑪𝑫

Figure 8-1. Karnaugh map for 𝐹1 Figure 8-2. Karnaugh map for 𝐹2

Figure 8-3 Circuit diagram—with pin assignments and logic gate analysis—
for the joint implementation of both 𝐹1 = 𝐴𝐵 ′ 𝐷′ + 𝐶 ′ and 𝐹2 = 𝐴𝐵 ′ 𝐷′ + 𝐵𝐷 + 𝐶𝐷
 Laboratory Activity No . 8| 3

PROCEDURE
To verify whether the simplified functions of 𝐹1 and 𝐹2 give the correct minterms, a
composite logic diagram is designed as shown Figure 8-3. This circuit—which jointly
implements the two functions 𝐹1 and 𝐹2 —employs all four two-input NAND gates of a 7400
IC as well as all three three-input NAND gates of a 7410 IC.

The circuit is mounted on the digital trainer as shown in Figure 8-4. After all
interconnections are made and double-checked, the trainer is then plugged into a wall outlet.
A joint truth table for 𝐹1 and 𝐹2 is generated based on the logic level outputs of the two
functions, as depicted by LED5 and LED6 of the data status monitor and illustrated in Figure 8-
5. The truth table is shown in Table 8-1.

7400 7410

Figure 8-4. Connection diagram of the circuit in Figure 8-3

RESULTS AND DISCUSSION

As depicted in Figure 8-5 and Table 8-1, LED5 lights up in response to nine input combinations:
0000, 0001, 0100, 0101, 1000, 1001, 1010, 1100, and 1101. These input states correspond to
the following minterms: 𝑚0 , 𝑚1 , 𝑚4 , 𝑚5 , 𝑚8 , 𝑚9 , 𝑚10 , 𝑚12 , and 𝑚13 . Expressed as the sum
of these minterms, the resulting function can be written as

𝐹1 = 𝑚0 + 𝑚1 + 𝑚4 + 𝑚5 + 𝑚8 + 𝑚9 + 𝑚10 + 𝑚12 + 𝑚13 ,

which conforms exactly to the given Boolean function

𝐹1 𝐴, 𝐵, 𝐶, 𝐷 = Σ 0, 1, 4, 5, 8, 9, 10, 12, 13 .
 Laboratory Activity No . 8| 4

SWITCHES DATA STATUS

INPUT INPUT OUTPUT
S1 S2 S3 S4 LED1 LED2 LED3 LED4 LED5 LED6

4 Table 8-1. Truth Table

Corresponding to Figure 8-5
5
INPUT OUTPUT
6 m 𝑨 𝑩 𝑪 𝑫 𝑭𝟏 𝑭𝟐

7 0 0 0 0 0 1 0
1 0 0 0 1 1 0
8 2 0 0 1 0 0 0
3 0 0 1 1 0 1
9
4 0 1 0 0 1 0
5 0 1 0 1 1 1
10
6 0 1 1 0 0 0
11 7 0 1 1 1 0 1
8 1 0 0 0 1 1
12 9 1 0 0 1 1 0
10 1 0 1 0 1 1
13
11 1 0 1 1 0 1
14 12 1 1 0 0 1 0
13 1 1 0 1 1 1
15 14 1 1 1 0 0 0
D1 D2 D3 D4 IN1 IN2 IN3 IN4 IN5 IN6 15 1 1 1 1 0 1

Figure 8-5. Output diagram of 𝐹1 and 𝐹2

 Laboratory Activity No . 8| 5

Similarly, because LED6 is ON for the input combinations 0011, 0101, 0111, 1000, 1010, 1011,
1101, and 1111, which corresponds to the eight minterms 𝑚3 , 𝑚5 , 𝑚7 , 𝑚8 , 𝑚10 , 𝑚11 , 𝑚13 ,
and 𝑚15 , this output function is represented by

𝐹2 = 𝑚3 + 𝑚5 + 𝑚7 + 𝑚8 + 𝑚10 + 𝑚11 + 𝑚13 + 𝑚15 ,

which again, conforms exactly to the given Boolean function

𝐹2 𝐴, 𝐵, 𝐶, 𝐷 = Σ 3, 5, 7, 8, 10, 11, 13, 15 .

These equivalences imply that the two simplified functions obtained by means of maps are
indeed both valid. Additionally, we can also verify (theoretically) the validity of the simplified
functions by generating their truth tables as shown in Table 8-2, and then comparing the truth
values for 𝐹1 and 𝐹2 to the desired minterms. Indeed, the last two columns of the table
below are exactly the same as the last two columns of Table 8-1.

Table 8-2. Truth Table for 𝐹1 = 𝐴𝐵 ′ 𝐷′ + 𝐶′ and

𝐹2 = 𝐴𝐵 ′ 𝐷′ + 𝐵𝐷 + 𝐶𝐷

𝑨 𝑩 𝑪 𝑫 𝑩′ 𝑪′ 𝑫′ 𝑨𝑩′𝑫′ 𝑩𝑫 𝑪𝑫 𝑭𝟏 𝑭𝟐
0 0 0 0 1 1 1 0 0 0 1 0
0 0 0 1 1 1 0 0 0 0 1 0
0 0 1 0 1 0 1 0 0 0 0 0
0 0 1 1 1 0 0 0 0 1 0 1
0 1 0 0 0 1 1 0 0 0 1 0
0 1 0 1 0 1 0 0 1 0 1 1
0 1 1 0 0 0 1 0 0 0 0 0
0 1 1 1 0 0 0 0 1 1 0 1
1 0 0 0 1 1 1 1 0 0 1 1
1 0 0 1 1 1 0 0 0 0 1 0
1 0 1 0 1 0 1 1 0 0 1 1
1 0 1 1 1 0 0 0 0 1 0 1
1 1 0 0 0 1 1 0 0 0 1 0
1 1 0 1 0 1 0 0 1 0 1 1
1 1 1 0 0 0 1 0 0 0 0 0
1 1 1 1 0 0 0 0 1 1 0 1
 Laboratory Activity No . 8| 6

CONCLUSION

Based on the results of this experiment, the following conclusions can be drawn:

 The map method is useful in obtaining a simplified expression in sum-of-products form

of a given Boolean function expressed in sum-of-minterms form.

 The Boolean function 𝐹1 𝐴, 𝐵, 𝐶, 𝐷 = Σ 0, 1, 4, 5, 8, 9, 10, 12, 13 is equivalent to

𝐹1 𝐴, 𝐵, 𝐶, 𝐷 = 𝐴𝐵 ′ 𝐷′ + 𝐶′ , while 𝐹2 𝐴, 𝐵, 𝐶, 𝐷 = Σ 3, 5, 7, 8, 10, 11, 13, 15 is
′ ′
equivalent to 𝐹2 𝐴, 𝐵, 𝐶, 𝐷 = 𝐴𝐵 𝐷 + 𝐵𝐷 + 𝐶𝐷 .