DON’T CARE CONDITION

OBJECTIVES
 To obtain the truth table of a given Boolean function using the proper don’t-care
conditions.
 To use don’t-care conditions on a K-map to provide further simplification of the
Boolean expression.
 To design and construct a circuit that implements the simplified Boolean expression.
 To verify that the circuit’s logic level outputs coincide with the truth table.

MATERIALS
 Alexan Digital Trainer
 one 7400 quad two-input NAND gate
 insulated connecting wires
 cutter or scissors

PROBLEM ANALYSIS
The desired logic circuit implements the Boolean function

𝐹 = 𝐴′ 𝐶 + 𝐴𝐶′𝐷′
If we assume that all the combinations of the values for the variables 𝐴, 𝐶, and 𝐷 of the
function are valid, then the resulting truth table for 𝐹 is the one depicted in Table 11-1.

Table 11-1. Truth Table for 𝐹 = 𝐴′ 𝐶 + 𝐴𝐶′𝐷′

𝑨 𝑪 𝑫 𝑨′ 𝑪′ 𝑫′ 𝑨′𝑪 𝑨𝑪′𝑫′ 𝑭 = 𝑨′ 𝑪 + 𝑨𝑪′𝑫′

0 0 0 1 1 1 0 0 0
0 0 1 1 1 0 0 0 0
0 1 0 1 0 1 1 0 1
0 1 1 1 0 0 1 0 1
1 0 0 0 1 1 0 1 1
1 0 1 0 1 0 0 0 0
1 1 0 0 0 1 0 0 0
1 1 1 0 0 0 0 0 0
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The problem specifies, however, that the circuit input combination 𝐴 = 𝐶 = 1 can never
occur. This implies that the input combinations 110 and 111 are both invalid. Hence, 𝐹 has an
unspecified output for such combinations and so we simply don’t care what value is assumed
by the function for these unspecified minterms 𝑚6 and 𝑚7 . Now using these don’t-care
conditions, we obtain a revised truth table for 𝐹 as depicted in Table 11-2, and a
corresponding K-map, as shown in Figure 11-1.

Table 11-1. Revised Truth Table

for 𝐹 = 𝐴′ 𝐶 + 𝐴𝐶′𝐷′ BD
A 00 01 11 10
𝑨 𝑪 𝑫 𝑭 = 𝑨′ 𝑪 + 𝑨𝑪′𝑫′ 𝑚0 𝑚1 𝑚3 𝑚2
0 0 0 1 1
0 0 0 0
𝑚6
0 0 1 0 1 𝑚4 𝑚5 𝑚7
1 0 X X
0 1 0 1
0 1 1 1
𝑨𝑫′ 𝑪
1 0 0 1
1 0 1 0 Figure 11-1. Obtaining a
1 1 0 X simpler expression for 𝐹 using
1 1 1 X don’t-care conditions

As illustrated in the K-map of Figure 11-1, the don’t-care conditions represented by the
X’s in the map can be used to further simplify the given Boolean expression. In particular, since
the don’t-care minterms may be assumed to be either 0 or 1, we can choose to include both of
them with the 1’s to yield the simplest expression

𝐹 = 𝐴𝐷 ′ + 𝐶
or in sum-of-minterms form, 𝐹 = Σ 2, 3, 4, 6, 7 . In this new function, one literal is dropped
from each term of the original Boolean expression consequently minimizing the number of
gates required to implement the circuit.

PROCEDURE
A circuit that implements the simplified Boolean function 𝐹 = 𝐴𝐷′ + 𝐶 can be designed and
constructed using all four two-input NAND gates of a 7400 IC. The logic diagram of such circuit
is shown in Figure 11-2 and the corresponding connection diagram in Figure 11-3.
 Laboratory Activity No . 11| 3

Figure 11-2 Circuit diagram—with pin assignments and logic gate

analysis—for the implementation of 𝐹 = 𝐴𝐷′ + 𝐶 a single 7400
quad two-input NAND gate

7400

Figure 11-3. Connection diagram of the circuit in Figure 11-2

 Laboratory Activity No . 11| 4

The circuit of Figure 11-2 is mounted on the digital trainer in accordance with Figure 11-
3. After all pin connections are double-checked and power is supplied to the trainer, the ON-
OFF state of LED4 is monitored for all eight possible input combinations. The results are then
recorded in Figure 11-4 and correspondingly interpreted in Table 11-3.

RESULTS AND DISCUSSION

SWITCHES DATA STATUS

INPUT INPUT OUT
S1 S2 S3 LED1 LED2 LED3 LED4

0
Table 11-3. Truth Table
Corresponding to Figure 11-4
1

INPUT OUTPUT
2 D1 D2 D3 IN4

𝑨 𝑩 𝑫 𝑭
3
0 0 0 0
4 0 0 1 0
0 1 0 1
5
0 1 1 1
1 0 0 1
6
1 0 1 0
7 1 1 0 1
1 1 1 1
D1 D2 D3 IN1 IN2 IN3 IN4

Figure 11-4. Output diagram of 𝐹

We see from the results above that Table 11-3 is almost similar to Table 11-2 except
that the X’s corresponding to the don’t-care minterms are now converted into 1’s of the
function. Again, since the input combinations 110 and 111 are both invalid, or will never occur,
then we don’t care whatever output value the Boolean function takes with respect to such
combinations. What we do care about is choosing whether to include the X’s with the 1’s or
with the 0’s so that we obtain the simplest Boolean expression that satisfies the conditions
stated in the problem.
 Laboratory Activity No . 11| 5

CONCLUSION

From the results of this experiment, it can be deduced that:

 The Boolean function 𝐹 = 𝐴′ 𝐶 + 𝐴𝐶 ′ 𝐷′ , with don’t-care condition 𝑑 = Σ 6, 7 , can

be simplified into 𝐹 = 𝐴𝐷′ + 𝐶 , or in sum-of-minterms form, 𝐹 = Σ 2, 3, 4, 6, 7 .

 The simplified Boolean expression 𝐹 = 𝐴𝐷′ + 𝐶 can be implemented using all four
two-input NAND gates of a 7400 IC.

 The simplification process adapted in this experiment is indeed valid because the logic
level outputs of the simplified function 𝐹 = 𝐴𝐷′ + 𝐶 coincide with the expected or
required truth values.