Beruflich Dokumente
Kultur Dokumente
DesigningofAutomaticTrafficLightControllerinRoadsandRailwaysTransportSystemforControllingPurpose
Strictly as per the compliance and regulations of :
2013. Mr. Prashant Kumar, " FARSE " . This is a research/review paper, distributed under the terms of the Creative Commons
Attribution-Noncommercial 3.0 Unported License http://creativecommons.org/licenses/by-nc/3.0/), permitting all non commercial
use, distribution, and reproduction in any medium, provided the original work is properly cited.
I.
Introduction
Year 2 013
Year 2 013
Year 2 013
Electronics-This
Concepts
of
Digital
AutomaticTraffic Light Controller System is based on the
concept of Digital Electronics which shows the Roads
Traffic Light System as Combinational Circuit. This
system has arisen the concept of Four Direction Roads
and the controlling of Roads in a Sequence Manner.
This system is based on the designing of this four
direction based Traffic Light Controller.
It also shows the Railway Traffic Light Controller
System as Sequential Circuit which can be restart as
Hazard and Accidental Problems. The main purpose for
designing this circuit is that the system has arisen on
four direction zone which shows if any hazard problem
created on any direction as based on the designing of
Traffic Light Controller. This System can restart that zone
due to Hazard Problems as maintaining the Railway
System in Automatic Controlling Based Traffic Light
Controller System.
Abbreviations used in Truth Table
Year 2 013
4
2
NG
NY
NR
WG
WY
WR
SG
SY
SR
EG
EY
ER
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
1
1
1
1
1
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
0
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
1
1
1
1
1
1
0
0
0
NG
NY
NR
WG
WY
WR
SG
SY
SR
EG
EY
ER
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
1
0
0
0
1
NG
NY
NR
WG
WY
WR
SG
SY
SR
EG
EY
ER
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
0
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
1
0
0
0
1
NG
NY
NR
WG
WY
WR
SG
SY
SR
EG
EY
ER
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Year 2 013
Year 2 013
6
2
Advantages
Free
Very complete libraries of components
Multiple testing, designing and debug possibilities.
Lots of aid tools.
1.
Disadvantages
Very unstable
2.
3.
4.
5.
6.
7.
8.
9.
Sub-micron,
deep-submicron,
technology support.
nanoscale
Year 2 013
Observation of output after connecting the chip with the output LEDs and input clocks
Year 2 013
8
2
Year 2 013
VERILOG HDL Design Simulation
II.
2.
3.
Acknowledgement
4.
5.
Year 2 013
6.
7.
10
2
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
Year 2 013
11
Year 2 013