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UNIT 1
PART A
1.
2.
3.
4.
5.
6.

What are the different operating regions for an MOS transistor? (MAY/JUNE 2012)
What is layout design rule? (or) What is the objective of layout rules(NOV/DEC-2012)
List the various issues in Technology-CAD (MAY/JUNE 2013)
Define the lambda layout rules (MAY/JUNE 2013)
List the various issues in Technology-CAD (MAY/JUNE 2013)
Why the tunneling current is higher for NMOS transistors than PMOS transistor with silica
gate? (NOV/DEC-2012)
7. Draw the IV characteristics of MOS transistor (MAY/JUNE 2012)
8. Determine whether an nMOS transistor with a threshold voltage of 0.7 Vis operating in the
saturation region if VGS = 2 V and VDS= 3V.(NOV/DEC 2011)
9. Write down the equation for describing the channel length modulation effect in NMOS
transistors. (NOV/DEC 2011)
10. Draw the Energy band diagrams of the components that makeup the MOS system.
(APRIL/MAY 2011).
11. What are the non-ideal I-V effects? ( MAY/JUNE 2014)
12. Discuss about two layout design rule. (MAY/JUNE 2014)
13. What is meant by body effect? .(NOV/DEC 2014)
14. What is the need of design rules? .(NOV/DEC 2014)
PART B
1. Explain in detail about the ideal I-V characteristics of a NMOS and PMOS device.
(MAY/JUNE 2013)(NOV/DEC 13)
(OR)
Discuss in detail with necessary equations the operation of MOSFET and its current- voltage
characteristics (April/May-2011)
(OR)
Derive the drain current of MOS device in different operating regions. .(NOV/DEC 2014)
2. Explain in detail about the non ideal I-V characteristics of a NMOS and PMOS device.
(MAY/JUNE 2013)(NOV/DEC 13)
(OR)
Explain the second order effects in detail
3. Explain about C-V characteristics of a MOS transistor( MAY/JUNE 2014)
4. Explain about CMOS process enhancements. (April/May-2011) (Nov/Dec 2011)
(MAY/JUNE 14) (NOV/DEC 2014)
5. Explain about various CMOS Technologies. (Nov/DEC-2012)
i.
n-well process (n-tub process)
ii.
Silicon-on-Insulator (SOI) Process:
(OR)
Explain in detail with neat diagram the fabrication process of an nMOS transistor
(April/May-2011) (Nov/DEC-2011)
(OR)
Describe with neat diagram the well and channel formation in CMOS process(NOV/DEC
2014)
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6. Explain about Layout Design Rules.(MAY/JUNE 14) (April/May-2011) (MAY/JUNE

2012) ( MAY/JUNE 2014)
7. Explain about DC transfer characteristics (Nov/DEC-2012) (Nov/Dec 2011) (May/June2012) (May/June 2013) ( MAY/JUNE 2014)
NOTE: * ITALICED ARE VERY IMPORTANT QUESTIONS
**BOLDED ARE QUESTION KEYWORDS

UNIT 2
PART A
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.

13.
14.
15.

Define Elmore delay model (May/June-2010) (NOV/DEC 2014)

Define parasitic delay (Apr/May-11)
Define branching effort (Nov/Dec-11)
What is static power dissipation (Nov/Dec-12)
What is short circuit power dissipation (May/June-11)
Define design margin (May/June-13) ( MAY/JUNE 2014)
Express the TPHL & TPLH in terms of Cload (Apr/May-11)
How do you define the term device modeling (May/June-13)
Give the effect of supply voltage and temperature variation on the CMOS system
performance (Nov/Dec-12)
Draw the equivalent circuit structure of level 1 MOSFET model in SPICE (May/June-12)
Brief about the variation of fringing field factor with the interconnect geometry (May/june-12)
Write the expression for the logical effort and parasitic delay of n input NOR gate (Nov/Dec-11)
Why does interconnect increase the circuit delay (Nov/Dec-11)
List different types of scaling (Nov/Dec-14)
Define transistor sizing problem. ( MAY/JUNE 2014)

PART B
1. Discuss in detail about the resistive and capacitive delay estimation of a CMOS inverter
circuit(MAY/JUNE 2013) (Nov/Dec-14)
2. Explain the static and dynamic power dissipation in CMOS circuits with necessary
diagram and expressions(Nov/Dec-11) ( MAY/JUNE 2014)
3. Give a brief account on interconnect. ( MAY/JUNE 2014) (Nov/Dec-14)
4. Give a brief account on design margin (Nov/Dec-11)
5.
Explain the different factors that affect reliability of CMOS chips and Explain the circuit
pitfalls that affect reliability of CMOS chips (Nov/dec-12) (MAY/JUNE 2013) (Nov/Dec-11)
.
6. Explain in detail about the scaling concept (MAY/JUNE 2013) (Nov/Dec-14)
(or)
7. Discuss the principle of constant and lateral field scaling. Write the effect of above scaling
methods on device characteristics. (Nov/dec-12) (Apr/May-11) (Nov/Dec-11)
8. Discuss the mathematical equations that can be used to model the drain current and
diffusion capacitance of MOS transistors. (Nov/dec-12)
(or)
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Explain the device models and device characteristics (MAY/JUNE 2012) ( MAY/JUNE 2014)
9. Give brief notes on logical effort and transistor sizing. (Nov/dec-12) (MAY/JUNE 2013)
10. Explain the SPICE tutorial in detail(MAY/JUNE 2012) ( MAY/JUNE 2014)
NOTE: * ITALICED ARE VERY IMPORTANT QUESTIONS
**BOLDED ARE QUESTION KEYWORDS
*** For device model, device characteristics, spice tutorial refer class notes.

UNIT 5
PART A

1.
2.
3.
4.
5.
6.

Design a 1-Bit adder using verilog module.(Nov/Dec 2012)

Write an example for implicit continuous assignment.(Nov/Dec 2012)
What are gate primitives in multiple input gates? [MAY/JUNE-13]
What is transport delay model?[APRIL/MAY-11 & MAY/JUNE-12]
What is sub-program overloading? [APRIL/MAY-11]
What are the delay specification available in verilog HDL for modeling a logic gate
[NOV/DEC-12]
7. Write a verilog module for half adder using dataflow modeling? [NOV/DEC-11]
8. Give the comparison between structural and switch-level modeling? [MAY/JUNE-13]
PART B
9. Explain the operators used and also Explain various features of Data flow Modeling
10. Explain various features of gate level modeling (April/May-2011) (May/ June 2013)
11. Explain the features of Behavioral modeling. (Nov/Dec 2012) (May/ June 2013)
12. i. Write the Program for 2 to 4 decoder circuit using Data Flow Modeling (Nov/Dec 2012)
ii. Write the Program for 2 to 4 decoder using Gate-Level modeling: [MAY/JUNE-12]
13. Write the Program for 4 to 1 multiplexer using Gate-level modeling (Nov/Dec 2012),
(May/ June 2013) (Nov/Dec 2011) (NOV/DEC 2014)
14. Write the verilog Program for 1X8 de multiplexer using behavioral modeling (May/ June 2013)
15. Write the verilog Program for priority encoder circuit using gate level modeling (May/
June 2013) (May/ June 2014)
16. Write the verilog Program for full adder using gate level modeling[MAY/JUNE-12]
17. Write the verilog Program for ripple carry adder using gate level modeling
18. Write the verilog Program for equality detector using the modeling(May/ June 2014)
19. Write the verilog Program for comparator using the modeling(May/ June 2013)
[MAY/JUNE-12]
20. Explain the different timing controls available in the verilog HDL(Nov/Dec 2012)
21. Write the verilog Program for D flipflop or D latch. (Nov/Dec 2011)
NOTE: * ITALICED ARE VERY IMPORTANT QUESTIONS
**BOLDED ARE QUESTION KEYWORDS
*** For more programs refer class notes and material. Study all the
programs, Circuit diagrams in all modelling.

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UNIT 4
PART A
1. List the design guidelines for i d d q testing. [April/may 2011]
2. What are t he fact ors t hat cause t iming failures? [May/June 2012]
3. What are t he advant age o f a sing le st uck at fault [May/June 2012]
4. List the basic types of cmos testing. [May/june 2013]
5. What is meant by logic verification? [May/june 2013]
6.What are the stages at which a chip can be tested? [November/December 2012]
7.State the objective of functionality test. [November/December 2011.]
8.What are the test fixtures required to test a chip? [Nov/Dec 2011.] (May/June 14)
9.What is the need for testing. (May/June 14)
10. Mention different types of CMOS testing techniques. (NOV/DEC 2014)
11. What is a tester, test fixture and handler?.(NOV/DEC 2014)

PART-B
1. Explain The Fault Simulation Methods? (Nov/Dec 12)
2. Explain the design for testability (May/June 13)
(i) Ad-Hoc Testing
(ii) Scan Design Techniques (Nov/Dec 12) (Apr/May 11) (May/June 12) (Nov/Dec 11)
(NOV/DEC 2014)
(iii)Built-In Self-Test (or) BIST process (Nov/Dec 12) (Apr/May 11) (NOV/DEC 2014)
3. Explain the Boundary Scan Technique (May/June 13) (May/June 14)
4. Explain Silicon debug principle. (Nov/Dec 12) (May/June 13) (May/June 12) (May/June 14)
5. Explain the manufacturing test principles in detail. (Nov/Dec 11) (NOV/DEC 2014)

NOTE: * ITALICED ARE VERY IMPORTANT QUESTIONS

**BOLDED ARE QUESTION KEYWORDS

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UNIT 3
PART A
1.
2.
3.
4.
5.
6.
7.
8.

Write a note on CMOS transmission gate logic. (Apr/May 11)

What is Differential flip-flops? (Nov/Dec 11)
What is synchronizers? (May/June 13) (May/June 14)
Mention the qualities of an ideal sequencing method. (Nov/Dec 12)
List the various power losses in CMOS circuits. (May/June 13)
Implement a 2:1 multiplexer using pass transistor. (Nov/Dec 13)
State any two criteria for low power logic design (May/June-14)
Differentiate latch and flip flop(NOV/DEC 2014)

PART-B
1. Explain the Static CMOS? (May/June 13)
2. Explain the sequencing Dynamic Circuits(Nov/Dec 12) (May/June 13) (Nov/Dec 11)
(or)
Explain the domino and dual rail domino logic with neat diagram (NOV/DEC 2014)
3. Explain the Pass-Transistor Circuits (Apr/May 11) (Nov/Dec 13)
4. Explain the Sequencing Static Circuits.
5. Explain the following: (May/June-14) (NOV/DEC 2014)
(i) Pulsed Latches(Nov/Dec 12)
(ii) Resettable Latches and Flip-Flops (Nov/Dec 12)
(iii)Enabled Latches and Flip-Flops
(iv) Klass Semidynamic Flip-Flop (SDFF)
6. Describe the different methods for reducing static and dynamic power dissipation
(or)
State low power circuit design. (Nov/Dec 12) (NOV/DEC 2014)

NOTE: * ITALICED ARE VERY IMPORTANT QUESTIONS

**BOLDED ARE QUESTION KEYWORDS

HINT
*STUDY THE UNITS IN BELOW ORDER
5TH,4TH,1ST,2ND,3RD,
**ATTEND ALL THE 5 UNIT QUESTIONS.

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